drivers/intel/fsp2_0: add FSP TempRamInit & TempRamExit API support

FSP v2.0 Specification adds APIs TempRamInit & TempRamExit for
Cache-As-Ram initialization and teardown.  Add fsp2_0 driver
support for TempRamInit & TempRamExit APIs.

Verified on Intel Leaf Hill CRB and confirmed that Cache-As-Ram
is correctly set up and torn down using the FSP v2.0 APIs
without coreboot implementation of CAR init/teardown.

Change-Id: I482ff580e1b5251a8214fe2e3d2d38bd5f3e3ed2
Signed-off-by: Brenton Dong <brenton.m.dong@intel.com>
Reviewed-on: https://review.coreboot.org/17062
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/arch/x86/postcar.c

@@ -18,9 +18,14 @@
 #include <main_decl.h>
 #include <program_loading.h>
 #include <soc/intel/common/util.h>
+#include <fsp/util.h>
 
 void main(void)
 {
+	/* Call TempRamExit FSP API if enabled. */
+	if (IS_ENABLED(CONFIG_FSP_CAR))
+		fsp_temp_ram_exit();
+
 	console_init();
 
 	/* Recover cbmem so infrastruture using it is functional. */