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soc/intel/xeon_sp: Reserve MMIO range for VTd BAR dynamically

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vtd_probe_bar_size is used to decide the BAR size.

TEST=Build and boot on intel/archercity CRB

Change-Id: Ie45dd29e386cbfcb136ce2152aba2ec67757ee3c
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82431
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Shuo Liu 2024-05-15 04:32:08 +08:00 committed by Lean Sheng Tan
parent bcd2473766
commit 0a6f5188e8
3 changed files with 22 additions and 4 deletions
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2
src/soc/intel/xeon_sp/include/soc/chip_common.h
View File

@ -90,4 +90,6 @@ bool is_cxl_domain(const struct device *dev);
void unlock_pam_regions(void);
size_t vtd_probe_bar_size(struct device *dev);
#endif /* _CHIP_COMMON_H_ */

17
src/soc/intel/xeon_sp/uncore.c
View File

@ -51,6 +51,20 @@ enum {
NUM_MAP_ENTRIES
};
size_t vtd_probe_bar_size(struct device *dev)
{
uint32_t id = pci_read_config32(dev, PCI_VENDOR_ID);
assert(id == (PCI_VID_INTEL | (MMAP_VTD_CFG_REG_DEVID << 16)));
uint32_t val = pci_read_config32(dev, VTD_BAR_CSR);
pci_write_config32(dev, VTD_BAR_CSR, (uint32_t)(-4 * KiB));
size_t size = (~(pci_read_config32(dev, VTD_BAR_CSR) & ((uint32_t)(-4 * KiB)))) + 1;
assert(size != 0);
pci_write_config32(dev, VTD_BAR_CSR, val);
return size;
}
static struct map_entry memory_map[NUM_MAP_ENTRIES] = {
[TOHM_REG] = MAP_ENTRY_LIMIT_64(VTD_TOHM_CSR, 26, "TOHM"),
[MMIOL_REG] = MAP_ENTRY_BASE_32(VTD_MMIOL_CSR, "MMIOL"),
@ -211,7 +225,8 @@ static void mc_add_dram_resources(struct device *dev, int *res_count)
mc_report_map_entries(dev, &mc_values[0]);
if (mc_values[VTDBAR_REG]) {
res = mmio_range(dev, VTD_BAR_CSR, mc_values[VTDBAR_REG], 8 * KiB);
res = mmio_range(dev, VTD_BAR_CSR, mc_values[VTDBAR_REG],
vtd_probe_bar_size(dev));
LOG_RESOURCE("vtd_bar", dev, res);
}

7
src/soc/intel/xeon_sp/uncore_acpi.c
View File

@ -272,12 +272,13 @@ static unsigned long acpi_create_drhd(unsigned long current, struct device *iomm
printk(BIOS_DEBUG, "[Hardware Unit Definition] Flags: 0x%x, PCI Segment Number: 0x%x, "
"Register Base Address: 0x%x\n",
DRHD_INCLUDE_PCI_ALL, pcie_seg, reg_base);
current += acpi_create_dmar_drhd_4k(current, DRHD_INCLUDE_PCI_ALL,
pcie_seg, reg_base);
current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL,
pcie_seg, reg_base, vtd_probe_bar_size(iommu));
} else {
printk(BIOS_DEBUG, "[Hardware Unit Definition] Flags: 0x%x, PCI Segment Number: 0x%x, "
"Register Base Address: 0x%x\n", 0, pcie_seg, reg_base);
current += acpi_create_dmar_drhd_4k(current, 0, pcie_seg, reg_base);
current += acpi_create_dmar_drhd(current, 0, pcie_seg, reg_base,
vtd_probe_bar_size(iommu));
}
// Add PCH IOAPIC