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mb/asus/p8z77-m: Update USB current map to match vendor

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This board has used the USB current map from asus/p8z77-m_pro since it
first landed in coreboot, which actually doesn't match vendor firmware.
Apply values obtained from hardware while running vendor firmware
to both native and MRC config.

Change-Id: I7ce13493c3ecac8154460c1fedf05e2d70a8e394
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82756
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Keith Hui
2024-05-31 23:19:40 -04:00
committed by Martin L Roth
parent 51a57eb5ea
commit 0aa069fb10
2 changed files with 23 additions and 7 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
src/mainboard/asus/p8x7x-series/variants/p8z77-m/early_init.c
View File

@@ -14,16 +14,16 @@
const struct southbridge_usb_port mainboard_usb_ports[] = {
/* {enable, current, oc_pin} */
{1, 2, 0}, /* Port 0: USB3 front internal header, top */
{1, 2, 0}, /* Port 1: USB3 front internal header, bottom */
{1, 8, 0}, /* Port 0: USB3 front internal header, top */
{1, 8, 0}, /* Port 1: USB3 front internal header, bottom */
{1, 2, 1}, /* Port 2: USB3 rear, top */
{1, 2, 1}, /* Port 3: USB3 rear, bottom */
{1, 2, 2}, /* Port 4: USB2 rear, PS2 top */
{1, 2, 2}, /* Port 5: USB2 rear, PS2 bottom */
{1, 2, 3}, /* Port 6: USB2 rear, ETH, top */
{1, 2, 3}, /* Port 7: USB2 rear, ETH, bottom */
{1, 2, 4}, /* Port 8: USB2 internal header USB910, top */
{1, 2, 4}, /* Port 9: USB2 internal header USB910, bottom */
{1, 9, 4}, /* Port 8: USB2 internal header USB910, top */
{1, 9, 4}, /* Port 9: USB2 internal header USB910, bottom */
{1, 2, 6}, /* Port 10: USB2 internal header USB1112, top */
{1, 2, 5}, /* Port 11: USB2 internal header USB1112, bottom */
{1, 2, 5}, /* Port 12: USB2 internal header USB1314, top */

22
src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb
View File

@@ -2,14 +2,30 @@
chip northbridge/intel/sandybridge
register "usb_port_config" = "{
{1, 0, 0x0080}, {1, 0, 0x0080}, {1, 1, 0x0080}, {1, 1, 0x0080}, {1, 2, 0x0080},
{1, 2, 0x0080}, {1, 3, 0x0080}, {1, 3, 0x0080}, {1, 4, 0x0080}, {1, 4, 0x0080},
{1, 6, 0x0080}, {1, 5, 0x0080}, {1, 5, 0x0080}, {1, 6, 0x0080}
{1, 0, 0x0040}, {1, 0, 0x0040}, {1, 1, 0x0130}, {1, 1, 0x0130}, {1, 2, 0x0130},
{1, 2, 0x0130}, {1, 3, 0x0130}, {1, 3, 0x0130}, {1, 4, 0x0080}, {1, 4, 0x0080},
{1, 6, 0x0130}, {1, 5, 0x0130}, {1, 5, 0x0130}, {1, 6, 0x0130}
}"
device domain 0 on
subsystemid 0x1043 0x84ca inherit
chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH
register "gen1_dec" = "0x000c0291"
register "usb_port_config" = "{
{1, 8, 0}, /* Port 0: USB3 front internal header, top */
{1, 8, 0}, /* Port 1: USB3 front internal header, bottom */
{1, 2, 1}, /* Port 2: USB3 rear, top */
{1, 2, 1}, /* Port 3: USB3 rear, bottom */
{1, 2, 2}, /* Port 4: USB2 rear PS2, top */
{1, 2, 2}, /* Port 5: USB2 rear PS2, bottom */
{1, 2, 3}, /* Port 6: USB2 rear LAN, top */
{1, 2, 3}, /* Port 7: USB2 rear LAN, bottom */
{1, 9, 4}, /* Port 8: USB2 internal header USB910, top */
{1, 9, 4}, /* Port 9: USB2 internal header USB910, bottom */
{1, 2, 6}, /* Port 10: USB2 internal header USB1112, top */
{1, 2, 5}, /* Port 11: USB2 internal header USB1112, bottom */
{1, 2, 5}, /* Port 12: USB2 internal header USB1314, top */
{1, 2, 6} /* Port 13: USB2 internal header USB1314, bottom */
}"
device ref pcie_rp1 on end # PCIe x4 slot
device ref pcie_rp2 off end