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- 1.1.4

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Major restructuring of hypertransport handling.
  Major rewerite of superio/NSC/pc87360 as a proof of concept for handling superio resources dynamically
  Updates to hard_reset handling when resetting because of the need to change hypertransport link
    speeds and widths.
    (a) No longer assume the boot is good just because we get to a hard reset point.
    (b) Set a flag to indicate that the BIOS triggered the reset so we don't decrement the
       boot counter.
  Updates to arima/hdama mptable so it tracks the new bus numbers


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1097 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Eric Biederman
2003-09-02 17:16:48 +00:00
parent e9a271e32c
commit 0ac6b41e70
17 changed files with 1136 additions and 337 deletions
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268
src/devices/pci_device.c
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@@ -496,163 +496,6 @@ static struct device *pci_scan_get_dev(struct device **list, unsigned int devfn)
return dev;
}
void assign_id_set_links(device_t dev, uint8_t *pos,
uint8_t *previous_pos, unsigned previous_unitid,
unsigned last_unitid, int *reset_needed,
struct device *bus, unsigned *next_unitid)
{
static const uint8_t link_width_to_pow2[]= { 3, 4, 0, 5, 1, 2, 0, 0 };
static const uint8_t pow2_to_link_width[] = { 0x7, 4, 5, 0, 1, 3 };
uint16_t flags;
struct bus prev_bus;
struct device last, previous;
unsigned count;
uint8_t present_width_cap;
uint16_t present_freq_cap;
uint8_t upstream_width_cap;
uint16_t upstream_freq_cap;
uint8_t ln_upstream_width_in, ln_present_width_in;
uint8_t ln_upstream_width_out, ln_present_width_out;
uint16_t mask;
uint8_t freq;
uint8_t old_freq;
uint8_t upstream_width, present_width;
uint8_t old_width;
flags = pci_read_config16(dev, (*pos) + PCI_CAP_FLAGS);
printk_debug("flags: 0x%04x\n", (unsigned)flags);
if ((flags >> 13) != 0)
return; /* Entry is a Host */
/* Entry is a Slave secondary */
flags &= ~0x1f; /* mask out base unit ID */
flags |= *next_unitid & 0x1f; /* assign ID */
count = (flags >> 5) & 0x1f; /* get unit count */
printk_debug("unitid: 0x%02x, count: 0x%02x\n",
*next_unitid, count);
pci_write_config16(dev, (*pos) + PCI_CAP_FLAGS, flags);
*next_unitid += count;
if (previous_unitid == 0) { /* the link is back to the host */
prev_bus.secondary = 0;
/* calculate the previous pos for the host */
*previous_pos = 0x80;
previous.bus = &prev_bus;
previous.path.type = DEVICE_PATH_PCI;
previous.path.u.pci.devfn = 0x18 << 3;
#warning "FIXME we should not hard code this!"
} else {
previous.bus = bus;
previous.path.type = DEVICE_PATH_PCI;
previous.path.u.pci.devfn = previous_unitid << 3;
}
last.bus = bus;
last.path.type = DEVICE_PATH_PCI;
last.path.u.pci.devfn = last_unitid << 3;
/* Set link width and frequency */
present_freq_cap = pci_read_config16(&last,
(*pos) + PCI_HT_CAP_SLAVE_FREQ_CAP0);
present_width_cap = pci_read_config8(&last,
(*pos) + PCI_HT_CAP_SLAVE_WIDTH0);
if(previous_unitid == 0) { /* the link is back to the host */
upstream_freq_cap = pci_read_config16(&previous,
(*previous_pos) + PCI_HT_CAP_HOST_FREQ_CAP);
upstream_width_cap = pci_read_config8(&previous,
(*previous_pos) + PCI_HT_CAP_HOST_WIDTH);
}
else { /* The link is back up the chain */
upstream_freq_cap = pci_read_config16(&previous,
(*previous_pos) + PCI_HT_CAP_SLAVE_FREQ_CAP1);
upstream_width_cap = pci_read_config8(&previous,
(*previous_pos) + PCI_HT_CAP_SLAVE_WIDTH1);
}
/* Calculate the highest possible frequency */
/* Errata for 8131 - freq 5 has hardware problems don't support it */
freq = log2(present_freq_cap & upstream_freq_cap & 0x1f);
/* Calculate the highest width */
ln_upstream_width_in = link_width_to_pow2[upstream_width_cap & 7];
ln_present_width_out = link_width_to_pow2[(present_width_cap >> 4) & 7];
if (ln_upstream_width_in > ln_present_width_out) {
ln_upstream_width_in = ln_present_width_out;
}
upstream_width = pow2_to_link_width[ln_upstream_width_in];
present_width = pow2_to_link_width[ln_upstream_width_in] << 4;
ln_upstream_width_out = link_width_to_pow2[(upstream_width_cap >> 4) & 7];
ln_present_width_in = link_width_to_pow2[present_width_cap & 7];
if (ln_upstream_width_out > ln_present_width_in) {
ln_upstream_width_out = ln_present_width_in;
}
upstream_width |= pow2_to_link_width[ln_upstream_width_out] << 4;
present_width |= pow2_to_link_width[ln_upstream_width_out];
/* set the present device */
old_freq = pci_read_config8(&last, (*pos) + PCI_HT_CAP_SLAVE_FREQ0);
if(old_freq != freq) {
pci_write_config8(&last,
(*pos) + PCI_HT_CAP_SLAVE_FREQ0, freq);
*reset_needed = 1;
printk_debug("HyperT FreqP old %x new %x\n",old_freq,freq);
}
old_width = pci_read_config8(&last,
(*pos) + PCI_HT_CAP_SLAVE_WIDTH0 + 1);
if(present_width != old_width) {
pci_write_config8(&last,
(*pos) + PCI_HT_CAP_SLAVE_WIDTH0 + 1, present_width);
*reset_needed = 1;
printk_debug("HyperT widthP old %x new %x\n",
old_width, present_width);
}
/* set the upstream device */
if(previous_unitid == 0) { /* the link is back to the host */
old_freq = pci_read_config8(&previous,
(*previous_pos) + PCI_HT_CAP_HOST_FREQ);
old_freq &= 0x0f;
if(freq != old_freq) {
pci_write_config8(&previous,
(*previous_pos) + PCI_HT_CAP_HOST_FREQ, freq);
*reset_needed = 1;
printk_debug("HyperT freqUH old %x new %x\n",
old_freq, freq);
}
old_width = pci_read_config8(&previous,
(*previous_pos) + PCI_HT_CAP_HOST_WIDTH + 1);
if(upstream_width != old_width) {
pci_write_config8(&previous,
(*previous_pos) + PCI_HT_CAP_HOST_WIDTH + 1,
upstream_width);
*reset_needed = 1;
printk_debug("HyperT widthUH old %x new %x\n",
old_width, upstream_width);
}
}
else { /* The link is back up the chain */
old_freq = pci_read_config8(&previous,
(*previous_pos) + PCI_HT_CAP_SLAVE_FREQ1);
old_freq &= 0x0f;
if(freq != old_freq) {
pci_write_config8(&previous,
(*previous_pos) + PCI_HT_CAP_SLAVE_FREQ1,
freq);
*reset_needed = 1;
printk_debug("HyperT freqUL old %x new %x\n",
old_freq, freq);
}
old_width = pci_read_config8(&previous,
(*previous_pos) + PCI_HT_CAP_SLAVE_WIDTH1 + 1);
if(upstream_width != old_width) {
pci_write_config8(&previous,
(*previous_pos) + PCI_HT_CAP_SLAVE_WIDTH1,
upstream_width);
*reset_needed = 1;
printk_debug("HyperT widthUL old %x new %x\n",
old_width, upstream_width);
}
}
*previous_pos = *pos;
*pos=0;
}
#define HYPERTRANSPORT_SUPPORT 1
/** Scan the pci bus devices and bridges.
* @param bus pointer to the bus structure
* @param min_devfn minimum devfn to look at in the scan usually 0x00
@@ -668,11 +511,6 @@ unsigned int pci_scan_bus(struct bus *bus,
device_t dev;
device_t old_devices;
device_t child;
#if HYPERTRANSPORT_SUPPORT
unsigned next_unitid, last_unitid, previous_unitid;
int reset_needed = 0;
uint8_t previous_pos;
#endif
printk_debug("PCI: pci_scan_bus for bus %d\n", bus->secondary);
@@ -682,112 +520,6 @@ unsigned int pci_scan_bus(struct bus *bus,
post_code(0x24);
#if HYPERTRANSPORT_SUPPORT
/* Spin through the devices and collapse any early
* hypertransport enumeration.
*/
for(devfn = min_devfn; devfn <= max_devfn; devfn += 8) {
struct device dummy;
uint32_t id;
uint8_t hdr_type, pos;
dummy.bus = bus;
dummy.path.type = DEVICE_PATH_PCI;
dummy.path.u.pci.devfn = devfn;
id = pci_read_config32(&dummy, PCI_VENDOR_ID);
if ( (id == 0xffffffff) || (id == 0x00000000) ||
(id == 0x0000ffff) || (id == 0xffff0000)) {
continue;
}
hdr_type = pci_read_config8(&dummy, PCI_HEADER_TYPE);
pos = 0;
switch(hdr_type & 0x7f) {
case PCI_HEADER_TYPE_NORMAL:
case PCI_HEADER_TYPE_BRIDGE:
pos = PCI_CAPABILITY_LIST;
break;
}
if (pos > PCI_CAP_LIST_NEXT) {
pos = pci_read_config8(&dummy, pos);
}
while(pos != 0) {
uint8_t cap;
cap = pci_read_config8(&dummy, pos + PCI_CAP_LIST_ID);
printk_debug("Capability: 0x%02x @ 0x%02x\n", cap, pos);
if (cap == PCI_CAP_ID_HT) {
uint16_t flags;
flags = pci_read_config16(&dummy,
pos + PCI_CAP_FLAGS);
printk_debug("flags: 0x%04x\n",
(unsigned)flags);
if ((flags >> 13) == 0) {
/* Clear the unitid */
flags &= ~0x1f;
pci_write_config16(&dummy,
pos + PCI_CAP_FLAGS, flags);
break;
}
}
pos = pci_read_config8(&dummy, pos + PCI_CAP_LIST_NEXT);
}
}
/* If present assign unitid to a hypertransport chain */
last_unitid = 0;
next_unitid = 1;
previous_pos = 0;
do {
struct device dummy;
uint32_t id;
uint8_t hdr_type, pos;
previous_unitid = last_unitid;
last_unitid = next_unitid;
/* Read the next unassigned device off the stack */
dummy.bus = bus;
dummy.path.type = DEVICE_PATH_PCI;
dummy.path.u.pci.devfn = 0;
id = pci_read_config32(&dummy, PCI_VENDOR_ID);
/* If the chain is enumerated quit */
if (id == 0xffffffff || id == 0x00000000 ||
id == 0x0000ffff || id == 0xffff0000) {
break;
}
hdr_type = pci_read_config8(&dummy, PCI_HEADER_TYPE);
pos = 0;
switch(hdr_type & 0x7f) {
case PCI_HEADER_TYPE_NORMAL:
case PCI_HEADER_TYPE_BRIDGE:
pos = PCI_CAPABILITY_LIST;
break;
}
if (pos > PCI_CAP_LIST_NEXT) {
pos = pci_read_config8(&dummy, pos);
}
while(pos != 0) { /* loop through the linked list */
uint8_t cap;
cap = pci_read_config8(&dummy, pos + PCI_CAP_LIST_ID);
printk_debug("Capability: 0x%02x @ 0x%02x\n", cap, pos);
if (cap == PCI_CAP_ID_HT) {
assign_id_set_links(&dummy,&pos,&previous_pos,
previous_unitid, last_unitid,
&reset_needed, bus,
&next_unitid);
}
if(pos)
pos = pci_read_config8(&dummy,
pos + PCI_CAP_LIST_NEXT);
}
} while((last_unitid != next_unitid) && (next_unitid <= 0x1f));
#if HAVE_HARD_RESET == 1
if(reset_needed) {
printk_debug("HyperT reset needed\n");
boot_successful();
hard_reset();
}
printk_debug("HyperT reset not needed\n");
#endif /* HAVE_HARD_RESET */
#endif /* HYPERTRANSPORT_SUPPORT */
/* probe all devices on this bus with some optimization for non-existance and
single funcion devices */
for (devfn = min_devfn; devfn <= max_devfn; devfn++) {