Changes to allow Via/Epia code to be compiled after recent code changes.

New Files :-
	src/cpu/via/model_centaur/Config.lb
	src/cpu/via/model_centaur/model_centaur_init.c

Updated Files :-
	src/arch/i386/include/arch/smp/mpspec.h
		- make write_smp_table a define for non smp systems
	src/cpu/x86/lapic/lapic_cpu_init.c
		- change possible typo
	src/mainboard/via/epia/Config.lb
	src/mainboard/via/epia/Options.lb

	src/mainboard/via/epia/auto.c
	src/mainboard/via/epia/chip.h
	src/mainboard/via/epia/failover.c
		- updated after recent code changes
	src/northbridge/via/vt8601/chip.h
	src/northbridge/via/vt8601/northbridge.c
	src/northbridge/via/vt8601/raminit.c
		- corrections after recent code changes to allow compiling
	src/southbridge/via/vt8231/chip.h
	src/southbridge/via/vt8231/vt8231.c
		- initial pass to allow compiling after recent code changes.


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1726 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

src/cpu/via/model_centaur/Config.lb

@@ -0,0 +1,9 @@
+dir /cpu/x86/tsc
+dir /cpu/x86/mtrr
+dir /cpu/x86/fpu
+dir /cpu/x86/mmx
+dir /cpu/x86/sse
+dir /cpu/x86/lapic
+dir /cpu/x86/cache
+dir /cpu/intel/microcode
+driver model_centaur_init.o

src/cpu/via/model_centaur/model_centaur_init.c

@@ -0,0 +1,56 @@
+#include <console/console.h>
+#include <device/device.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <string.h>
+#include <cpu/cpu.h>
+#include <cpu/x86/mtrr.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/lapic.h>
+#include <cpu/intel/microcode.h>
+#include <cpu/x86/cache.h>
+#include <cpu/x86/mtrr.h>
+
+static uint32_t microcode_updates[] = {
+	/* WARNING - Intel has a new data structure that has variable length
+	 * microcode update lengths.  They are encoded in int 8 and 9.  A
+	 * dummy header of nulls must terminate the list.
+	 */
+
+	/*  Dummy terminator  */
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+};
+
+
+static void model_centaur_init(device_t dev)
+{
+	/* Turn on caching if we haven't already */
+	x86_enable_cache();
+	x86_mtrr_check();
+	
+	/* Update the microcode */
+	intel_update_microcode(microcode_updates);
+
+	/* Enable the local cpu apics */
+	setup_lapic();
+};
+
+static struct device_operations cpu_dev_ops = {
+	.init     = model_centaur_init,
+};
+
+#warning "FIXME - need correct cpu id here for VIA C3"
+static struct cpu_device_id cpu_table[] = {
+	{ X86_VENDOR_CENTAUR, 0x0670 },		// VIA C3 Samual 2
+	{ X86_VENDOR_CENTAUR, 0x0678 },		// VIA C3 Ezra
+	{ X86_VENDOR_CENTAUR, 0x0680 },		// VIA C3 Ezra-T
+	{ 0, 0 },
+};
+
+static struct cpu_driver driver __cpu_driver = {
+	.ops      = &cpu_dev_ops,
+	.id_table = cpu_table,
+};

src/cpu/x86/lapic/lapic_cpu_init.c

@@ -301,7 +301,7 @@ void initialize_cpus(struct bus *cpu_bus)
 	cpu_path.u.apic.apic_id = lapicid();
 #else
 	/* Get the device path of the boot cpu */
-	cpu_path.type           = DEVICE_PATH_BOOT_CPU;
+	cpu_path.type           = DEVICE_PATH_DEFAULT_CPU;
 #endif
 	
 	/* Find the device structure for the boot cpu */