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broadwell: Fix building with USE=quiet-cb

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This function needs to be available in different LOGLEVELs.

BUG=chrome-os-partner:28234
BRANCH=samus
TEST=USE=quiet-cb emerge-samus coreboot

Change-Id: Ib56995db64a7417a637eb8a93350fc40e6f83340
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 716d26c82a7df1dccf8956f301ab0e103fcedcff
Original-Change-Id: Ia8f0d05af24c9070c8c9241a3a7e137f845d1cab
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/221540
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9262
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Duncan Laurie
2014-10-03 15:34:09 -07:00
committed by Patrick Georgi
parent 88b004d6fc
commit 0b92a5e607
1 changed files with 6 additions and 6 deletions
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12
src/soc/intel/broadwell/me_status.c
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@@ -27,6 +27,12 @@
#include <broadwell/me.h>
#include <delay.h>
static inline void me_read_dword_ptr(void *ptr, int offset)
{
u32 dword = pci_read_config32(PCH_DEV_ME, offset);
memcpy(ptr, &dword, sizeof(dword));
}
#if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG)
/* HFS1[3:0] Current Working State Values */
@@ -201,12 +207,6 @@ static const char *me_progress_policy_values[] = {
"Required VSCC values for flash parts do not match",
};
static inline void me_read_dword_ptr(void *ptr, int offset)
{
u32 dword = pci_read_config32(PCH_DEV_ME, offset);
memcpy(ptr, &dword, sizeof(dword));
}
void intel_me_status(void)
{
struct me_hfs _hfs, *hfs = &_hfs;