From 0bcf238f2c5982e7d693f895907901d705d83b16 Mon Sep 17 00:00:00 2001 From: Jeremy Soller Date: Thu, 20 Jun 2019 13:57:30 -0600 Subject: [PATCH] Update gpio's after fixing coreboot-collector --- .../gaze14_1650_15/include/variant/gpio.h | 84 +-- .../gaze14_1650_17/include/variant/gpio.h | 620 ++++++++++++++++++ .../gaze14_1660ti_15/include/variant/gpio.h | 271 -------- src/mainboard/system76/whl-u/gpio.h | 72 +- 4 files changed, 700 insertions(+), 347 deletions(-) create mode 100644 src/mainboard/system76/cfl-h/variants/gaze14_1650_17/include/variant/gpio.h delete mode 100644 src/mainboard/system76/cfl-h/variants/gaze14_1660ti_15/include/variant/gpio.h diff --git a/src/mainboard/system76/cfl-h/variants/gaze14_1650_15/include/variant/gpio.h b/src/mainboard/system76/cfl-h/variants/gaze14_1650_15/include/variant/gpio.h index 4f5926a937..c63e9e0938 100644 --- a/src/mainboard/system76/cfl-h/variants/gaze14_1650_15/include/variant/gpio.h +++ b/src/mainboard/system76/cfl-h/variants/gaze14_1650_15/include/variant/gpio.h @@ -131,23 +131,23 @@ static const struct pad_config gpio_table[] = { // GPP_B // GSPI // TODO: TPM_PIRQ# - _PAD_CFG_STRUCT(GPP_B0, 0x40000700, 0x0000), + PAD_CFG_GPI(GPP_B0, NONE, DEEP), // NC - PAD_CFG_GPI(GPP_B1, NONE, DEEP), + PAD_CFG_TERM_GPO(GPP_B1, 0, NONE, DEEP), // Power Management // NC - PAD_CFG_TERM_GPO(GPP_B2, 0, NONE, DEEP), + PAD_CFG_GPI(GPP_B2, NONE, DEEP), // CPU Misc // NC PAD_CFG_GPI(GPP_B3, NONE, DEEP), // TODO: EXTTS_SNI_DRV1 - PAD_CFG_GPI(GPP_B4, NONE, DEEP), + PAD_CFG_TERM_GPO(GPP_B4, 1, NONE, DEEP), // Clock Signals // NC - PAD_CFG_TERM_GPO(GPP_B5, 1, NONE, DEEP), + PAD_CFG_GPI(GPP_B5, NONE, PLTRST), // NC PAD_CFG_GPI(GPP_B6, NONE, PLTRST), // NC @@ -157,15 +157,15 @@ static const struct pad_config gpio_table[] = { // NC PAD_CFG_GPI(GPP_B9, NONE, PLTRST), // LAN_CLKREQ# - PAD_CFG_GPI(GPP_B10, NONE, PLTRST), + PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), // Audio // TODO: GPP_B11: DDR Voltage select - 0 = 1.2V, 1 = 1.35V - PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), + PAD_CFG_GPI(GPP_B11, UP_20K, DEEP), // Power Management // SLP_S0# - PAD_CFG_GPI(GPP_B12, UP_20K, DEEP), + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // PLT_RST# PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), @@ -175,25 +175,25 @@ static const struct pad_config gpio_table[] = { // GSPI // NC - PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + PAD_NC(GPP_B15, NONE), // NC - PAD_NC(GPP_B16, NONE), + PAD_CFG_GPI(GPP_B16, NONE, DEEP), // NC PAD_CFG_GPI(GPP_B17, NONE, DEEP), // LPSS_GSPI0_MOSI - strap for no reboot mode - PAD_CFG_GPI(GPP_B18, NONE, DEEP), + PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), // NC - PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), + PAD_NC(GPP_B19, NONE), // NC PAD_NC(GPP_B20, NONE), // NC PAD_NC(GPP_B21, NONE), // LPSS_GSPI1_MOSI - strap for booting from SPI or LPC - PAD_NC(GPP_B22, NONE), + PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1), // SMBUS // PCH_HOT_GNSS_DISABLE - strap for DCI BSSB mode - PAD_CFG_NF(GPP_B23, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B23, NONE, DEEP, NF2), // GPP_C // SMBUS @@ -238,9 +238,9 @@ static const struct pad_config gpio_table[] = { // I2C_SDA_TP PAD_CFG_NF(GPP_C17, NONE, PLTRST, NF1), // NC - PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), + PAD_NC(GPP_C18, NONE), // NC - PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), + PAD_NC(GPP_C19, NONE), // UART // UART2_RXD @@ -490,74 +490,74 @@ static const struct pad_config gpio_table[] = { // GPP_I // Display Signals // NC - _PAD_CFG_STRUCT(GPP_I0, 0x40000700, 0x3c00), + PAD_CFG_GPI(GPP_I0, NONE, DEEP), // HDMI_HPD - _PAD_CFG_STRUCT(GPP_I1, 0x40000700, 0x3c00), + PAD_CFG_NF(GPP_I1, NONE, PLTRST, NF1), // NC - _PAD_CFG_STRUCT(GPP_I2, 0x40000700, 0x3c00), + PAD_CFG_NF(GPP_I2, NONE, DEEP, NF1), // MDP_E_HPD - _PAD_CFG_STRUCT(GPP_I3, 0x40000700, 0x0000), + _PAD_CFG_STRUCT(GPP_I3, 0x46880100, 0x0000), // EDP_HPD - _PAD_CFG_STRUCT(GPP_I4, 0x40000700, 0x0000), + PAD_CFG_NF(GPP_I4, NONE, DEEP, NF1), // NC - _PAD_CFG_STRUCT(GPP_I5, 0x40000700, 0x0000), + PAD_CFG_GPI(GPP_I5, NONE, DEEP), // NC - _PAD_CFG_STRUCT(GPP_I6, 0x40000700, 0x0000), + PAD_CFG_GPI(GPP_I6, NONE, DEEP), // HDMI_CTRLCLK - _PAD_CFG_STRUCT(GPP_I7, 0x40000700, 0x0000), + PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1), // HDMI_CTRLDATA - _PAD_CFG_STRUCT(GPP_I8, 0x40000700, 0x0000), + PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1), // NC - _PAD_CFG_STRUCT(GPP_I9, 0x40000700, 0x1000), + PAD_CFG_GPI(GPP_I9, NONE, DEEP), // NC - _PAD_CFG_STRUCT(GPP_I10, 0x40000700, 0x1000), + PAD_CFG_GPI(GPP_I10, NONE, DEEP), // PCIE // TODO: H_SKTOCC_N - _PAD_CFG_STRUCT(GPP_I11, 0x40000700, 0x3c00), + PAD_CFG_GPI(GPP_I11, NONE, DEEP), // NC - _PAD_CFG_STRUCT(GPP_I12, 0x40000700, 0x3c00), + PAD_CFG_GPI(GPP_I12, NONE, DEEP), // NC - _PAD_CFG_STRUCT(GPP_I13, 0x40000700, 0x3c00), + PAD_CFG_GPI(GPP_I13, NONE, DEEP), // NC - _PAD_CFG_STRUCT(GPP_I14, 0x40000700, 0x3c00), + PAD_CFG_GPI(GPP_I14, NONE, DEEP), // GPP_J // CNVI // CNVI_GNSS_PA_BLANKING - _PAD_CFG_STRUCT(GPP_J0, 0x40000700, 0x3c00), + PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1), // Power Management // NC - _PAD_CFG_STRUCT(GPP_J1, 0x40000700, 0x3c00), + PAD_CFG_TERM_GPO(GPP_J1, 1, NONE, DEEP), // GPIO // NC - _PAD_CFG_STRUCT(GPP_J2, 0x40000700, 0x3c00), + PAD_NC(GPP_J2, NONE), // NC - _PAD_CFG_STRUCT(GPP_J3, 0x40000700, 0x3c00), + PAD_NC(GPP_J3, NONE), // CNVI // CNVI_BRI_DT - _PAD_CFG_STRUCT(GPP_J4, 0x40000700, 0x3c00), + PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1), // CNVI_BRI_RSP - PAD_CFG_GPI(GPP_J5, NONE, DEEP), + PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1), // CNVI_RGI_DT - PAD_CFG_NF(GPP_J6, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1), // CNVI_RGI_RSP - PAD_CFG_NF(GPP_J7, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_J7, UP_20K, DEEP, NF1), // CNVI_MFUART2_RXD - _PAD_CFG_STRUCT(GPP_J8, 0x46880100, 0x0000), + PAD_CFG_NF(GPP_J8, NONE, DEEP, NF1), // CNVI_MFUART2_TXD PAD_CFG_NF(GPP_J9, NONE, DEEP, NF1), // GPIO // NC - PAD_CFG_GPI(GPP_J10, NONE, DEEP), + PAD_NC(GPP_J10, NONE), // A4WP // NC - PAD_CFG_GPI(GPP_J11, NONE, DEEP), + PAD_NC(GPP_J11, NONE), // GPP_K // GPIO diff --git a/src/mainboard/system76/cfl-h/variants/gaze14_1650_17/include/variant/gpio.h b/src/mainboard/system76/cfl-h/variants/gaze14_1650_17/include/variant/gpio.h new file mode 100644 index 0000000000..c63e9e0938 --- /dev/null +++ b/src/mainboard/system76/cfl-h/variants/gaze14_1650_17/include/variant/gpio.h @@ -0,0 +1,620 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 System76 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include +#include + +#ifndef __ACPI__ + +/* Early pad configuration in romstage. */ +static const struct pad_config early_gpio_table[] = { + // UART2 + // UART2_RXD + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), + // UART2_TXD + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), + // NC + PAD_NC(GPP_C22, NONE), + // NC + PAD_NC(GPP_C23, NONE), +}; + +/* Pad configuration in ramstage. */ +static const struct pad_config gpio_table[] = { +// GPD + // Power Management + // NC + PAD_CFG_NF(GPD0, NONE, DEEP, NF1), + // AC_PRESENT + PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1), + // NC + PAD_CFG_GPI(GPD2, NATIVE, PWROK), + // PWR_BTN# + PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), + // SUSB#_PCH + PAD_CFG_NF(GPD4, NONE, DEEP, NF1), + // SUSC#_PCH + PAD_CFG_NF(GPD5, NONE, DEEP, NF1), + // NC + _PAD_CFG_STRUCT(GPD6, 0x44000601, 0x0000), + + // GPIO + // NC + _PAD_CFG_STRUCT(GPD7, 0x04000300, 0x0000), + + // Power Management + // SUS_CLK_R + PAD_CFG_NF(GPD8, NONE, DEEP, NF1), + // NC + PAD_CFG_GPI(GPD9, NONE, PWROK), + // NC + PAD_CFG_NF(GPD10, NONE, PWROK, NF1), + // NC + PAD_CFG_TERM_GPO(GPD11, 0, NONE, PWROK), + +// GPP_A + // LPC + // SB_KBCRST# + PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), + // LPC_AD0 + PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), + // LPC_AD1 + PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), + // LPC_AD2 + PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), + // LPC_AD3 + PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), + // LPC_FRAME# + PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), + // SERIRQ + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), + // NC + PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), + // PM_CLKRUN# + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), + // PCLK_KBC + PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), + // NC + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), + + // Power Management + // TODO: LAN_WAKEUP# + PAD_CFG_GPI(GPP_A11, NONE, DEEP), + // NC + PAD_CFG_GPI(GPP_A12, NONE, DEEP), + // SUSWARN# + PAD_CFG_NF(GPP_A13, DN_20K, DEEP, NF1), + + // LPC + // NC + PAD_CFG_TERM_GPO(GPP_A14, 0, DN_20K, DEEP), + + // Power Management + // SUS_PWR_ACK + PAD_CFG_GPI(GPP_A15, NONE, DEEP), + + // Clock Signals + // NC + PAD_NC(GPP_A16, NONE), + + // ISH + // NC + PAD_NC(GPP_A17, NONE), + // SB_BLON + PAD_CFG_TERM_GPO(GPP_A18, 1, NONE, DEEP), + // NC + PAD_NC(GPP_A19, NONE), + // NC + PAD_NC(GPP_A20, NONE), + // NC + PAD_NC(GPP_A21, NONE), + // SATA_PWR_EN + PAD_CFG_TERM_GPO(GPP_A22, 0, NONE, DEEP), + // NC + PAD_NC(GPP_A23, NONE), + +// GPP_B + // GSPI + // TODO: TPM_PIRQ# + PAD_CFG_GPI(GPP_B0, NONE, DEEP), + // NC + PAD_CFG_TERM_GPO(GPP_B1, 0, NONE, DEEP), + + // Power Management + // NC + PAD_CFG_GPI(GPP_B2, NONE, DEEP), + + // CPU Misc + // NC + PAD_CFG_GPI(GPP_B3, NONE, DEEP), + // TODO: EXTTS_SNI_DRV1 + PAD_CFG_TERM_GPO(GPP_B4, 1, NONE, DEEP), + + // Clock Signals + // NC + PAD_CFG_GPI(GPP_B5, NONE, PLTRST), + // NC + PAD_CFG_GPI(GPP_B6, NONE, PLTRST), + // NC + PAD_CFG_GPI(GPP_B7, NONE, PLTRST), + // NC + PAD_CFG_GPI(GPP_B8, NONE, PLTRST), + // NC + PAD_CFG_GPI(GPP_B9, NONE, PLTRST), + // LAN_CLKREQ# + PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), + + // Audio + // TODO: GPP_B11: DDR Voltage select - 0 = 1.2V, 1 = 1.35V + PAD_CFG_GPI(GPP_B11, UP_20K, DEEP), + + // Power Management + // SLP_S0# + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + // PLT_RST# + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + + // Audio + // PCH_SPKR + PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), + + // GSPI + // NC + PAD_NC(GPP_B15, NONE), + // NC + PAD_CFG_GPI(GPP_B16, NONE, DEEP), + // NC + PAD_CFG_GPI(GPP_B17, NONE, DEEP), + // LPSS_GSPI0_MOSI - strap for no reboot mode + PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + // NC + PAD_NC(GPP_B19, NONE), + // NC + PAD_NC(GPP_B20, NONE), + // NC + PAD_NC(GPP_B21, NONE), + // LPSS_GSPI1_MOSI - strap for booting from SPI or LPC + PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1), + + // SMBUS + // PCH_HOT_GNSS_DISABLE - strap for DCI BSSB mode + PAD_CFG_NF(GPP_B23, NONE, DEEP, NF2), + +// GPP_C + // SMBUS + // SMB_CLK + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), + // SMB_DATA + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), + // NC + PAD_CFG_GPI(GPP_C2, NONE, DEEP), + // NC + PAD_NC(GPP_C3, NONE), + // NC + PAD_NC(GPP_C4, NONE), + // NC + PAD_CFG_GPI(GPP_C5, NONE, DEEP), + // NC + PAD_CFG_GPI(GPP_C6, NONE, DEEP), + // NC + PAD_CFG_GPI(GPP_C7, NONE, DEEP), + + // UART + // NC + PAD_NC(GPP_C8, NONE), + // TODO: CNVI_DET# + PAD_CFG_TERM_GPO(GPP_C9, 1, NONE, DEEP), + // NC + PAD_NC(GPP_C10, NONE), + // NC + PAD_NC(GPP_C11, NONE), + // NC + PAD_NC(GPP_C12, NONE), + // NC + PAD_NC(GPP_C13, NONE), + // NC + PAD_NC(GPP_C14, NONE), + // NC + PAD_NC(GPP_C15, NONE), + + // I2C + // I2C_SCL_TP + PAD_CFG_NF(GPP_C16, NONE, PLTRST, NF1), + // I2C_SDA_TP + PAD_CFG_NF(GPP_C17, NONE, PLTRST, NF1), + // NC + PAD_NC(GPP_C18, NONE), + // NC + PAD_NC(GPP_C19, NONE), + + // UART + // UART2_RXD + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), + // UART2_TXD + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), + // NC + PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1), + // NC + PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1), + +// GPP_D + // SPI + // NC + PAD_NC(GPP_D0, NONE), + // NC + PAD_NC(GPP_D1, NONE), + // NC + PAD_NC(GPP_D2, NONE), + // NC + PAD_NC(GPP_D3, NONE), + + // I2C + // NC + PAD_NC(GPP_D4, NONE), + + // CNVI + // CNVI_RF_RST# + PAD_CFG_NF(GPP_D5, NONE, DEEP, NF3), + // XTAL_CLKREQ + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF3), + // NC + PAD_NC(GPP_D7, NONE), + // NC + PAD_NC(GPP_D8, NONE), + + // ISH + // NC + PAD_NC(GPP_D9, NONE), + // NC + PAD_NC(GPP_D10, NONE), + // NC + PAD_NC(GPP_D11, NONE), + // NC + PAD_NC(GPP_D12, NONE), + // NC + PAD_NC(GPP_D13, NONE), + // NC + PAD_NC(GPP_D14, NONE), + // NC + PAD_NC(GPP_D15, NONE), + // NC + PAD_NC(GPP_D16, NONE), + + // DMIC + // NC + PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), + // NC + PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), + // NC + PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), + // NC + PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), + + // SPI + // NC + PAD_NC(GPP_D21, NONE), + // NC + PAD_NC(GPP_D22, NONE), + + // ISH + // NC + PAD_NC(GPP_D23, NONE), + +// GPP_E + // SATA + // NC + PAD_CFG_GPI(GPP_E0, NONE, DEEP), + // SATAGP1 + PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), + // NC + PAD_CFG_GPI(GPP_E2, NONE, DEEP), + + // CPU Misc + // TODO: EXTTS_SNI_DRV0 + _PAD_CFG_STRUCT(GPP_E3, 0x44000101, 0x0000), + + // SATA + // DEVSLP0 + PAD_CFG_GPI(GPP_E4, UP_20K, DEEP), + // DEVSLP1 + PAD_CFG_GPI(GPP_E5, UP_20K, DEEP), + // NC + PAD_NC(GPP_E6, NONE), + + // CPU Misc + // TODO: TP_ATTN# + _PAD_CFG_STRUCT(GPP_E7, 0x40800100, 0x3000), + + // SATA + // SATA_LED# + PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), + + // USB2 + // NC + PAD_NC(GPP_E9, NONE), + // NC + PAD_NC(GPP_E10, NONE), + // NC + PAD_NC(GPP_E11, NONE), + // NC + PAD_NC(GPP_E12, NONE), + +// GPP_F + // SATA + // NC + PAD_NC(GPP_F0, NONE), + // NC + PAD_NC(GPP_F1, NONE), + // NC + PAD_NC(GPP_F2, NONE), + // NC + PAD_NC(GPP_F3, NONE), + // NC + PAD_NC(GPP_F4, NONE), + // KBLED_DET + PAD_CFG_GPI(GPP_F5, NONE, DEEP), + // LIGHT_KB_DET# + PAD_CFG_GPI(GPP_F6, NONE, DEEP), + // NC + PAD_NC(GPP_F7, NONE), + // NC + PAD_NC(GPP_F8, NONE), + // NC + PAD_NC(GPP_F9, NONE), + // BIOS_REC - strap for bios recovery enable + PAD_NC(GPP_F10, NONE), + // PCH_RSVD - unused strap + PAD_NC(GPP_F11, NONE), + // MFG_MODE - strap for manufacturing mode + PAD_NC(GPP_F12, NONE), + // TODO: GP39_GFX_CRB_DETECT - 0 = normal gfx, 1 = customer gfx + PAD_NC(GPP_F13, NONE), + + // Power Management + // H_SKTOCC_N + PAD_CFG_GPI(GPP_F14, UP_20K, DEEP), + + // USB2 + // NC + PAD_NC(GPP_F15, NONE), + // NC + PAD_NC(GPP_F16, NONE), + // NC + PAD_NC(GPP_F17, NONE), + // NC + PAD_NC(GPP_F18, NONE), + + // Display Signals + // NB_ENAVDD + PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), + // BLON + PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), + // EDP_BRIGHTNESS + PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), + // TODO: DGPU_RST#_PCH + PAD_CFG_TERM_GPO(GPP_F22, 0, NONE, PLTRST), + // TODO: DGPU_PWR_EN + PAD_CFG_TERM_GPO(GPP_F23, 0, NONE, DEEP), + +// GPP_G + // SD + // BOARD_ID1 + PAD_CFG_GPI(GPP_G0, NONE, DEEP), + // BOARD_ID2 + PAD_CFG_GPI(GPP_G1, NONE, DEEP), + // TPM_DET + PAD_CFG_GPI(GPP_G2, NONE, DEEP), + // TODO: GPIO4_1V8_MAIN_EN_R + PAD_CFG_GPI(GPP_G3, UP_20K, DEEP), + // NC + PAD_NC(GPP_G4, NONE), + // NC + PAD_NC(GPP_G5, NONE), + // NC + PAD_NC(GPP_G6, NONE), + // NC + PAD_NC(GPP_G7, NONE), + +// GPP_H + // Clock Signals + // WLAN_CLKREQ# + PAD_CFG_NF(GPP_H0, NONE, DEEP, NF1), + // NC + _PAD_CFG_STRUCT(GPP_H1, 0x84000300, 0x0000), + // PEG_CLKREQ# + PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1), + // NC + _PAD_CFG_STRUCT(GPP_H3, 0x84000300, 0x0000), + // SSD_CLKREQ# + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + // SSD2_CLKREQ# + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + // NC + _PAD_CFG_STRUCT(GPP_H6, 0x84000300, 0x0000), + // NC + _PAD_CFG_STRUCT(GPP_H7, 0x84000300, 0x0000), + // NC + _PAD_CFG_STRUCT(GPP_H8, 0x84000300, 0x0000), + // NC + _PAD_CFG_STRUCT(GPP_H9, 0x84000300, 0x0000), + + // SMBUS + // NC + PAD_CFG_GPI(GPP_H10, NONE, DEEP), + // NC + PAD_CFG_GPI(GPP_H11, NONE, DEEP), + // GPP_H_12 - strap for ESPI flash sharing mode + PAD_CFG_GPI(GPP_H12, NONE, DEEP), + // NC + PAD_CFG_GPI(GPP_H13, NONE, DEEP), + // NC + PAD_CFG_GPI(GPP_H14, NONE, DEEP), + // NC + PAD_CFG_GPI(GPP_H15, NONE, DEEP), + // NC + PAD_CFG_GPI(GPP_H16, NONE, DEEP), + // NC + PAD_CFG_GPI(GPP_H17, NONE, DEEP), + // NC + PAD_CFG_GPI(GPP_H18, NONE, DEEP), + + // ISH + // NC + PAD_CFG_GPI(GPP_H19, NONE, DEEP), + // NC + PAD_CFG_GPI(GPP_H20, NONE, DEEP), + // NC + PAD_CFG_GPI(GPP_H21, NONE, DEEP), + // NC + PAD_CFG_GPI(GPP_H22, NONE, DEEP), + + // GPIO + // NC + PAD_CFG_GPI(GPP_H23, NONE, DEEP), + +// GPP_I + // Display Signals + // NC + PAD_CFG_GPI(GPP_I0, NONE, DEEP), + // HDMI_HPD + PAD_CFG_NF(GPP_I1, NONE, PLTRST, NF1), + // NC + PAD_CFG_NF(GPP_I2, NONE, DEEP, NF1), + // MDP_E_HPD + _PAD_CFG_STRUCT(GPP_I3, 0x46880100, 0x0000), + // EDP_HPD + PAD_CFG_NF(GPP_I4, NONE, DEEP, NF1), + // NC + PAD_CFG_GPI(GPP_I5, NONE, DEEP), + // NC + PAD_CFG_GPI(GPP_I6, NONE, DEEP), + // HDMI_CTRLCLK + PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1), + // HDMI_CTRLDATA + PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1), + // NC + PAD_CFG_GPI(GPP_I9, NONE, DEEP), + // NC + PAD_CFG_GPI(GPP_I10, NONE, DEEP), + + // PCIE + // TODO: H_SKTOCC_N + PAD_CFG_GPI(GPP_I11, NONE, DEEP), + // NC + PAD_CFG_GPI(GPP_I12, NONE, DEEP), + // NC + PAD_CFG_GPI(GPP_I13, NONE, DEEP), + // NC + PAD_CFG_GPI(GPP_I14, NONE, DEEP), + +// GPP_J + // CNVI + // CNVI_GNSS_PA_BLANKING + PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1), + + // Power Management + // NC + PAD_CFG_TERM_GPO(GPP_J1, 1, NONE, DEEP), + + // GPIO + // NC + PAD_NC(GPP_J2, NONE), + // NC + PAD_NC(GPP_J3, NONE), + + // CNVI + // CNVI_BRI_DT + PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1), + // CNVI_BRI_RSP + PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1), + // CNVI_RGI_DT + PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1), + // CNVI_RGI_RSP + PAD_CFG_NF(GPP_J7, UP_20K, DEEP, NF1), + // CNVI_MFUART2_RXD + PAD_CFG_NF(GPP_J8, NONE, DEEP, NF1), + // CNVI_MFUART2_TXD + PAD_CFG_NF(GPP_J9, NONE, DEEP, NF1), + + // GPIO + // NC + PAD_NC(GPP_J10, NONE), + + // A4WP + // NC + PAD_NC(GPP_J11, NONE), + +// GPP_K + // GPIO + // NC + PAD_NC(GPP_K0, NONE), + // NC + PAD_NC(GPP_K1, NONE), + // NC + PAD_NC(GPP_K2, NONE), + // SCI# + _PAD_CFG_STRUCT(GPP_K3, 0x80880100, 0x3000), + // NC + PAD_NC(GPP_K4, NONE), + // NC + PAD_NC(GPP_K5, NONE), + // SWI# + _PAD_CFG_STRUCT(GPP_K6, 0x40880100, 0x3000), + // NC + PAD_NC(GPP_K7, NONE), + // SATA_M2_PWR_EN1 + PAD_CFG_GPI(GPP_K8, NONE, DEEP), + // SATA_M2_PWR_EN2 + PAD_CFG_GPI(GPP_K9, NONE, DEEP), + // NC + PAD_CFG_GPI(GPP_K10, NONE, DEEP), + // NC + PAD_CFG_GPI(GPP_K11, NONE, DEEP), + + // GSX + // NC + PAD_NC(GPP_K12, NONE), + // NC + PAD_NC(GPP_K13, NONE), + // NC + PAD_NC(GPP_K14, NONE), + // NC + PAD_NC(GPP_K15, NONE), + // NC + PAD_NC(GPP_K16, NONE), + + // GPIO + // NC + PAD_NC(GPP_K17, NONE), + // NC + PAD_NC(GPP_K18, NONE), + // SMI# + _PAD_CFG_STRUCT(GPP_K19, 0x42000100, 0x3000), + // TODO: GPU_EVENT# + _PAD_CFG_STRUCT(GPP_K20, 0x44000101, 0x0000), + // TODO: GC6_FB_EN_PCH + PAD_CFG_GPI(GPP_K21, NONE, DEEP), + // TODO: DGPU_PWRGD_R + _PAD_CFG_STRUCT(GPP_K22, 0x80000100, 0x0000), + // NC + PAD_CFG_NF(GPP_K23, NONE, DEEP, NF1), +}; + +#endif + +#endif diff --git a/src/mainboard/system76/cfl-h/variants/gaze14_1660ti_15/include/variant/gpio.h b/src/mainboard/system76/cfl-h/variants/gaze14_1660ti_15/include/variant/gpio.h deleted file mode 100644 index 0efe5d2c3b..0000000000 --- a/src/mainboard/system76/cfl-h/variants/gaze14_1660ti_15/include/variant/gpio.h +++ /dev/null @@ -1,271 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2019 System76 - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ - -#ifndef MAINBOARD_GPIO_H -#define MAINBOARD_GPIO_H - -#include -#include - -#ifndef __ACPI__ - -/* Early pad configuration in romstage. */ -static const struct pad_config early_gpio_table[] = { - // UART2 - // UART2_RXD - PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), - // UART2_TXD - PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), - // NC - PAD_NC(GPP_C22, NONE), - // NC - PAD_NC(GPP_C23, NONE), -}; - -/* Pad configuration in ramstage. */ -static const struct pad_config gpio_table[] = { - PAD_CFG_NF(GPD0, NONE, DEEP, NF1), - PAD_CFG_NF(GPD1, DN_20K, DEEP, NF1), - PAD_CFG_GPI(GPD2, DN_20K, PWROK), - PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), - PAD_CFG_NF(GPD4, DN_20K, DEEP, NF1), - PAD_CFG_NF(GPD5, DN_20K, DEEP, NF1), - PAD_CFG_NF(GPD6, DN_20K, DEEP, NF1), - PAD_CFG_GPI(GPD7, NONE, PWROK), - PAD_CFG_NF(GPD8, DN_20K, DEEP, NF1), - PAD_CFG_GPI(GPD9, DN_20K, PWROK), - _PAD_CFG_STRUCT(GPD10, 0x04000601, 0x1000), - PAD_CFG_TERM_GPO(GPD11, 0, DN_20K, DEEP), - PAD_CFG_TERM_GPO(GPP_A0, 0, NONE, DEEP), - PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), - PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), - PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), - PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), - PAD_CFG_NF(GPP_A5, DN_20K, DEEP, NF1), - PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), - _PAD_CFG_STRUCT(GPP_A7, 0x80100100, 0x0000), - PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), - PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1), - PAD_CFG_GPI(GPP_A11, UP_20K, DEEP), - PAD_CFG_GPI(GPP_A12, NONE, DEEP), - PAD_CFG_NF(GPP_A13, DN_20K, DEEP, NF1), - PAD_CFG_NF(GPP_A14, DN_20K, DEEP, NF1), - PAD_CFG_NF(GPP_A15, UP_20K, DEEP, NF1), - _PAD_CFG_STRUCT(GPP_A16, 0x44000101, 0x1000), - _PAD_CFG_STRUCT(GPP_A17, 0x44000101, 0x0000), - PAD_CFG_TERM_GPO(GPP_A18, 1, NONE, DEEP), - PAD_CFG_GPI(GPP_A19, NONE, DEEP), - PAD_CFG_GPI(GPP_A20, NONE, DEEP), - _PAD_CFG_STRUCT(GPP_A21, 0x44000101, 0x0000), - PAD_CFG_TERM_GPO(GPP_A22, 1, NONE, DEEP), - PAD_CFG_GPI(GPP_A23, NONE, DEEP), - _PAD_CFG_STRUCT(GPP_B0, 0x40000700, 0x0000), - PAD_CFG_GPI(GPP_B1, NONE, DEEP), - PAD_CFG_TERM_GPO(GPP_B2, 0, NONE, DEEP), - PAD_CFG_TERM_GPO(GPP_B3, 0, NONE, DEEP), - PAD_CFG_TERM_GPO(GPP_B4, 0, NONE, DEEP), - PAD_CFG_TERM_GPO(GPP_B5, 0, UP_20K, DEEP), - PAD_CFG_TERM_GPO(GPP_B6, 0, NONE, DEEP), - PAD_CFG_TERM_GPO(GPP_B7, 0, NONE, DEEP), - PAD_CFG_TERM_GPO(GPP_B8, 0, NONE, DEEP), - PAD_CFG_TERM_GPO(GPP_B9, 0, NONE, DEEP), - PAD_CFG_TERM_GPO(GPP_B10, 0, NONE, DEEP), - PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), - PAD_CFG_TERM_GPO(GPP_B12, 0, NONE, DEEP), - _PAD_CFG_STRUCT(GPP_B13, 0x44000601, 0x0000), - _PAD_CFG_STRUCT(GPP_B14, 0x44000601, 0x1000), - PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), - PAD_CFG_TERM_GPO(GPP_B16, 0, NONE, DEEP), - PAD_CFG_TERM_GPO(GPP_B17, 0, NONE, DEEP), - PAD_CFG_TERM_GPO(GPP_B18, 0, NONE, DEEP), - PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), - PAD_CFG_TERM_GPO(GPP_B20, 0, NONE, DEEP), - PAD_CFG_TERM_GPO(GPP_B21, 0, NONE, DEEP), - PAD_CFG_TERM_GPO(GPP_B22, 0, NONE, DEEP), - PAD_CFG_NF(GPP_B23, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), - PAD_CFG_GPI(GPP_C2, NONE, DEEP), - PAD_CFG_GPI(GPP_C3, NONE, DEEP), - PAD_CFG_GPI(GPP_C4, NONE, DEEP), - PAD_CFG_TERM_GPO(GPP_C5, 0, NONE, DEEP), - PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), - PAD_CFG_TERM_GPO(GPP_C8, 0, NONE, DEEP), - PAD_CFG_GPI(GPP_C9, NONE, DEEP), - PAD_CFG_TERM_GPO(GPP_C10, 0, NONE, DEEP), - PAD_CFG_TERM_GPO(GPP_C11, 0, NONE, DEEP), - PAD_CFG_TERM_GPO(GPP_C12, 0, NONE, DEEP), - PAD_CFG_TERM_GPO(GPP_C13, 0, NONE, DEEP), - PAD_CFG_TERM_GPO(GPP_C14, 0, NONE, DEEP), - PAD_CFG_TERM_GPO(GPP_C15, 0, NONE, DEEP), - PAD_CFG_NF(GPP_C16, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_C17, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_C18, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_C19, NONE, PLTRST, NF1), - PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1), - PAD_CFG_TERM_GPO(GPP_D0, 0, NONE, DEEP), - PAD_CFG_TERM_GPO(GPP_D1, 0, NONE, DEEP), - PAD_CFG_TERM_GPO(GPP_D2, 0, NONE, DEEP), - PAD_CFG_TERM_GPO(GPP_D3, 0, NONE, DEEP), - PAD_CFG_TERM_GPO(GPP_D4, 0, NONE, DEEP), - PAD_CFG_NF(GPP_D5, NONE, DEEP, NF3), - PAD_CFG_NF(GPP_D6, NONE, DEEP, NF3), - PAD_CFG_TERM_GPO(GPP_D7, 0, NONE, DEEP), - PAD_CFG_TERM_GPO(GPP_D8, 0, NONE, DEEP), - PAD_CFG_TERM_GPO(GPP_D9, 0, NONE, DEEP), - PAD_CFG_TERM_GPO(GPP_D10, 0, NONE, DEEP), - PAD_CFG_TERM_GPO(GPP_D11, 0, NONE, DEEP), - PAD_CFG_TERM_GPO(GPP_D12, 0, NONE, DEEP), - PAD_CFG_TERM_GPO(GPP_D13, 0, NONE, DEEP), - PAD_CFG_TERM_GPO(GPP_D14, 0, NONE, DEEP), - PAD_CFG_TERM_GPO(GPP_D15, 0, NONE, DEEP), - PAD_CFG_TERM_GPO(GPP_D16, 0, NONE, DEEP), - PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), - PAD_CFG_TERM_GPO(GPP_D21, 0, NONE, DEEP), - PAD_CFG_TERM_GPO(GPP_D22, 0, NONE, DEEP), - PAD_CFG_TERM_GPO(GPP_D23, 0, NONE, DEEP), - PAD_CFG_GPI(GPP_E0, NONE, DEEP), - PAD_CFG_NF(GPP_E1, UP_20K, DEEP, NF1), - PAD_CFG_GPI(GPP_E2, NONE, DEEP), - PAD_CFG_TERM_GPO(GPP_E3, 0, UP_20K, DEEP), - PAD_CFG_TERM_GPO(GPP_E4, 1, NONE, DEEP), - PAD_CFG_TERM_GPO(GPP_E5, 0, NONE, DEEP), - PAD_CFG_TERM_GPO(GPP_E6, 0, NONE, DEEP), - _PAD_CFG_STRUCT(GPP_E7, 0x80800100, 0x0000), - PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), - _PAD_CFG_STRUCT(GPP_E9, 0x44000101, 0x3000), - _PAD_CFG_STRUCT(GPP_E10, 0x44000501, 0x3000), - _PAD_CFG_STRUCT(GPP_E11, 0x44000501, 0x3000), - _PAD_CFG_STRUCT(GPP_E12, 0x44000501, 0x3000), - PAD_CFG_TERM_GPO(GPP_F0, 0, NONE, DEEP), - PAD_CFG_TERM_GPO(GPP_F1, 0, NONE, DEEP), - PAD_CFG_TERM_GPO(GPP_F2, 0, NONE, DEEP), - PAD_CFG_TERM_GPO(GPP_F3, 0, NONE, DEEP), - PAD_CFG_TERM_GPO(GPP_F4, 0, NONE, DEEP), - PAD_CFG_GPI(GPP_F5, NONE, DEEP), - _PAD_CFG_STRUCT(GPP_F6, 0x44000101, 0x0000), - PAD_CFG_TERM_GPO(GPP_F7, 0, NONE, DEEP), - PAD_CFG_TERM_GPO(GPP_F8, 1, NONE, DEEP), - PAD_CFG_TERM_GPO(GPP_F9, 0, NONE, DEEP), - PAD_CFG_GPI(GPP_F10, NONE, DEEP), - PAD_CFG_GPI(GPP_F11, NONE, DEEP), - PAD_CFG_GPI(GPP_F12, NONE, DEEP), - PAD_CFG_GPI(GPP_F13, NONE, DEEP), - PAD_CFG_GPI(GPP_F14, NONE, DEEP), - _PAD_CFG_STRUCT(GPP_F15, 0x44000501, 0x3000), - _PAD_CFG_STRUCT(GPP_F16, 0x44000501, 0x3000), - _PAD_CFG_STRUCT(GPP_F17, 0x44000501, 0x3000), - _PAD_CFG_STRUCT(GPP_F18, 0x44000501, 0x3000), - PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), - PAD_CFG_TERM_GPO(GPP_F22, 1, NONE, DEEP), - PAD_CFG_TERM_GPO(GPP_F23, 1, NONE, DEEP), - PAD_CFG_GPI(GPP_G0, UP_20K, DEEP), - PAD_CFG_GPI(GPP_G1, UP_20K, DEEP), - PAD_CFG_GPI(GPP_G2, NONE, DEEP), - _PAD_CFG_STRUCT(GPP_G3, 0x44000101, 0x0000), - PAD_CFG_GPI(GPP_G4, NONE, DEEP), - PAD_CFG_TERM_GPO(GPP_G5, 0, NONE, DEEP), - PAD_CFG_TERM_GPO(GPP_G6, 0, NONE, DEEP), - PAD_CFG_TERM_GPO(GPP_G7, 0, NONE, DEEP), - PAD_CFG_NF(GPP_H0, NONE, DEEP, NF1), - PAD_CFG_TERM_GPO(GPP_H1, 0, NONE, DEEP), - PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1), - PAD_CFG_TERM_GPO(GPP_H3, 0, NONE, DEEP), - PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), - PAD_CFG_GPI(GPP_H5, DN_20K, DEEP), - PAD_CFG_TERM_GPO(GPP_H6, 0, NONE, DEEP), - PAD_CFG_TERM_GPO(GPP_H7, 0, NONE, DEEP), - PAD_CFG_TERM_GPO(GPP_H8, 0, NONE, DEEP), - PAD_CFG_TERM_GPO(GPP_H9, 0, NONE, DEEP), - PAD_CFG_TERM_GPO(GPP_H10, 0, NONE, DEEP), - PAD_CFG_TERM_GPO(GPP_H11, 0, NONE, DEEP), - PAD_CFG_TERM_GPO(GPP_H12, 0, NONE, DEEP), - PAD_CFG_GPI(GPP_H13, NONE, DEEP), - PAD_CFG_TERM_GPO(GPP_H14, 0, NONE, DEEP), - PAD_CFG_GPI(GPP_H15, NONE, DEEP), - PAD_CFG_TERM_GPO(GPP_H16, 0, NONE, DEEP), - PAD_CFG_TERM_GPO(GPP_H17, 0, NONE, DEEP), - PAD_CFG_TERM_GPO(GPP_H18, 0, NONE, DEEP), - PAD_CFG_TERM_GPO(GPP_H19, 0, NONE, DEEP), - PAD_CFG_TERM_GPO(GPP_H20, 0, NONE, DEEP), - PAD_CFG_TERM_GPO(GPP_H21, 0, NONE, DEEP), - PAD_CFG_TERM_GPO(GPP_H22, 0, NONE, DEEP), - PAD_CFG_GPI(GPP_H23, UP_20K, DEEP), - _PAD_CFG_STRUCT(GPP_I0, 0x40000700, 0x3c00), - _PAD_CFG_STRUCT(GPP_I1, 0x40000700, 0x3c00), - _PAD_CFG_STRUCT(GPP_I2, 0x40000700, 0x3c00), - _PAD_CFG_STRUCT(GPP_I3, 0x40000700, 0x0000), - _PAD_CFG_STRUCT(GPP_I4, 0x40000700, 0x0000), - _PAD_CFG_STRUCT(GPP_I5, 0x40000700, 0x0000), - _PAD_CFG_STRUCT(GPP_I6, 0x40000700, 0x0000), - _PAD_CFG_STRUCT(GPP_I7, 0x40000700, 0x0000), - _PAD_CFG_STRUCT(GPP_I8, 0x40000700, 0x0000), - _PAD_CFG_STRUCT(GPP_I9, 0x40000700, 0x1000), - _PAD_CFG_STRUCT(GPP_I10, 0x40000700, 0x1000), - _PAD_CFG_STRUCT(GPP_I11, 0x40000700, 0x3c00), - _PAD_CFG_STRUCT(GPP_I12, 0x40000700, 0x3c00), - _PAD_CFG_STRUCT(GPP_I13, 0x40000700, 0x3c00), - _PAD_CFG_STRUCT(GPP_I14, 0x40000700, 0x3c00), - _PAD_CFG_STRUCT(GPP_J0, 0x40000700, 0x3c00), - _PAD_CFG_STRUCT(GPP_J1, 0x40000700, 0x3c00), - _PAD_CFG_STRUCT(GPP_J2, 0x40000700, 0x3c00), - _PAD_CFG_STRUCT(GPP_J3, 0x40000700, 0x3c00), - _PAD_CFG_STRUCT(GPP_J4, 0x40000700, 0x3c00), - PAD_CFG_NF(GPP_J5, NONE, DEEP, NF1), - _PAD_CFG_STRUCT(GPP_J6, 0x46880100, 0x0000), - PAD_CFG_NF(GPP_J7, NONE, DEEP, NF1), - _PAD_CFG_STRUCT(GPP_J8, 0x46880100, 0x0000), - PAD_CFG_NF(GPP_J9, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_J10, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_J11, NONE, DEEP, NF1), - PAD_CFG_TERM_GPO(GPP_K0, 0, NONE, DEEP), - PAD_CFG_TERM_GPO(GPP_K1, 0, NONE, DEEP), - PAD_CFG_TERM_GPO(GPP_K2, 0, NONE, DEEP), - _PAD_CFG_STRUCT(GPP_K3, 0x40880100, 0x0000), - PAD_CFG_TERM_GPO(GPP_K4, 0, NONE, DEEP), - PAD_CFG_TERM_GPO(GPP_K5, 0, NONE, DEEP), - _PAD_CFG_STRUCT(GPP_K6, 0x40880100, 0x0000), - PAD_CFG_TERM_GPO(GPP_K7, 0, NONE, DEEP), - PAD_CFG_TERM_GPO(GPP_K8, 1, NONE, DEEP), - PAD_CFG_TERM_GPO(GPP_K9, 1, NONE, DEEP), - PAD_CFG_TERM_GPO(GPP_K10, 0, NONE, DEEP), - PAD_CFG_TERM_GPO(GPP_K11, 0, NONE, DEEP), - PAD_CFG_TERM_GPO(GPP_K12, 0, NONE, DEEP), - PAD_CFG_TERM_GPO(GPP_K13, 0, NONE, DEEP), - PAD_CFG_TERM_GPO(GPP_K14, 0, NONE, DEEP), - PAD_CFG_TERM_GPO(GPP_K15, 0, NONE, DEEP), - PAD_CFG_TERM_GPO(GPP_K16, 0, NONE, DEEP), - PAD_CFG_TERM_GPO(GPP_K17, 0, NONE, DEEP), - PAD_CFG_TERM_GPO(GPP_K18, 0, NONE, DEEP), - _PAD_CFG_STRUCT(GPP_K19, 0x42800101, 0x0000), - PAD_CFG_TERM_GPO(GPP_K20, 1, NONE, DEEP), - PAD_CFG_GPI(GPP_K21, NONE, DEEP), - _PAD_CFG_STRUCT(GPP_K22, 0x44000101, 0x0000), - PAD_CFG_TERM_GPO(GPP_K23, 1, NONE, DEEP), -}; - -#endif - -#endif diff --git a/src/mainboard/system76/whl-u/gpio.h b/src/mainboard/system76/whl-u/gpio.h index 4d480db3f1..57d4265f93 100644 --- a/src/mainboard/system76/whl-u/gpio.h +++ b/src/mainboard/system76/whl-u/gpio.h @@ -23,6 +23,19 @@ #define PAD_CFG_NC(pad) PAD_NC(pad, NONE) +/* Early pad configuration in romstage. */ +static const struct pad_config early_gpio_table[] = { + // UART2 + // UART2_RXD + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), + // UART2_TXD + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), + // NC + PAD_CFG_NC(GPP_C22), + // NC + PAD_CFG_NC(GPP_C23), +}; + /* Pad configuration in ramstage. */ static const struct pad_config gpio_table[] = { // GPD @@ -40,7 +53,7 @@ static const struct pad_config gpio_table[] = { // SUSC#_PCH PAD_CFG_NF(GPD5, NONE, DEEP, NF1), // SLP_A# - PAD_CFG_NC(GPD6), + PAD_CFG_NF(GPD6, NONE, DEEP, NF1), // GPIO // NC @@ -52,9 +65,9 @@ static const struct pad_config gpio_table[] = { // Power Management // GPD9_RTD3 - PAD_CFG_NF(GPD9, NONE, DEEP, NF1), + PAD_CFG_NC(GPD9), // NC - PAD_CFG_NC(GPD10), + PAD_CFG_NF(GPD10, NONE, DEEP, NF1), // NC PAD_CFG_NC(GPD11), @@ -85,7 +98,7 @@ static const struct pad_config gpio_table[] = { // PCLK_KBC PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), // NC - PAD_CFG_NC(GPP_A10), + PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1), // GSPI1 // NC @@ -101,7 +114,7 @@ static const struct pad_config gpio_table[] = { // LPC // NC - PAD_CFG_NC(GPP_A14), + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), // Power Management // SUS_PWR_ACK @@ -123,9 +136,9 @@ static const struct pad_config gpio_table[] = { // NC PAD_CFG_NC(GPP_A21), // PS8338B_SW - PAD_CFG_GPO(GPP_A22, 0, DEEP), + PAD_CFG_TERM_GPO(GPP_A22, 0, NONE, DEEP), // PS8338B_PCH - PAD_CFG_GPO(GPP_A23, 0, DEEP), + PAD_CFG_NC(GPP_A23), // GPP_B // Power @@ -219,19 +232,19 @@ static const struct pad_config gpio_table[] = { // TBCIO_PLUG_EVENT _PAD_CFG_STRUCT(GPP_C9, 0x82880100, 0x3000), // TBT_FRC_PWR - PAD_CFG_GPO(GPP_C10, 1, DEEP), + PAD_CFG_TERM_GPO(GPP_C10, 0, NONE, PLTRST), // NC PAD_CFG_NC(GPP_C11), // UART1 // GPP_C12_RTD3 - PAD_CFG_GPO(GPP_C12, 1, DEEP), + PAD_CFG_TERM_GPO(GPP_C12, 1, NONE, PLTRST), // SSD_PWR_DN# - PAD_CFG_GPO(GPP_C13, 1, DEEP), + PAD_CFG_TERM_GPO(GPP_C13, 1, NONE, PLTRST), // TBTA_HRESET - PAD_CFG_GPO(GPP_C14, 0, DEEP), + PAD_CFG_TERM_GPO(GPP_C14, 0, NONE, PLTRST), // TBT_PERST_N - PAD_CFG_GPO(GPP_C15, 1, DEEP), + PAD_CFG_TERM_GPO(GPP_C15, 1, UP_20K, PLTRST), // I2C // T_SDA @@ -276,11 +289,11 @@ static const struct pad_config gpio_table[] = { // NC PAD_CFG_NC(GPP_D7), // SB_BLON - PAD_CFG_GPO(GPP_D8, 1, DEEP), + PAD_CFG_TERM_GPO(GPP_D8, 1, NONE, DEEP), // GSPI2 // SWI# - PAD_CFG_GPI_SCI_LOW(GPP_D9, NONE, DEEP, LEVEL), + _PAD_CFG_STRUCT(GPP_D9, 0x40880100, 0x0000), // NC PAD_CFG_NC(GPP_D10), // RTD3_PCIE_WAKE# @@ -296,7 +309,7 @@ static const struct pad_config gpio_table[] = { // NC PAD_CFG_NC(GPP_D15), // RTD3_3G_PW R_EN - PAD_CFG_GPO(GPP_D16, 1, DEEP), + PAD_CFG_TERM_GPO(GPP_D16, 1, NONE, PWROK), // DMIC // NC @@ -365,7 +378,7 @@ static const struct pad_config gpio_table[] = { // SMI# _PAD_CFG_STRUCT(GPP_E15, 0x42840100, 0x0), // SCI# - PAD_CFG_GPI_SCI_LOW(GPP_E16, NONE, DEEP, LEVEL), + _PAD_CFG_STRUCT(GPP_E16, 0x80880100, 0x0000), // EDP_HPD PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), // MDP_CTRLCLK @@ -398,13 +411,13 @@ static const struct pad_config gpio_table[] = { // CNVI_BRI_DT PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), // CNVI_BRI_RSP - PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F5, UP_20K, DEEP, NF1), // CNVI_RGI_DT - PAD_CFG_NF(GPP_F6, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), // CNVI_RGI_RSP - PAD_CFG_NF(GPP_F7, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F7, UP_20K, DEEP, NF1), // CNVI_MFUART2_RXD - PAD_CFG_NF(GPP_F8, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), // CNVI_MFUART2_TXD PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), @@ -440,7 +453,7 @@ static const struct pad_config gpio_table[] = { // A4WP // A4WP_PRESENT - PAD_CFG_NF(GPP_F23, NONE, DEEP, NF1), + PAD_CFG_GPI(GPP_F23, DN_20K, DEEP), // GPP_G // SD @@ -466,9 +479,9 @@ static const struct pad_config gpio_table[] = { // NC PAD_CFG_NC(GPP_H0), // CNVI_RST# - PAD_CFG_NF(GPP_H1, DN_20K, DEEP, NF3), + PAD_CFG_NF(GPP_H1, NONE, DEEP, NF3), // CNVI_CLKREQ - PAD_CFG_NF(GPP_H2, DN_20K, DEEP, NF3), + PAD_CFG_NF(GPP_H2, NONE, DEEP, NF3), // NC PAD_CFG_NC(GPP_H3), @@ -524,18 +537,9 @@ static const struct pad_config gpio_table[] = { // GPPC_H21 PAD_CFG_NC(GPP_H21), // TBT_RTD3_PWR_EN_R - PAD_CFG_GPO(GPP_H22, 1, DEEP), + PAD_CFG_TERM_GPO(GPP_H22, 1, NONE, PLTRST), // NC, WIGIG_PEWAKE - PAD_CFG_GPO(GPP_H23, 1, DEEP), -}; - -/* Early pad configuration in romstage. */ -static const struct pad_config early_gpio_table[] = { - // UART2 - // UART2_RXD - PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), - // UART2_TXD - PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), + PAD_CFG_NC(GPP_H23), }; #endif