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soc/samsung: Drop unneeded empty lines

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Change-Id: Ib2843c40de8e4607b8b9d665761a689227878bc0
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44600
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
This commit is contained in:
Elyes HAOUAS
2020-08-19 21:45:24 +02:00
committed by Michael Niewöhner
parent 0180e43f3d
commit 0c2724c844
11 changed files with 0 additions and 29 deletions
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1
src/soc/samsung/exynos5250/fb.c
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@@ -508,7 +508,6 @@ int dp_controller_init(struct s5p_dp_device *dp_device)
return ret; return ret;
} }
base = dp->base; base = dp->base;
/* Enable enhanced mode */ /* Enable enhanced mode */
setbits32(&base->sys_ctl_4, ENHANCED); setbits32(&base->sys_ctl_4, ENHANCED);

6
src/soc/samsung/exynos5250/i2c.c
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@@ -94,9 +94,6 @@ static struct s3c24x0_i2c_bus i2c_busses[] = {
}, },
}; };
static int i2c_int_pending(struct i2c_regs *regs) static int i2c_int_pending(struct i2c_regs *regs)
{ {
return read8(&regs->con) & I2cConIntPending; return read8(&regs->con) & I2cConIntPending;
@@ -146,9 +143,6 @@ static int i2c_wait_for_int(struct i2c_regs *regs)
return 1; return 1;
} }
static int i2c_send_stop(struct i2c_regs *regs) static int i2c_send_stop(struct i2c_regs *regs)
{ {
uint8_t mode = read8(&regs->stat) & (I2cStatModeMask); uint8_t mode = read8(&regs->stat) & (I2cStatModeMask);

1
src/soc/samsung/exynos5250/include/soc/dsim.h
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@@ -52,7 +52,6 @@ check_member(exynos5_dsim, phyacchr1, 0x54);
#define VIDEO_MODE (1 << 25) #define VIDEO_MODE (1 << 25)
#define BURST_MODE (1 << 26) #define BURST_MODE (1 << 26)
#define DSIM_PHYACCHR_AFC_EN (1 << 14) #define DSIM_PHYACCHR_AFC_EN (1 << 14)
#define DSIM_PHYACCHR_AFC_CTL_OFFSET 5 #define DSIM_PHYACCHR_AFC_CTL_OFFSET 5

1
src/soc/samsung/exynos5250/include/soc/setup.h
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@@ -141,7 +141,6 @@ struct exynos5_phy_control;
| (CPUD_RATIO << 4) \ | (CPUD_RATIO << 4) \
| (ARM_RATIO)) | (ARM_RATIO))
/* CLK_FSYS */ /* CLK_FSYS */
#define CLK_SRC_FSYS0_VAL 0x66666 #define CLK_SRC_FSYS0_VAL 0x66666
#define CLK_DIV_FSYS0_VAL 0x0BB00000 #define CLK_DIV_FSYS0_VAL 0x0BB00000

2
src/soc/samsung/exynos5420/dp.c
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@@ -31,7 +31,6 @@
* 11. Source sends video data. * 11. Source sends video data.
*/ */
static int exynos_dp_init_dp(void) static int exynos_dp_init_dp(void)
{ {
int ret; int ret;
@@ -843,7 +842,6 @@ int exynos_init_dp(struct edp_device_info *edp_info)
{ {
unsigned int ret; unsigned int ret;
dp_phy_control(1); dp_phy_control(1);
ret = exynos_dp_init_dp(); ret = exynos_dp_init_dp();

2
src/soc/samsung/exynos5420/dp_lowlevel.c
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@@ -75,7 +75,6 @@ void exynos_dp_enable_video_mute(unsigned int enable)
return; return;
} }
static void exynos_dp_init_analog_param(void) static void exynos_dp_init_analog_param(void)
{ {
u32 reg; u32 reg;
@@ -999,7 +998,6 @@ int exynos_dp_init_video(void)
return 0; return 0;
} }
void exynos_dp_config_video_slave_mode(struct edp_video_info *video_info) void exynos_dp_config_video_slave_mode(struct edp_video_info *video_info)
{ {
u32 reg; u32 reg;

10
src/soc/samsung/exynos5420/i2c.c
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@@ -71,7 +71,6 @@ struct i2c_bus
unsigned int clk_div; unsigned int clk_div;
}; };
static struct i2c_bus i2c_busses[] = { static struct i2c_bus i2c_busses[] = {
{ {
.bus_num = 0, .bus_num = 0,
@@ -236,9 +235,6 @@ enum {
I2cStatMasterXmit = 0x3 << 6 I2cStatMasterXmit = 0x3 << 6
}; };
static int hsi2c_get_clk_details(struct i2c_bus *i2c, int *div, int *cycle, static int hsi2c_get_clk_details(struct i2c_bus *i2c, int *div, int *cycle,
unsigned int op_clk) unsigned int op_clk)
{ {
@@ -487,9 +483,6 @@ static int hsi2c_transfer(struct i2c_bus *i2c, struct i2c_msg *segments,
return 0; return 0;
} }
static int i2c_int_pending(struct i2c_regs *regs) static int i2c_int_pending(struct i2c_regs *regs)
{ {
return read8(&regs->con) & I2cConIntPending; return read8(&regs->con) & I2cConIntPending;
@@ -539,9 +532,6 @@ static int i2c_wait_for_int(struct i2c_regs *regs)
return 1; return 1;
} }
static int i2c_send_stop(struct i2c_regs *regs) static int i2c_send_stop(struct i2c_regs *regs)
{ {
uint8_t mode = read8(&regs->stat) & (I2cStatModeMask); uint8_t mode = read8(&regs->stat) & (I2cStatModeMask);

1
src/soc/samsung/exynos5420/include/soc/dmc.h
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@@ -300,7 +300,6 @@ enum {
MEM_TIMINGS_MSR_COUNT = 5, MEM_TIMINGS_MSR_COUNT = 5,
}; };
/* These are the memory timings for a particular memory type and speed */ /* These are the memory timings for a particular memory type and speed */
struct mem_timings { struct mem_timings {
enum mem_manuf mem_manuf; /* Memory manufacturer */ enum mem_manuf mem_manuf; /* Memory manufacturer */

2
src/soc/samsung/exynos5420/include/soc/dp.h
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@@ -1338,12 +1338,10 @@ enum {
VIDEO_TIMING_FROM_REGISTER VIDEO_TIMING_FROM_REGISTER
}; };
struct exynos_dp_platform_data { struct exynos_dp_platform_data {
struct edp_device_info *edp_dev_info; struct edp_device_info *edp_dev_info;
}; };
int exynos_init_dp(struct edp_device_info *edp_info); int exynos_init_dp(struct edp_device_info *edp_info);
void exynos_set_dp_platform_data(struct exynos_dp_platform_data *pd); void exynos_set_dp_platform_data(struct exynos_dp_platform_data *pd);

1
src/soc/samsung/exynos5420/include/soc/dsim.h
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@@ -52,7 +52,6 @@ check_member(exynos5_dsim, phyacchr1, 0x54);
#define VIDEO_MODE (1 << 25) #define VIDEO_MODE (1 << 25)
#define BURST_MODE (1 << 26) #define BURST_MODE (1 << 26)
#define DSIM_PHYACCHR_AFC_EN (1 << 14) #define DSIM_PHYACCHR_AFC_EN (1 << 14)
#define DSIM_PHYACCHR_AFC_CTL_OFFSET 5 #define DSIM_PHYACCHR_AFC_CTL_OFFSET 5

2
src/soc/samsung/exynos5420/include/soc/setup.h
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@@ -642,7 +642,6 @@ struct exynos5_phy_control;
#define CTRL_FORCE_MASK (0x7F << 8) #define CTRL_FORCE_MASK (0x7F << 8)
#define CTRL_LOCK_COARSE_MASK (0x7F << 10) #define CTRL_LOCK_COARSE_MASK (0x7F << 10)
#define CTRL_OFFSETD_RESET_VAL 0x8 #define CTRL_OFFSETD_RESET_VAL 0x8
#define CTRL_OFFSETD_VAL 0x7F #define CTRL_OFFSETD_VAL 0x7F
@@ -711,7 +710,6 @@ struct exynos5_phy_control;
#define PHY_CON39_VAL_34_OHM 0x0DB60DB6 #define PHY_CON39_VAL_34_OHM 0x0DB60DB6
#define PHY_CON39_VAL_30_OHM 0x0FFF0FFF #define PHY_CON39_VAL_30_OHM 0x0FFF0FFF
#define CTRL_BSTLEN_OFFSET 8 #define CTRL_BSTLEN_OFFSET 8
#define CTRL_RDLAT_OFFSET 0 #define CTRL_RDLAT_OFFSET 0