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oryp7

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Change-Id: Id5b960a8a8929063e0b0e56e079324c80f2b6638
This commit is contained in:
Jeremy Soller
2021-02-20 19:29:20 -07:00
committed by Jeremy Soller
parent 6c748392f2
commit 0c2cc3e73e
18 changed files with 1915 additions and 0 deletions
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88
src/mainboard/system76/oryp7/Kconfig Normal file
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if BOARD_SYSTEM76_ORYP7
config BOARD_SPECIFIC_OPTIONS
def_bool y
select BOARD_ROMSIZE_KB_16384
select DRIVERS_I2C_HID
select DRIVERS_I2C_TAS5825M
select DRIVERS_SYSTEM76_DGPU
select EC_SYSTEM76_EC
select EC_SYSTEM76_EC_BAT_THRESHOLDS
select EC_SYSTEM76_EC_COLOR_KEYBOARD
select EC_SYSTEM76_EC_DGPU
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select HAVE_CMOS_DEFAULT
select HAVE_OPTION_TABLE
select INTEL_GMA_HAVE_VBT
select INTEL_LPSS_UART_FOR_CONSOLE
select MAINBOARD_HAS_LPC_TPM
select MAINBOARD_HAS_TPM2
select NO_UART_ON_SUPERIO
select PCIEXP_HOTPLUG
select SOC_INTEL_CANNONLAKE_PCH_H
select SOC_INTEL_COMETLAKE_1
select SOC_INTEL_COMMON_BLOCK_HDA_VERB
select SPD_READ_BY_WORD
select SYSTEM_TYPE_LAPTOP
select TPM_RDRESP_NEED_DELAY
select USE_LEGACY_8254_TIMER # Fix failure to boot GRUB
select USE_OPTION_TABLE
config MAINBOARD_DIR
string
default "system76/oryp7"
config MAINBOARD_PART_NUMBER
string
default "oryp7"
config MAINBOARD_SMBIOS_PRODUCT_NAME
string
default "Oryx Pro"
config MAINBOARD_VERSION
string
default "oryp7"
config CBFS_SIZE
hex
default 0xA00000
config CONSOLE_POST
bool
default y
config ONBOARD_VGA_IS_PRIMARY
bool
default y
config UART_FOR_CONSOLE
int
default 2
config MAX_CPUS
int
default 16
config DIMM_MAX
int
default 2
config DIMM_SPD_SIZE
int
default 512
config VGA_BIOS_FILE
string
default "pci8086,9bc4.rom"
config VGA_BIOS_ID
string
default "8086,9bc4"
config POST_DEVICE
bool
default n
endif

2
src/mainboard/system76/oryp7/Kconfig.name Normal file
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config BOARD_SYSTEM76_ORYP7
bool "oryp7"

4
src/mainboard/system76/oryp7/Makefile.inc Normal file
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bootblock-y += bootblock.c
ramstage-y += ramstage.c
ramstage-y += hda_verb.c
ramstage-y += tas5825m.c

30
src/mainboard/system76/oryp7/acpi/backlight.asl Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <drivers/intel/gma/acpi/gma.asl>
Scope (GFX0) {
Name (BRIG, Package (22) {
40, /* default AC */
40, /* default Battery */
5,
10,
15,
20,
25,
30,
35,
40,
45,
50,
55,
60,
65,
70,
75,
80,
85,
90,
95,
100
})
}

11
src/mainboard/system76/oryp7/acpi/gpe.asl Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
// GPP_K6 SCI
Method (_L06, 0, Serialized) {
Debug = Concatenate("GPE _L06: ", ToHexString(\_SB.PCI0.LPCB.EC0.WFNO))
If (\_SB.PCI0.LPCB.EC0.ECOK) {
If (\_SB.PCI0.LPCB.EC0.WFNO == 1) {
Notify(\_SB.LID0, 0x80)
}
}
}

20
src/mainboard/system76/oryp7/acpi/mainboard.asl Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include "../gpio.h"
#include <drivers/system76/dgpu/acpi/dgpu.asl>
#define EC_GPE_SCI 0x03 /* GPP_K3 */
#define EC_GPE_SWI 0x06 /* GPP_K6 */
#define EC_COLOR_KEYBOARD 1
#include <ec/system76/ec/acpi/ec.asl>
Scope (\_SB) {
#include "sleep.asl"
Scope (PCI0) {
#include "backlight.asl"
}
}
Scope (\_GPE) {
#include "gpe.asl"
}

14
src/mainboard/system76/oryp7/acpi/sleep.asl Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
/* Method called from _PTS prior to enter sleep state */
Method (MPTS, 1) {
\_SB.PCI0.LPCB.EC0.PTS (Arg0)
// Turn DGPU on before sleeping
\_SB.PCI0.PEGP.DEV0._ON()
}
/* Method called from _WAK prior to wakeup */
Method (MWAK, 1) {
\_SB.PCI0.LPCB.EC0.WAK (Arg0)
}

8
src/mainboard/system76/oryp7/board_info.txt Normal file
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Vendor name: System76
Board name: oryp7
Category: laptop
Release year: 2021
ROM package: SOIC-8
ROM protocol: SPI
ROM socketed: n
Flashrom support: y

11
src/mainboard/system76/oryp7/bootblock.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <bootblock_common.h>
#include <gpio.h>
#include "gpio.h"
#include <drivers/system76/dgpu/bootblock.c>
void bootblock_mainboard_init(void) {
gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
dgpu_power_enable(1);
}

2
src/mainboard/system76/oryp7/cmos.default Normal file
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boot_option=Fallback
preserve_smmstore=0

35
src/mainboard/system76/oryp7/cmos.layout Normal file
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# SPDX-License-Identifier: GPL-2.0-only
entries
0 384 r 0 reserved_memory
# RTC_BOOT_BYTE (coreboot hardcoded)
384 1 e 2 boot_option
388 4 h 0 reboot_counter
#395 4 e 3 debug_level
408 1 h 1 preserve_smmstore
984 16 h 0 check_sum
enumerations
1 0 Disable
1 1 Enable
2 0 Fallback
2 1 Normal
3 0 Emergency
3 1 Alert
3 2 Critical
3 3 Error
3 4 Warning
3 5 Notice
3 6 Info
3 7 Debug
3 8 Spew
checksums
checksum 392 983 984

222
src/mainboard/system76/oryp7/devicetree.cb Normal file
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chip soc/intel/cannonlake
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
// Touchpad I2C bus
.i2c[0] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 80,
.fall_time_ns = 110,
},
}"
# CPU (soc/intel/cannonlake/cpu.c)
# Power limit
register "power_limits_config" = "{
.tdp_pl1_override = 45,
.tdp_pl2_override = 90,
}"
# Enable Enhanced Intel SpeedStep
register "eist_enable" = "1"
# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c)
register "enable_c6dram" = "1"
# FSP Silicon (soc/intel/cannonlake/fsp_params.c)
# Serial I/O
register "SerialIoDevMode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci, // Touchpad I2C bus
[PchSerialIoIndexUART2] = PchSerialIoSkipInit, // Debug console
}"
# Misc
register "AcousticNoiseMitigation" = "1"
# Power
register "PchPmSlpS3MinAssert" = "3" # 50ms
register "PchPmSlpS4MinAssert" = "1" # 1s
register "PchPmSlpSusMinAssert" = "4" # 4s
register "PchPmSlpAMinAssert" = "4" # 2s
# Thermal
register "tcc_offset" = "8"
# Serial IRQ Continuous
register "serirq_mode" = "SERIRQ_CONTINUOUS"
# PM Util (soc/intel/cannonlake/pmutil.c)
# GPE configuration
# Note that GPE events called out in ASL code rely on this
# route. i.e. If this route changes then the affected GPE
# offset bits also need to be changed.
register "gpe0_dw0" = "PMC_GPP_K"
register "gpe0_dw1" = "PMC_GPP_G"
register "gpe0_dw2" = "PMC_GPP_E"
# Actual device tree
device cpu_cluster 0 on
device lapic 0 on end
end
device domain 0 on
subsystemid 0x1558 0x65e5 inherit
device pci 00.0 on end # Host Bridge
device pci 01.0 on # GPU Port
# PCI Express Graphics #0 x16, Clock 8 (NVIDIA GPU)
register "PcieClkSrcUsage[8]" = "0x40"
register "PcieClkSrcClkReq[8]" = "8"
end
device pci 02.0 on # Integrated Graphics Device
register "gfx" = "GMA_DEFAULT_PANEL(0)"
end
device pci 04.0 on # SA Thermal device
register "Device4Enable" = "1"
end
device pci 12.0 on end # Thermal Subsystem
device pci 12.5 off end # UFS SCS
device pci 12.6 off end # GSPI #2
device pci 13.0 off end # Integrated Sensor Hub
device pci 14.0 on # USB xHCI
# USB2
register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # USB 3 Left
register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C
register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # USB 3 Right 1
register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # USB 3 Right 2
register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Per-key RGB
register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Camera
register "usb2_ports[10]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint
register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
# USB3
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3 Left
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3 right 1
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3 right 2
end
device pci 14.1 off end # USB xDCI (OTG)
device pci 14.2 on end # Shared SRAM
device pci 14.3 on # CNVi wifi
#chip drivers/intel/wifi
# register "wake" = "PME_B0_EN_BIT"
#end
end
device pci 14.5 off end # SDCard
device pci 15.0 on
chip drivers/i2c/hid
register "generic.hid" = ""PNP0C50""
register "generic.desc" = ""Synaptics Touchpad""
register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)"
register "generic.probed" = "1"
register "hid_desc_reg_offset" = "0x20"
device i2c 2c on end
end
end # I2C #0
device pci 15.1 off end # I2C #1
device pci 15.2 off end # I2C #2
device pci 15.3 off end # I2C #3
device pci 16.0 off end # Management Engine Interface 1
device pci 16.1 off end # Management Engine Interface 2
device pci 16.2 off end # Management Engine IDE-R
device pci 16.3 off end # Management Engine KT Redirection
device pci 16.4 off end # Management Engine Interface 3
device pci 16.5 off end # Management Engine Interface 4
device pci 17.0 on # SATA
register "SataPortsEnable[1]" = "1" # SSD (SATA1A)
end
device pci 19.0 off end # I2C #4
device pci 19.1 off end # I2C #5
device pci 19.2 on end # UART #2
device pci 1a.0 off end # eMMC
device pci 1b.0 on # PCI Express Port 17
# PCI Express root port #17 x4, Clock 0 (Thunderbolt)
register "PcieRpEnable[16]" = "1"
register "PcieRpLtrEnable[16]" = "1"
register "PcieRpHotPlug[16]" = "1"
register "PcieClkSrcUsage[0]" = "16"
register "PcieClkSrcClkReq[0]" = "0"
register "PcieRpSlotImplemented[16]" = "1"
end
device pci 1b.1 off end # PCI Express Port 18
device pci 1b.2 off end # PCI Express Port 19
device pci 1b.3 off end # PCI Express Port 20
device pci 1b.4 on # PCI Express Port 21
# PCI Express root port #21 x4, Clock 11 (SSD2)
register "PcieRpEnable[20]" = "1"
register "PcieRpLtrEnable[20]" = "1"
register "PcieClkSrcUsage[11]" = "20"
register "PcieClkSrcClkReq[11]" = "11"
register "PcieRpSlotImplemented[20]" = "1"
end
device pci 1b.5 off end # PCI Express Port 22
device pci 1b.6 off end # PCI Express Port 23
device pci 1b.7 off end # PCI Express Port 24
device pci 1c.0 off end # PCI Express Port 1
device pci 1c.1 off end # PCI Express Port 2
device pci 1c.2 off end # PCI Express Port 3
device pci 1c.3 off end # PCI Express Port 4
device pci 1c.4 off end # PCI Express Port 5
device pci 1c.5 off end # PCI Express Port 6
device pci 1c.6 off end # PCI Express Port 7
device pci 1c.7 off end # PCI Express Port 8
device pci 1d.0 on # PCI Express Port 9
# PCI Express root port #9 x4, Clock 12 (SSD1)
register "PcieRpEnable[8]" = "1"
register "PcieRpLtrEnable[8]" = "1"
register "PcieClkSrcUsage[12]" = "8"
register "PcieClkSrcClkReq[12]" = "12"
register "PcieRpSlotImplemented[8]" = "1"
end
device pci 1d.1 off end # PCI Express Port 10
device pci 1d.2 off end # PCI Express Port 11
device pci 1d.3 off end # PCI Express Port 12
device pci 1d.4 off end # PCI Express Port 13
device pci 1d.5 on # PCI Express Port 14
# PCI Express root port #14 x1, Clock 7 (GLAN)
register "PcieRpEnable[13]" = "1"
register "PcieRpLtrEnable[13]" = "1"
register "PcieClkSrcUsage[7]" = "13"
register "PcieClkSrcClkReq[7]" = "7"
register "PcieRpSlotImplemented[13]" = "1"
end
device pci 1d.6 on # PCI Express Port 15
# PCI Express root port #15 x1, Clock 9 (Card Reader)
register "PcieRpEnable[14]" = "1"
register "PcieRpLtrEnable[14]" = "1"
register "PcieClkSrcUsage[9]" = "14"
register "PcieClkSrcClkReq[9]" = "9"
register "PcieRpSlotImplemented[14]" = "1"
end
device pci 1d.7 on # PCI Express Port 16
# PCI Express root port #16 x1, Clock 6 (WLAN)
register "PcieRpEnable[15]" = "1"
register "PcieRpLtrEnable[15]" = "1"
register "PcieClkSrcUsage[6]" = "15"
register "PcieClkSrcClkReq[6]" = "6"
register "PcieRpSlotImplemented[15]" = "1"
end
device pci 1e.0 off end # UART #0
device pci 1e.1 off end # UART #1
device pci 1e.2 off end # GSPI #0
device pci 1e.3 off end # GSPI #1
device pci 1f.0 on # LPC Interface
register "gen1_dec" = "0x000c0081"
register "gen2_dec" = "0x00040069"
register "gen3_dec" = "0x00fc0e01"
register "gen4_dec" = "0x00fc0f01"
chip drivers/pc80/tpm
device pnp 0c31.0 on end
end
end
device pci 1f.1 off end # P2SB
device pci 1f.2 off end # Power Management Controller
device pci 1f.3 on # Intel HDA
register "PchHdaAudioLinkHda" = "1"
end
device pci 1f.4 on # SMBus
chip drivers/i2c/tas5825m
register "id" = "0"
device i2c 4e on end # (8bit address: 0x9c)
end
end
device pci 1f.5 on end # PCH SPI
device pci 1f.6 off end # GbE
end
end

31
src/mainboard/system76/oryp7/dsdt.asl Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi.h>
DefinitionBlock(
"dsdt.aml",
"DSDT",
ACPI_DSDT_REV_2,
OEM_ID,
ACPI_TABLE_CREATOR,
0x20110725 // OEM revision
)
{
#include <soc/intel/common/block/acpi/acpi/platform.asl>
#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
#include <cpu/intel/common/acpi/cpu.asl>
Device (\_SB.PCI0)
{
#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
#include <soc/intel/cannonlake/acpi/southbridge.asl>
}
#include <southbridge/intel/common/acpi/sleepstates.asl>
Scope (\_SB.PCI0.LPCB)
{
#include <drivers/pc80/pc/ps2_controller.asl>
}
#include "acpi/mainboard.asl"
}

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src/mainboard/system76/oryp7/gpio.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef MAINBOARD_GPIO_H
#define MAINBOARD_GPIO_H
#define DGPU_RST_N GPP_F22
#define DGPU_PWR_EN GPP_F23
#define DGPU_GC6 GPP_K21
#ifndef __ACPI__
#include <soc/gpe.h>
#include <soc/gpio.h>
/* Pad configuration in romstage. */
static const struct pad_config early_gpio_table[] = {
PAD_CFG_TERM_GPO(GPP_C14, 1, NONE, RSMRST), // M.2_PLT_RST_CNTRL1#
PAD_CFG_TERM_GPO(GPP_C15, 1, NONE, RSMRST), // M.2_PLT_RST_CNTRL2#
PAD_CFG_TERM_GPO(GPP_F0, 1, NONE, RSMRST), // TBT_PERST_N
PAD_CFG_TERM_GPO(GPP_F22, 0, NONE, DEEP), // DGPU_RST_N
PAD_CFG_TERM_GPO(GPP_F23, 0, NONE, DEEP), // DGPU_PWR_EN
PAD_CFG_TERM_GPO(GPP_H16, 1, NONE, RSMRST), // TBT_RTD3_PWR_EN_R
PAD_CFG_TERM_GPO(GPP_K8, 1, NONE, RSMRST), // SATA_M2_PWR_EN1
PAD_CFG_TERM_GPO(GPP_K9, 1, NONE, RSMRST), // SATA_M2_PWR_EN2
PAD_CFG_TERM_GPO(GPP_K11, 1, NONE, RSMRST), // GPIO_LANRTD3
};
/* Pad configuration in ramstage. */
static const struct pad_config gpio_table[] = {
/* ------- GPIO Group GPD ------- */
PAD_CFG_NF(GPD0, NONE, DEEP, NF1), // PM_BATLOW#
PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1), // AC_PRESENT
PAD_CFG_GPI(GPD2, NATIVE, PWROK), // LAN_WAKEUP#
PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), // PWR_BTN#
PAD_CFG_NF(GPD4, NONE, DEEP, NF1), // SUSB#_PCH
PAD_CFG_NF(GPD5, NONE, DEEP, NF1), // SUSC#_PCH
PAD_NC(GPD6, UP_20K),
PAD_CFG_GPI(GPD7, UP_20K, PWROK), // GPD_7 (crystal input, low = single ended, high = differential)
PAD_CFG_NF(GPD8, NONE, DEEP, NF1), // SUS_CLK
PAD_NC(GPD9, UP_20K),
PAD_CFG_NF(GPD10, NONE, DEEP, NF1), // SLP_S5#
PAD_NC(GPD11, UP_20K),
/* ------- GPIO Group GPP_A ------- */
PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), // SB_KBCRST#
PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), // LPC_AD0
PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), // LPC_AD1
PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), // LPC_AD2
PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), // LPC_AD3
PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), // LPC_FRAME#
PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), // SERIRQ
PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), // LPC_PIRQA#
PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), // PM_CLKRUN#
PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), // PCLK_KBC
PAD_NC(GPP_A10, UP_20K),
PAD_CFG_GPI(GPP_A11, UP_20K, DEEP), // LAN_WAKEUP#
PAD_CFG_TERM_GPO(GPP_A12, 1, NONE, DEEP), // ROM_I2C_EN
PAD_NC(GPP_A13, NONE), // SUSWARN# (test point)
PAD_NC(GPP_A14, NONE),
PAD_NC(GPP_A15, NONE), // SUS_PWR_ACK# (test point)
PAD_NC(GPP_A16, UP_20K),
PAD_NC(GPP_A17, UP_20K),
PAD_NC(GPP_A18, UP_20K), // GPP_A18 (test point)
PAD_CFG_TERM_GPO(GPP_A19, 1, NONE, DEEP), // SB_BLON
PAD_NC(GPP_A20, NONE),
PAD_CFG_GPI(GPP_A21, UP_20K, DEEP), // EAPD_MODE
PAD_CFG_TERM_GPO(GPP_A22, 1, NONE, DEEP), // WLAN_SSD2_GPIO1
PAD_CFG_TERM_GPO(GPP_A23, 1, NONE, DEEP), // WLAN_SSD2_GPIO
/* ------- GPIO Group GPP_B ------- */
_PAD_CFG_STRUCT(GPP_B0, 0x42080100, 0x3000), // TPM_PIRQ#
PAD_NC(GPP_B1, UP_20K),
PAD_NC(GPP_B2, UP_20K),
PAD_CFG_TERM_GPO(GPP_B3, 1, NONE, DEEP), // BT_EN
PAD_CFG_TERM_GPO(GPP_B4, 1, NONE, DEEP), // WLAN_EN
PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), // TBT_CLKREQ#
PAD_CFG_GPI(GPP_B6, NONE, DEEP), // DDS_ID0
PAD_CFG_TERM_GPO(GPP_B7, 1, NONE, PLTRST), // CR_GPIO_RST#
PAD_CFG_TERM_GPO(GPP_B8, 1, NONE, PLTRST), // CR_GPIO_WAKE#
PAD_CFG_GPI(GPP_B9, NONE, DEEP), // DDS_DET
PAD_CFG_GPI(GPP_B10, NONE, DEEP), // GSYNC_DET
PAD_NC(GPP_B11, UP_20K),
PAD_CFG_GPI(GPP_B12, UP_20K, DEEP), // SLP_S0#
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST#
PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), // PCH_SPKR
PAD_NC(GPP_B15, UP_20K),
PAD_NC(GPP_B16, UP_20K),
PAD_NC(GPP_B17, UP_20K),
PAD_NC(GPP_B18, UP_20K), // LPSS_GSPI0_MOSI (test point)
PAD_NC(GPP_B19, UP_20K),
PAD_NC(GPP_B20, UP_20K),
PAD_NC(GPP_B21, UP_20K),
PAD_CFG_GPI(GPP_B22, UP_20K, DEEP), // LPSS_GSPI1_MOSI (boot strap)
PAD_CFG_NF(GPP_B23, NONE, DEEP, NF2), // PCH_HOT_GNSS_DISABLE (boot strap)
/* ------- GPIO Group GPP_C ------- */
PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK
PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DATA
PAD_CFG_GPI(GPP_C2, UP_20K, DEEP), // CNVI_WAKE#
PAD_NC(GPP_C3, UP_20K),
PAD_NC(GPP_C4, UP_20K),
PAD_CFG_GPI(GPP_C5, UP_20K, DEEP), // WLAN_WAKEUP#
PAD_CFG_GPI(GPP_C6, UP_20K, DEEP), // SMC_CPU_THERM
PAD_CFG_GPI(GPP_C7, UP_20K, DEEP), // SMD_CPU_THERM
PAD_CFG_GPI(GPP_C8, NONE, PLTRST), // TPM_DET
PAD_CFG_GPI(GPP_C9, NONE, DEEP), // CNVI_DET#
PAD_NC(GPP_C10, UP_20K),
PAD_NC(GPP_C11, UP_20K),
PAD_NC(GPP_C12, UP_20K),
PAD_NC(GPP_C13, UP_20K),
PAD_CFG_TERM_GPO(GPP_C14, 1, NONE, RSMRST), // M.2_PLT_RST_CNTRL1#
PAD_CFG_TERM_GPO(GPP_C15, 1, NONE, RSMRST), // M.2_PLT_RST_CNTRL2#
PAD_CFG_NF(GPP_C16, NONE, PLTRST, NF1), // I2C_SDA_TP
PAD_CFG_NF(GPP_C17, NONE, PLTRST, NF1), // I2C_SCL_TP
PAD_CFG_NF(GPP_C18, NONE, PLTRST, NF1), // I2C_SDA_Pantone
PAD_CFG_NF(GPP_C19, NONE, PLTRST, NF1), // I2C_SCL_Pantone
PAD_CFG_GPI(GPP_C20, UP_20K, DEEP), // CNVI_MFUART2_RXD
PAD_CFG_GPI(GPP_C21, UP_20K, DEEP), // CNVI_MFUART2_TXD
PAD_CFG_GPI(GPP_C22, UP_20K, DEEP), // LAN_PLT_RST#
PAD_NC(GPP_C23, UP_20K),
/* ------- GPIO Group GPP_D ------- */
PAD_NC(GPP_D0, UP_20K),
PAD_NC(GPP_D1, UP_20K),
PAD_NC(GPP_D2, UP_20K),
PAD_NC(GPP_D3, UP_20K),
PAD_CFG_NF(GPP_D4, NONE, PLTRST, NF2), // I2C_SDA_PDROM
PAD_CFG_NF(GPP_D5, NONE, DEEP, NF3), // CNVI_RST#
PAD_CFG_NF(GPP_D6, NONE, DEEP, NF3), // CNVI_CLKREQ
PAD_NC(GPP_D7, UP_20K), // M.2_BT_PCMIN (test point)
PAD_NC(GPP_D8, UP_20K), // M.2_BT_PCMCLK (test point)
PAD_NC(GPP_D9, UP_20K),
PAD_NC(GPP_D10, UP_20K),
PAD_NC(GPP_D11, UP_20K),
PAD_NC(GPP_D12, UP_20K),
PAD_NC(GPP_D13, UP_20K),
PAD_NC(GPP_D14, UP_20K),
PAD_NC(GPP_D15, UP_20K),
PAD_NC(GPP_D16, UP_20K),
PAD_NC(GPP_D17, UP_20K),
PAD_NC(GPP_D18, UP_20K),
PAD_NC(GPP_D19, UP_20K),
PAD_NC(GPP_D20, UP_20K),
PAD_NC(GPP_D21, UP_20K),
PAD_NC(GPP_D22, UP_20K),
PAD_CFG_NF(GPP_D23, NONE, PLTRST, NF2), // I2C_SCL_PDROM
/* ------- GPIO Group GPP_E ------- */
PAD_NC(GPP_E0, UP_20K),
PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), // M.2_SSD1_PEDET
PAD_NC(GPP_E2, UP_20K),
PAD_CFG_GPI(GPP_E3, NONE, DEEP), // 10k pull up
PAD_NC(GPP_E4, UP_20K),
PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), // M2_P1_SATA_DEVSLP
_PAD_CFG_STRUCT(GPP_E6, 0x82040100, 0x0000), // SMI#
PAD_CFG_GPI_APIC_LOW(GPP_E7, NONE, PLTRST), // TP_ATTN#
PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), // PCH_SATAHDD_LED#
PAD_NC(GPP_E9, UP_20K), // USB_OC0# (test point)
PAD_NC(GPP_E10, UP_20K), // USB_OC1# (test point)
PAD_NC(GPP_E11, UP_20K), // USB_OC2# (test point)
PAD_NC(GPP_E12, UP_20K), // USB_OC3# (test point)
/* ------- GPIO Group GPP_F ------- */
PAD_CFG_TERM_GPO(GPP_F0, 1, NONE, RSMRST), // TBT_PERST_N
PAD_CFG_GPI(GPP_F1, NONE, DEEP), // M.2_SSD2_PEDET (board error)
PAD_CFG_GPI(GPP_F2, NONE, DEEP), // TBTA_HRESET
PAD_NC(GPP_F3, UP_20K),
PAD_NC(GPP_F4, UP_20K),
PAD_NC(GPP_F5, UP_20K), // PLVDD_RST_EC
PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), // M2_P4_SATA_DEVSLP (board error)
PAD_NC(GPP_F7, UP_20K), // BL_PWM_EN_EC
PAD_NC(GPP_F8, UP_20K), // MUX_CTRL_BIOS
PAD_NC(GPP_F9, UP_20K), // PS8461_SW
PAD_CFG_GPI(GPP_F10, UP_20K, DEEP), // BIOS_REC
PAD_CFG_GPI(GPP_F11, UP_20K, DEEP), // PCH_RSVD
PAD_NC(GPP_F12, UP_20K),
PAD_CFG_GPI(GPP_F13, UP_20K, DEEP), // GP39_GFX_CRB_DETECT
PAD_CFG_GPI(GPP_F14, UP_20K, DEEP), // 10k pull to H_SKTOCC_N
PAD_NC(GPP_F15, UP_20K), // USB_OC4# (test point)
PAD_NC(GPP_F16, UP_20K),
PAD_NC(GPP_F17, UP_20K),
PAD_NC(GPP_F18, UP_20K), // USB_OC7# (test point)
PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // NB_ENAVDD
PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), // BLON
PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), // EDP_BRIGHTNESS
PAD_CFG_TERM_GPO(GPP_F22, 1, NONE, DEEP), // DGPU_RST#_PCH
PAD_CFG_TERM_GPO(GPP_F23, 1, NONE, DEEP), // DGPU_PWR_EN
/* ------- GPIO Group GPP_G ------- */
PAD_CFG_GPI(GPP_G0, DN_20K, DEEP), // BOARD_ID1
PAD_CFG_GPI(GPP_G1, DN_20K, DEEP), // BOARD_ID2
PAD_CFG_GPI(GPP_G2, DN_20K, DEEP), // BOARD_ID3
PAD_CFG_GPI(GPP_G3, DN_20K, DEEP), // BOARD_ID4
PAD_CFG_GPI(GPP_G4, UP_20K, DEEP), // GPIO4_NVVDD_EN_R
PAD_NC(GPP_G5, UP_20K),
PAD_NC(GPP_G6, UP_20K),
PAD_NC(GPP_G7, UP_20K),
/* ------- GPIO Group GPP_H ------- */
PAD_CFG_NF(GPP_H0, NONE, DEEP, NF1), // WLAN_CLKREQ#
PAD_CFG_NF(GPP_H1, NONE, DEEP, NF1), // CLK_REQ7_LAN#
PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1), // CLK_REQ8_PEG#
PAD_CFG_NF(GPP_H3, NONE, DEEP, NF1), // CLK_REQ9_CARD#
_PAD_CFG_STRUCT(GPP_H4, 0x40880100, 0x3000), // RTD3_PCIE_WAKE#
PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), // CLK_REQ11_SSD2#
PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), // CLK_REQ12_SSD1#
PAD_NC(GPP_H7, UP_20K),
PAD_NC(GPP_H8, UP_20K),
PAD_NC(GPP_H9, UP_20K),
PAD_NC(GPP_H10, UP_20K),
PAD_NC(GPP_H11, UP_20K),
PAD_NC(GPP_H12, NONE), // eSPI flash sharing mode strap
PAD_CFG_GPI(GPP_H13, NONE, DEEP), // 100k pull up
PAD_NC(GPP_H14, UP_20K),
PAD_CFG_GPI(GPP_H15, NONE, DEEP), // 100k pull up
PAD_CFG_TERM_GPO(GPP_H16, 1, NONE, RSMRST), // TBT_RTD3_PWR_EN_R
PAD_CFG_TERM_GPO(GPP_H17, 1, NONE, PLTRST), // TBT_FORCE_PWR_R
PAD_NC(GPP_H18, UP_20K),
PAD_CFG_TERM_GPO(GPP_H19, 1, NONE, DEEP), // GPIO_CARD_AUX
PAD_CFG_TERM_GPO(GPP_H20, 1, NONE, DEEP), // GPIO_CARD
PAD_CFG_GPI(GPP_H21, UP_20K, DEEP), // 20k pull down, 4.7k pull up
PAD_NC(GPP_H22, UP_20K),
PAD_CFG_GPI(GPP_H23, NONE, DEEP), // DGPU_SELECT#
/* ------- GPIO Group GPP_I ------- */
PAD_NC(GPP_I0, UP_20K),
_PAD_CFG_STRUCT(GPP_I1, 0x46880100, 0x0000), // HDMI_HPD
_PAD_CFG_STRUCT(GPP_I2, 0x46880100, 0x0000), // G_DP_DHPD_E
_PAD_CFG_STRUCT(GPP_I3, 0x46880100, 0x0000), // OUT2_HPD
PAD_CFG_NF(GPP_I4, NONE, DEEP, NF1), // SB_IEDP_HPD
PAD_NC(GPP_I5, UP_20K),
PAD_NC(GPP_I6, UP_20K),
PAD_NC(GPP_I7, UP_20K),
PAD_NC(GPP_I8, UP_20K),
PAD_NC(GPP_I9, UP_20K),
_PAD_CFG_STRUCT(GPP_I10, 0x82880100, 0x0000), // TBCIO_PLUG_EVENT
PAD_CFG_GPI(GPP_I11, UP_20K, DEEP), // 10k pull to H_SKTOCC_N, 10k pull up
PAD_CFG_GPI(GPP_I12, DN_20K, DEEP), // D02C_BOARD_ID (10k pull up)
PAD_NC(GPP_I13, UP_20K),
PAD_NC(GPP_I14, UP_20K),
/* ------- GPIO Group GPP_J ------- */
PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING
PAD_CFG_NF(GPP_J1, NONE, DEEP, NF1), // CPU_VCCIO_PWR_GATE
PAD_CFG_GPI(GPP_J2, UP_20K, DEEP), // 100k pull down
PAD_NC(GPP_J3, UP_20K),
PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1), // M.2_CNV_BRI_DT_BT_UART0_RTS
PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1), // M.2_CNV_BRI_RSP
PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1), // M.2_CNV_RGI_DT_BT_UART0_TX
PAD_CFG_NF(GPP_J7, UP_20K, DEEP, NF1), // M.2_CNV_RGI_RSP
PAD_NC(GPP_J8, UP_20K),
PAD_CFG_GPI(GPP_J9, UP_20K, DEEP), // 100k pull up, 100k pull down
PAD_CFG_GPI(GPP_J10, UP_20K, DEEP), // 100k pull down
PAD_CFG_GPI(GPP_J11, UP_20K, DEEP), // 75k pull down
/* ------- GPIO Group GPP_K ------- */
PAD_NC(GPP_K0, UP_20K),
PAD_NC(GPP_K1, UP_20K),
PAD_NC(GPP_K2, UP_20K),
_PAD_CFG_STRUCT(GPP_K3, 0x80880100, 0x3000), // SCI#
PAD_NC(GPP_K4, UP_20K),
PAD_NC(GPP_K5, UP_20K),
_PAD_CFG_STRUCT(GPP_K6, 0x40880100, 0x0000), // SWI#
PAD_NC(GPP_K7, UP_20K),
PAD_CFG_TERM_GPO(GPP_K8, 1, NONE, RSMRST), // SATA_M2_PWR_EN1
PAD_CFG_TERM_GPO(GPP_K9, 1, NONE, RSMRST), // SATA_M2_PWR_EN2
PAD_CFG_TERM_GPO(GPP_K10, 1, NONE, DEEP), // LANRTD3_WAKE#
PAD_CFG_TERM_GPO(GPP_K11, 1, NONE, RSMRST), // GPIO_LANRTD3
PAD_NC(GPP_K12, UP_20K),
PAD_NC(GPP_K13, UP_20K),
PAD_CFG_GPI(GPP_K14, UP_20K, DEEP), // GPP_K_14_GSXDIN (test point)
PAD_NC(GPP_K15, UP_20K),
PAD_NC(GPP_K16, UP_20K),
PAD_NC(GPP_K17, UP_20K),
PAD_NC(GPP_K18, UP_20K),
PAD_CFG_GPI(GPP_K19, UP_20K, DEEP), // SMI#
PAD_NC(GPP_K20, NONE),
PAD_CFG_GPI(GPP_K21, NONE, DEEP), // GC6_FB_EN_PCH
PAD_CFG_TERM_GPO(GPP_K22, 0, NONE, DEEP), // OVRM
PAD_CFG_GPI(GPP_K23, NONE, DEEP), // DGPU_PWRGD_R
};
#endif
#endif

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src/mainboard/system76/oryp7/hda_verb.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <device/azalia_device.h>
const u32 cim_verb_data[] = {
/* Realtek, ALC1220 */
0x10ec1220, /* Vendor ID */
0x155865e5, /* Subsystem ID */
12, /* Number of entries */
AZALIA_SUBVENDOR(0, 0x155865e5),
AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
AZALIA_PIN_CFG(0, 0x14, 0x0421101f),
AZALIA_PIN_CFG(0, 0x15, 0x40000000),
AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
AZALIA_PIN_CFG(0, 0x17, 0x411111f0),
AZALIA_PIN_CFG(0, 0x18, 0x04a11040),
AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
AZALIA_PIN_CFG(0, 0x1b, 0x90170110),
AZALIA_PIN_CFG(0, 0x1d, 0x40b7952d),
AZALIA_PIN_CFG(0, 0x1e, 0x04451150),
};
const u32 pc_beep_verbs[] = {
// Enable DMIC microphone on ALC1220
0x02050036,
0x02042a6a,
};
AZALIA_ARRAY_SIZES;

13
src/mainboard/system76/oryp7/ramstage.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <device/device.h>
#include "gpio.h"
static void mainboard_init(void *chip_info)
{
gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
}
struct chip_operations mainboard_ops = {
.init = mainboard_init,
};

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src/mainboard/system76/oryp7/romstage.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <soc/cnl_memcfg_init.h>
#include <soc/romstage.h>
static const struct cnl_mb_cfg memcfg = {
.spd[0] = {
.read_type = READ_SMBUS,
.spd_spec = {.spd_smbus_address = 0xa0},
},
.spd[2] = {
.read_type = READ_SMBUS,
.spd_spec = {.spd_smbus_address = 0xa4},
},
.rcomp_resistor = { 121, 75, 100 },
.rcomp_targets = { 50, 25, 20, 20, 26 },
.dq_pins_interleaved = 1,
.vref_ca_config = 2,
};
void mainboard_memory_init_params(FSPM_UPD *memupd)
{
// Allow memory clocks higher than 2933 MHz
memupd->FspmConfig.SaOcSupport = 1;
// Set primary display to internal graphics
memupd->FspmConfig.PrimaryDisplay = 0;
cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg);
}

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src/mainboard/system76/oryp7/tas5825m.c Normal file
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