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mainboard/google/rush_ryu: remove rush_ryu mainboard

Browse Source 
The rush_ryu board was a development platform that never made it into
a product. Remove it as it's not available to anyone.

BUG=chrome-os-partner:55932

Change-Id: Ia3836ff8cade3009730543177a66736ae197572b
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16107
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
Aaron Durbin
2016-08-06 13:41:51 -05:00
parent e67cd9ee90
commit 0c634159a3
29 changed files with 0 additions and 4003 deletions
Download Patch File Download Diff File Expand all files Collapse all files

99
src/mainboard/google/rush_ryu/Kconfig
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@@ -1,99 +0,0 @@
##
## This file is part of the coreboot project.
##
## Copyright 2014 Google Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
if BOARD_GOOGLE_RUSH_RYU
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select BOARD_ID_AUTO
select EC_GOOGLE_CHROMEEC
select EC_GOOGLE_CHROMEEC_I2C
select EC_GOOGLE_CHROMEEC_I2C_PROTO3
select MAINBOARD_HAS_NATIVE_VGA_INIT
select MAINBOARD_DO_NATIVE_VGA_INIT
select SPI_FLASH
select SOC_NVIDIA_TEGRA132
select MAINBOARD_DO_DSI_INIT
select MAINBOARD_HAS_CHROMEOS
select BOARD_ROMSIZE_KB_8192
config CHROMEOS
select EC_SOFTWARE_SYNC
select VBOOT_VBNV_EC
select VIRTUAL_DEV_SWITCH
config MAINBOARD_DIR
string
default google/rush_ryu
config MAINBOARD_PART_NUMBER
string
default "Rush Ryu"
choice
prompt "BCT boot media"
default RUSH_RYU_BCT_CFG_SPI
help
Which boot media to configure the BCT for.
config RUSH_RYU_BCT_CFG_SPI
bool "SPI"
help
Configure the BCT for booting from SPI.
config RUSH_RYU_BCT_CFG_EMMC
bool "eMMC"
help
Configure the BCT for booting from eMMC.
endchoice
config BOOT_MEDIA_SPI_BUS
int "SPI bus with boot media ROM"
range 1 6
depends on RUSH_RYU_BCT_CFG_SPI
default 4
help
Which SPI bus the boot media is connected to.
config BOOT_MEDIA_SPI_CHIP_SELECT
int "Chip select for SPI boot media"
range 0 3
depends on RUSH_RYU_BCT_CFG_SPI
default 0
help
Which chip select to use for boot media.
config DRIVER_TPM_I2C_BUS
hex
default 0x2
config DRIVER_TPM_I2C_ADDR
hex
default 0x20
config EC_GOOGLE_CHROMEEC_I2C_BUS
hex
default 1
config EC_GOOGLE_CHROMEEC_BOARDNAME
string
default "ryu"
config GBB_HWID
string
depends on CHROMEOS
default "RYU TEST 9382"
endif # BOARD_GOOGLE_RUSH_RYU

2
src/mainboard/google/rush_ryu/Kconfig.name
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@@ -1,2 +0,0 @@
config BOARD_GOOGLE_RUSH_RYU
bool "Rush Ryu"

49
src/mainboard/google/rush_ryu/Makefile.inc
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@@ -1,49 +0,0 @@
##
## This file is part of the coreboot project.
##
## Copyright 2014 Google Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
# Add a handler for BCT config files
$(call add-special-class,bct-cfg)
bct-cfg-handler= $(eval $(obj)/generated/bct.cfg: $(1)$(2))
$(obj)/generated/bct.cfg:
@printf " CAT $(subst $(obj)/,,$(@))\n"
cat $^ > $@
subdirs-y += bct
bootblock-y += bootblock.c
bootblock-y += pmic.c
bootblock-y += reset.c
verstage-y += verstage.c
verstage-y += chromeos.c
verstage-y += reset.c
romstage-y += chromeos.c
romstage-y += pmic.c
romstage-y += reset.c
romstage-y += romstage.c
romstage-y += sdram_configs.c
ramstage-y += boardid.c
ramstage-y += mainboard.c
ramstage-y += reset.c
ramstage-y += chromeos.c
ramstage-y += pmic.c
bootblock-y += memlayout.ld
romstage-y += memlayout.ld
ramstage-y += memlayout.ld
verstage-y += memlayout.ld

25
src/mainboard/google/rush_ryu/bct/Makefile.inc
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@@ -1,25 +0,0 @@
##
## This file is part of the coreboot project.
##
## Copyright 2014 Google Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
bct-cfg-$(CONFIG_RUSH_RYU_BCT_CFG_EMMC) += emmc.cfg
bct-cfg-$(CONFIG_RUSH_RYU_BCT_CFG_SPI) += spi.cfg
bct-cfg-y += odmdata.cfg
bct-cfg-y += jtag.cfg
#NOTE: When full LPDDR3 SDRAM config is done in bootblock, remove this
bct-cfg-$(CONFIG_BOOTROM_SDRAM_INIT) += sdram-4GB-924.cfg
# Note when SDRAM config (sdram-*.cfg) files are changed, we have to regenerate
# the include files (sdram-*.inc) by running "./cfg2inc.sh sdram-*.cfg".
# TODO(hungte) Change cfg2inc.sh to NVIDIA's official tool in cbootimage.

30
src/mainboard/google/rush_ryu/bct/cfg2inc.sh
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@@ -1,30 +0,0 @@
#!/bin/sh
#
# This file is part of the coreboot project.
#
# Copyright 2014 Google Inc.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; version 2 of the License.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
bct_cfg2inc() {
local in_file="$1"
local out_file="$2"
echo "{ /* generated from ${in_file}; do not edit. */" >"${out_file}"
# Note currently we can only handle DDR3 type memory, even in C
# implementation.
sed "/^#.*$/d; s/^SDRAM.0./ /; s/\r$//; s/;$/,/;" \
"${in_file}" >> "${out_file}"
echo "}," >>"${out_file}"
}
for file in $@; do
echo "Generating $file => ${file%cfg}inc..."
bct_cfg2inc "${file}" "${file%cfg}inc"
done

13
src/mainboard/google/rush_ryu/bct/emmc.cfg
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@@ -1,13 +0,0 @@
# Copyright (c) 2013 The Chromium OS Authors. All rights reserved.
# Distributed under the terms of the GNU General Public License v2
Version = 0x00130001;
BlockSize = 0x00004000;
PageSize = 0x00000200;
PartitionSize = 0x01000000;
DevType[0] = NvBootDevType_Sdmmc;
DeviceParam[0].SdmmcParams.ClockDivider = 0x00000009;
DeviceParam[0].SdmmcParams.DataWidth = NvBootSdmmcDataWidth_8Bit;
DeviceParam[0].SdmmcParams.MaxPowerClassSupported = 0x00000000;
DeviceParam[0].SdmmcParams.MultiPageSupport = 0x00000000;

16
src/mainboard/google/rush_ryu/bct/jtag.cfg
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@@ -1,16 +0,0 @@
#
# Set JtagCtrl to 1 to reenable Jtag
#
JtagCtrl = 0;
#
# Fill in chip unique id
#
# ChipUid can be found by running tegrarcm in tegra recovery mode
# (also hooking up A-A USB cable) and looking for console output
# on line starting with "Chip UID:"
#
# Command example:
# $ sudo tegrarcm --bct=/build/nyan/firmware/bct/board.bct --bootloader=/build/nyan/firmware/u-boot.bin --loadaddr=0x80108000
# Where board.bct and u-boot.bin do not have to be prebuilt.
#
ChipUid = 0x00000000000000000000000000000000;

1
src/mainboard/google/rush_ryu/bct/odmdata.cfg
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@@ -1 +0,0 @@
OdmData = 0x80080000;

1387
src/mainboard/google/rush_ryu/bct/sdram-4GB-924.cfg
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File diff suppressed because it is too large Load Diff

311
src/mainboard/google/rush_ryu/bct/sdram-hynix-4GB-924.inc
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@@ -1,311 +0,0 @@
{ /* generated from sdram-hynix-4GB-924.cfg; do not edit. This is Hynix LPDDR3 */
.MemoryType = NvBootMemoryType_LpDdr2,
.PllMInputDivider = 0x00000001,
.PllMFeedbackDivider = 0x0000004d,
.PllMStableTime = 0x0000012c,
.PllMSetupControl = 0x00000000,
.PllMSelectDiv2 = 0x00000000,
.PllMPDLshiftPh45 = 0x00000001,
.PllMPDLshiftPh90 = 0x00000001,
.PllMPDLshiftPh135 = 0x00000001,
.PllMKCP = 0x00000000,
.PllMKVCO = 0x00000000,
.EmcBctSpare0 = 0x00000000,
.EmcBctSpare1 = 0x00000000,
.EmcBctSpare2 = 0x00000000,
.EmcBctSpare3 = 0x00000000,
.EmcBctSpare4 = 0x00000000,
.EmcBctSpare5 = 0x00000000,
.EmcBctSpare6 = 0x00000000,
.EmcBctSpare7 = 0x00000000,
.EmcBctSpare8 = 0x00000000,
.EmcBctSpare9 = 0x00000000,
.EmcBctSpare10 = 0x00000000,
.EmcBctSpare11 = 0x00000000,
.EmcClockSource = 0x80000000,
.EmcAutoCalInterval = 0x001fffff,
.EmcAutoCalConfig = 0xa1430000,
.EmcAutoCalConfig2 = 0x00000000,
.EmcAutoCalConfig3 = 0x00000000,
.EmcAutoCalWait = 0x00000190,
.EmcAdrCfg = 0x00000001,
.EmcPinProgramWait = 0x00000000,
.EmcPinExtraWait = 0x00000000,
.EmcTimingControlWait = 0x00000000,
.EmcRc = 0x00000037,
.EmcRfc = 0x00000078,
.EmcRfcSlr = 0x00000000,
.EmcRas = 0x00000026,
.EmcRp = 0x00000010,
.EmcR2r = 0x00000000,
.EmcW2w = 0x00000000,
.EmcR2w = 0x00000010,
.EmcW2r = 0x00000010,
.EmcR2p = 0x00000006,
.EmcW2p = 0x00000017,
.EmcRdRcd = 0x00000010,
.EmcWrRcd = 0x00000010,
.EmcRrd = 0x00000009,
.EmcRext = 0x00000005,
.EmcWext = 0x00000000,
.EmcWdv = 0x00000007,
.EmcWdvMask = 0x00000007,
.EmcQUse = 0x00000011,
.EmcQuseWidth = 0x00000004,
.EmcIbdly = 0x00000000,
.EmcEInput = 0x00000006,
.EmcEInputDuration = 0x00000011,
.EmcPutermExtra = 0x000e0000,
.EmcPutermWidth = 0x00000006,
.EmcPutermAdj = 0x00000000,
.EmcCdbCntl1 = 0x00000000,
.EmcCdbCntl2 = 0x00000000,
.EmcCdbCntl3 = 0x00000000,
.EmcQRst = 0x00000005,
.EmcQSafe = 0x00000018,
.EmcRdv = 0x00000020,
.EmcRdvMask = 0x00000022,
.EmcQpop = 0x00000017,
.EmcCtt = 0x00000000,
.EmcCttDuration = 0x00000006,
.EmcRefresh = 0x00000dd4,
.EmcBurstRefreshNum = 0x00000000,
.EmcPreRefreshReqCnt = 0x00000375,
.EmcPdEx2Wr = 0x00000006,
.EmcPdEx2Rd = 0x00000006,
.EmcPChg2Pden = 0x00000010,
.EmcAct2Pden = 0x00000000,
.EmcAr2Pden = 0x00000001,
.EmcRw2Pden = 0x0000001b,
.EmcTxsr = 0x00000082,
.EmcTxsrDll = 0x00000082,
.EmcTcke = 0x00000007,
.EmcTckesr = 0x0000000e,
.EmcTpd = 0x00000007,
.EmcTfaw = 0x0000002d,
.EmcTrpab = 0x00000014,
.EmcTClkStable = 0x00000003,
.EmcTClkStop = 0x00000003,
.EmcTRefBw = 0x00000f04,
.EmcFbioCfg5 = 0x1363a896,
.EmcFbioCfg6 = 0x00000000,
.EmcFbioSpare = 0x00000000,
.EmcCfgRsv = 0xff00ff00,
.EmcMrs = 0x00000000,
.EmcEmrs = 0x00000000,
.EmcEmrs2 = 0x00000000,
.EmcEmrs3 = 0x00000000,
.EmcMrw1 = 0x00010083,
.EmcMrw2 = 0x0002001c,
.EmcMrw3 = 0x00030001,
.EmcMrw4 = 0x800b0000,
.EmcMrwExtra = 0x00010083,
.EmcWarmBootMrwExtra = 0x0002001c,
.EmcWarmBootExtraModeRegWriteEnable = 0x00000000,
.EmcExtraModeRegWriteEnable = 0x00000000,
.EmcMrwResetCommand = 0x003f00fc,
.EmcMrwResetNInitWait = 0x0000000a,
.EmcMrsWaitCnt = 0x039c0019,
.EmcMrsWaitCnt2 = 0x039c0019,
.EmcCfg = 0xd3300000,
.EmcCfg2 = 0x0000089f,
.EmcCfgPipe = 0x00004080,
.EmcDbg = 0x01000c00,
.EmcCmdQ = 0x10004408,
.EmcMc2EmcQ = 0x06000404,
.EmcDynSelfRefControl = 0x80001c77,
.AhbArbitrationXbarCtrlMemInitDone = 0x00000001,
.EmcCfgDigDll = 0xe00400b9,
.EmcCfgDigDllPeriod = 0x00008000,
.EmcDevSelect = 0x00000000,
.EmcSelDpdCtrl = 0x0004001c,
.EmcDllXformDqs0 = 0x0000000a,
.EmcDllXformDqs1 = 0x0000000a,
.EmcDllXformDqs2 = 0x0000000c,
.EmcDllXformDqs3 = 0x0000000a,
.EmcDllXformDqs4 = 0x00000008,
.EmcDllXformDqs5 = 0x00004008,
.EmcDllXformDqs6 = 0x0000000a,
.EmcDllXformDqs7 = 0x00000008,
.EmcDllXformDqs8 = 0x0000000a,
.EmcDllXformDqs9 = 0x0000000a,
.EmcDllXformDqs10 = 0x0000000a,
.EmcDllXformDqs11 = 0x0000000a,
.EmcDllXformDqs12 = 0x0000000a,
.EmcDllXformDqs13 = 0x0000000a,
.EmcDllXformDqs14 = 0x0000000a,
.EmcDllXformDqs15 = 0x0000000a,
.EmcDllXformQUse0 = 0x00000000,
.EmcDllXformQUse1 = 0x00000000,
.EmcDllXformQUse2 = 0x00000000,
.EmcDllXformQUse3 = 0x00000000,
.EmcDllXformQUse4 = 0x00000000,
.EmcDllXformQUse5 = 0x00000000,
.EmcDllXformQUse6 = 0x00000000,
.EmcDllXformQUse7 = 0x00000000,
.EmcDllXformAddr0 = 0x00024002,
.EmcDllXformAddr1 = 0x00024002,
.EmcDllXformAddr2 = 0x00000008,
.EmcDllXformAddr3 = 0x00024002,
.EmcDllXformAddr4 = 0x00024002,
.EmcDllXformAddr5 = 0x00000008,
.EmcDllXformQUse8 = 0x00000000,
.EmcDllXformQUse9 = 0x00000000,
.EmcDllXformQUse10 = 0x00000000,
.EmcDllXformQUse11 = 0x00000000,
.EmcDllXformQUse12 = 0x00000000,
.EmcDllXformQUse13 = 0x00000000,
.EmcDllXformQUse14 = 0x00000000,
.EmcDllXformQUse15 = 0x00000000,
.EmcDliTrimTxDqs0 = 0x00000008,
.EmcDliTrimTxDqs1 = 0x00000008,
.EmcDliTrimTxDqs2 = 0x00000008,
.EmcDliTrimTxDqs3 = 0x00000008,
.EmcDliTrimTxDqs4 = 0x00000008,
.EmcDliTrimTxDqs5 = 0x00000008,
.EmcDliTrimTxDqs6 = 0x00000008,
.EmcDliTrimTxDqs7 = 0x00000008,
.EmcDliTrimTxDqs8 = 0x00000008,
.EmcDliTrimTxDqs9 = 0x00000008,
.EmcDliTrimTxDqs10 = 0x00000008,
.EmcDliTrimTxDqs11 = 0x00000008,
.EmcDliTrimTxDqs12 = 0x00000008,
.EmcDliTrimTxDqs13 = 0x00000008,
.EmcDliTrimTxDqs14 = 0x00000008,
.EmcDliTrimTxDqs15 = 0x00000008,
.EmcDllXformDq0 = 0x0000000e,
.EmcDllXformDq1 = 0x0000000e,
.EmcDllXformDq2 = 0x0000000e,
.EmcDllXformDq3 = 0x0000000e,
.EmcDllXformDq4 = 0x0000000e,
.EmcDllXformDq5 = 0x0000000e,
.EmcDllXformDq6 = 0x0000000e,
.EmcDllXformDq7 = 0x0000000e,
.WarmBootWait = 0x00000001,
.EmcCttTermCtrl = 0x00000802,
.EmcOdtWrite = 0x00000000,
.EmcOdtRead = 0x00000000,
.EmcZcalInterval = 0x00064000,
.EmcZcalWaitCnt = 0x00000058,
.EmcZcalMrwCmd = 0x000a0056,
.EmcMrsResetDll = 0x00000000,
.EmcZcalInitDev0 = 0x840a00ff,
.EmcZcalInitDev1 = 0x440a00ff,
.EmcZcalInitWait = 0x00000001,
.EmcZcalWarmColdBootEnables = 0x00000003,
.EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab,
.EmcZqCalDdr3WarmBoot = 0x00000000,
.EmcZcalWarmBootWait = 0x00000001,
.EmcMrsWarmBootEnable = 0x00000001,
.EmcMrsResetDllWait = 0x00000000,
.EmcMrsExtra = 0x00000000,
.EmcWarmBootMrsExtra = 0x00000000,
.EmcEmrsDdr2DllEnable = 0x00000000,
.EmcMrsDdr2DllReset = 0x00000000,
.EmcEmrsDdr2OcdCalib = 0x00000000,
.EmcDdr2Wait = 0x00000000,
.EmcClkenOverride = 0x00000000,
.McDisExtraSnapLevels = 0x00000000,
.EmcExtraRefreshNum = 0x00000002,
.EmcClkenOverrideAllWarmBoot = 0x00000000,
.McClkenOverrideAllWarmBoot = 0x00000000,
.EmcCfgDigDllPeriodWarmBoot = 0x00000003,
.PmcVddpSel = 0x00000001,
.PmcVddpSelWait = 0x00000002,
.PmcDdrPwr = 0x00000003,
.PmcDdrCfg = 0x00001000,
.PmcIoDpd3Req = 0x4ffefef7,
.PmcIoDpd3ReqWait = 0x00000000,
.PmcRegShort = 0x0000330f,
.PmcNoIoPower = 0x00000000,
.PmcPorDpdCtrlWait = 0x00000001,
.EmcXm2CmdPadCtrl = 0x00000220,
.EmcXm2CmdPadCtrl2 = 0x770c0000,
.EmcXm2CmdPadCtrl3 = 0x050c0000,
.EmcXm2CmdPadCtrl4 = 0x00000000,
.EmcXm2CmdPadCtrl5 = 0x00100100,
.EmcXm2DqsPadCtrl = 0x770c1414,
.EmcXm2DqsPadCtrl2 = 0x0120103d,
.EmcXm2DqsPadCtrl3 = 0x55555520,
.EmcXm2DqsPadCtrl4 = 0x00492492,
.EmcXm2DqsPadCtrl5 = 0x00492492,
.EmcXm2DqsPadCtrl6 = 0x55555500,
.EmcXm2DqPadCtrl = 0x770c2990,
.EmcXm2DqPadCtrl2 = 0x00000000,
.EmcXm2DqPadCtrl3 = 0x00000000,
.EmcXm2ClkPadCtrl = 0x77ffc004,
.EmcXm2ClkPadCtrl2 = 0x00000000,
.EmcXm2CompPadCtrl = 0x81f1f008,
.EmcXm2VttGenPadCtrl = 0x07070000,
.EmcXm2VttGenPadCtrl2 = 0x00000000,
.EmcXm2VttGenPadCtrl3 = 0x015ddddd,
.EmcAcpdControl = 0x00000000,
.EmcSwizzleRank0ByteCfg = 0x00001032,
.EmcSwizzleRank0Byte0 = 0x53067142,
.EmcSwizzleRank0Byte1 = 0x73025146,
.EmcSwizzleRank0Byte2 = 0x20136475,
.EmcSwizzleRank0Byte3 = 0x46273150,
.EmcSwizzleRank1ByteCfg = 0x00003210,
.EmcSwizzleRank1Byte0 = 0x73451026,
.EmcSwizzleRank1Byte1 = 0x73025146,
.EmcSwizzleRank1Byte2 = 0x20641735,
.EmcSwizzleRank1Byte3 = 0x42136075,
.EmcDsrVttgenDrv = 0x0000003f,
.EmcTxdsrvttgen = 0x00000000,
.EmcBgbiasCtl0 = 0x00000000,
.McEmemAdrCfg = 0x00000001,
.McEmemAdrCfgDev0 = 0x00080304,
.McEmemAdrCfgDev1 = 0x00080304,
.McEmemAdrCfgBankMask0 = 0x00001248,
.McEmemAdrCfgBankMask1 = 0x00002490,
.McEmemAdrCfgBankMask2 = 0x00000920,
.McEmemAdrCfgBankSwizzle3 = 0x00000001,
.McEmemCfg = 0x00001000,
.McEmemArbCfg = 0x0e00000d,
.McEmemArbOutstandingReq = 0x80000040,
.McEmemArbTimingRcd = 0x00000007,
.McEmemArbTimingRp = 0x00000008,
.McEmemArbTimingRc = 0x0000001b,
.McEmemArbTimingRas = 0x00000012,
.McEmemArbTimingFaw = 0x00000017,
.McEmemArbTimingRrd = 0x00000004,
.McEmemArbTimingRap2Pre = 0x00000004,
.McEmemArbTimingWap2Pre = 0x0000000e,
.McEmemArbTimingR2R = 0x00000004,
.McEmemArbTimingW2W = 0x00000001,
.McEmemArbTimingR2W = 0x00000009,
.McEmemArbTimingW2R = 0x00000009,
.McEmemArbDaTurns = 0x09090104,
.McEmemArbDaCovers = 0x001e141b,
.McEmemArbMisc0 = 0x71ae2a1c,
.McEmemArbMisc1 = 0x70000f02,
.McEmemArbRing1Throttle = 0x001f0000,
.McEmemArbOverride = 0x10000000,
.McEmemArbOverride1 = 0x00000000,
.McEmemArbRsv = 0xff00ff00,
.McClkenOverride = 0x00000000,
.McStatControl = 0x00000000,
.McDisplaySnapRing = 0x00000003,
.McVideoProtectBom = 0xfff00000,
.McVideoProtectBomAdrHi = 0x00000000,
.McVideoProtectSizeMb = 0x00000000,
.McVideoProtectVprOverride = 0xe4bac743,
.McVideoProtectVprOverride1 = 0x00000013,
.McVideoProtectGpuOverride0 = 0x00000000,
.McVideoProtectGpuOverride1 = 0x00000000,
.McSecCarveoutBom = 0xfff00000,
.McSecCarveoutAdrHi = 0x00000000,
.McSecCarveoutSizeMb = 0x00000000,
.McVideoProtectWriteAccess = 0x00000000,
.McSecCarveoutProtectWriteAccess = 0x00000000,
.EmcCaTrainingEnable = 0x00000001,
.EmcCaTrainingTimingCntl1 = 0x09257359,
.EmcCaTrainingTimingCntl2 = 0x00000017,
.SwizzleRankByteEncode = 0x00000008,
.BootRomPatchControl = 0x00000000,
.BootRomPatchData = 0x00000000,
.McMtsCarveoutBom = 0x78000000,
.McMtsCarveoutAdrHi = 0x00000001,
.McMtsCarveoutSizeMb = 0x00000080,
.McMtsCarveoutRegCtrl = 0x00000001,
},

311
src/mainboard/google/rush_ryu/bct/sdram-micron-4GB-528.inc
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@@ -1,311 +0,0 @@
{ /* generated from sdram-micron-4GB-528.cfg; do not edit. */
.MemoryType = NvBootMemoryType_LpDdr2,
.PllMInputDivider = 0x00000001,
.PllMFeedbackDivider = 0x0000002c,
.PllMStableTime = 0x0000012c,
.PllMSetupControl = 0x00000000,
.PllMSelectDiv2 = 0x00000000,
.PllMPDLshiftPh45 = 0x00000001,
.PllMPDLshiftPh90 = 0x00000001,
.PllMPDLshiftPh135 = 0x00000001,
.PllMKCP = 0x00000000,
.PllMKVCO = 0x00000000,
.EmcBctSpare0 = 0x00000000,
.EmcBctSpare1 = 0x00000000,
.EmcBctSpare2 = 0x00000000,
.EmcBctSpare3 = 0x00000000,
.EmcBctSpare4 = 0x00000000,
.EmcBctSpare5 = 0x00000000,
.EmcBctSpare6 = 0x00000000,
.EmcBctSpare7 = 0x00000000,
.EmcBctSpare8 = 0x00000000,
.EmcBctSpare9 = 0x00000000,
.EmcBctSpare10 = 0x00000000,
.EmcBctSpare11 = 0x00000000,
.EmcClockSource = 0x80000000,
.EmcAutoCalInterval = 0x001fffff,
.EmcAutoCalConfig = 0xa1430000,
.EmcAutoCalConfig2 = 0x00000000,
.EmcAutoCalConfig3 = 0x00000000,
.EmcAutoCalWait = 0x00000190,
.EmcAdrCfg = 0x00000001,
.EmcPinProgramWait = 0x00000000,
.EmcPinExtraWait = 0x00000000,
.EmcTimingControlWait = 0x00000000,
.EmcRc = 0x0000001f,
.EmcRfc = 0x00000044,
.EmcRfcSlr = 0x00000000,
.EmcRas = 0x00000016,
.EmcRp = 0x00000009,
.EmcR2r = 0x00000000,
.EmcW2w = 0x00000000,
.EmcR2w = 0x0000000a,
.EmcW2r = 0x00000009,
.EmcR2p = 0x00000003,
.EmcW2p = 0x0000000d,
.EmcRdRcd = 0x00000009,
.EmcWrRcd = 0x00000009,
.EmcRrd = 0x00000005,
.EmcRext = 0x00000004,
.EmcWext = 0x00000000,
.EmcWdv = 0x00000002,
.EmcWdvMask = 0x00000002,
.EmcQUse = 0x00000008,
.EmcQuseWidth = 0x00000003,
.EmcIbdly = 0x00000000,
.EmcEInput = 0x00000003,
.EmcEInputDuration = 0x0000000a,
.EmcPutermExtra = 0x00050000,
.EmcPutermWidth = 0x00000004,
.EmcPutermAdj = 0x00000000,
.EmcCdbCntl1 = 0x00000000,
.EmcCdbCntl2 = 0x00000000,
.EmcCdbCntl3 = 0x00000000,
.EmcQRst = 0x00000002,
.EmcQSafe = 0x00000011,
.EmcRdv = 0x00000015,
.EmcRdvMask = 0x00000017,
.EmcQpop = 0x0000000d,
.EmcCtt = 0x00000000,
.EmcCttDuration = 0x00000004,
.EmcRefresh = 0x000007cd,
.EmcBurstRefreshNum = 0x00000000,
.EmcPreRefreshReqCnt = 0x000001f3,
.EmcPdEx2Wr = 0x00000003,
.EmcPdEx2Rd = 0x00000003,
.EmcPChg2Pden = 0x00000009,
.EmcAct2Pden = 0x00000000,
.EmcAr2Pden = 0x00000001,
.EmcRw2Pden = 0x00000011,
.EmcTxsr = 0x0000004a,
.EmcTxsrDll = 0x0000004a,
.EmcTcke = 0x00000004,
.EmcTckesr = 0x00000008,
.EmcTpd = 0x00000004,
.EmcTfaw = 0x00000019,
.EmcTrpab = 0x0000000c,
.EmcTClkStable = 0x00000003,
.EmcTClkStop = 0x00000003,
.EmcTRefBw = 0x00000895,
.EmcFbioCfg5 = 0x1363a096,
.EmcFbioCfg6 = 0x00000000,
.EmcFbioSpare = 0x00000000,
.EmcCfgRsv = 0xff00ff00,
.EmcMrs = 0x00000000,
.EmcEmrs = 0x00000000,
.EmcEmrs2 = 0x00000000,
.EmcEmrs3 = 0x00000000,
.EmcMrw1 = 0x000100c3,
.EmcMrw2 = 0x00020006,
.EmcMrw3 = 0x00030001,
.EmcMrw4 = 0x800b0000,
.EmcMrwExtra = 0x000100c3,
.EmcWarmBootMrwExtra = 0x00020006,
.EmcWarmBootExtraModeRegWriteEnable = 0x00000000,
.EmcExtraModeRegWriteEnable = 0x00000000,
.EmcMrwResetCommand = 0x003f00fc,
.EmcMrwResetNInitWait = 0x0000000a,
.EmcMrsWaitCnt = 0x02100013,
.EmcMrsWaitCnt2 = 0x02100013,
.EmcCfg = 0xf3300000,
.EmcCfg2 = 0x0000089f,
.EmcCfgPipe = 0x000042a0,
.EmcDbg = 0x01000c00,
.EmcCmdQ = 0x10004408,
.EmcMc2EmcQ = 0x06000404,
.EmcDynSelfRefControl = 0x800010b3,
.AhbArbitrationXbarCtrlMemInitDone = 0x00000001,
.EmcCfgDigDll = 0xe01200b9,
.EmcCfgDigDllPeriod = 0x00008000,
.EmcDevSelect = 0x00000000,
.EmcSelDpdCtrl = 0x0004001c,
.EmcDllXformDqs0 = 0x007f400a,
.EmcDllXformDqs1 = 0x007f400a,
.EmcDllXformDqs2 = 0x007f400a,
.EmcDllXformDqs3 = 0x007f400a,
.EmcDllXformDqs4 = 0x007f400a,
.EmcDllXformDqs5 = 0x007f400a,
.EmcDllXformDqs6 = 0x007f400a,
.EmcDllXformDqs7 = 0x007f400a,
.EmcDllXformDqs8 = 0x007f400a,
.EmcDllXformDqs9 = 0x007f400a,
.EmcDllXformDqs10 = 0x007f400a,
.EmcDllXformDqs11 = 0x007f400a,
.EmcDllXformDqs12 = 0x007f400a,
.EmcDllXformDqs13 = 0x007f400a,
.EmcDllXformDqs14 = 0x007f400a,
.EmcDllXformDqs15 = 0x007f400a,
.EmcDllXformQUse0 = 0x00000000,
.EmcDllXformQUse1 = 0x00000000,
.EmcDllXformQUse2 = 0x00000000,
.EmcDllXformQUse3 = 0x00000000,
.EmcDllXformQUse4 = 0x00000000,
.EmcDllXformQUse5 = 0x00000000,
.EmcDllXformQUse6 = 0x00000000,
.EmcDllXformQUse7 = 0x00000000,
.EmcDllXformAddr0 = 0x00024000,
.EmcDllXformAddr1 = 0x00024000,
.EmcDllXformAddr2 = 0x00000006,
.EmcDllXformAddr3 = 0x00024000,
.EmcDllXformAddr4 = 0x00024000,
.EmcDllXformAddr5 = 0x00000006,
.EmcDllXformQUse8 = 0x00000000,
.EmcDllXformQUse9 = 0x00000000,
.EmcDllXformQUse10 = 0x00000000,
.EmcDllXformQUse11 = 0x00000000,
.EmcDllXformQUse12 = 0x00000000,
.EmcDllXformQUse13 = 0x00000000,
.EmcDllXformQUse14 = 0x00000000,
.EmcDllXformQUse15 = 0x00000000,
.EmcDliTrimTxDqs0 = 0x0000000b,
.EmcDliTrimTxDqs1 = 0x0000000b,
.EmcDliTrimTxDqs2 = 0x00000008,
.EmcDliTrimTxDqs3 = 0x0000000b,
.EmcDliTrimTxDqs4 = 0x0000000b,
.EmcDliTrimTxDqs5 = 0x00000008,
.EmcDliTrimTxDqs6 = 0x0000000b,
.EmcDliTrimTxDqs7 = 0x0000000b,
.EmcDliTrimTxDqs8 = 0x0000000b,
.EmcDliTrimTxDqs9 = 0x0000000b,
.EmcDliTrimTxDqs10 = 0x00000008,
.EmcDliTrimTxDqs11 = 0x0000000b,
.EmcDliTrimTxDqs12 = 0x0000000b,
.EmcDliTrimTxDqs13 = 0x00000008,
.EmcDliTrimTxDqs14 = 0x0000000b,
.EmcDliTrimTxDqs15 = 0x0000000b,
.EmcDllXformDq0 = 0x0000000c,
.EmcDllXformDq1 = 0x0000000c,
.EmcDllXformDq2 = 0x0000000c,
.EmcDllXformDq3 = 0x0000000c,
.EmcDllXformDq4 = 0x0000000c,
.EmcDllXformDq5 = 0x0000000c,
.EmcDllXformDq6 = 0x0000000c,
.EmcDllXformDq7 = 0x0000000c,
.WarmBootWait = 0x00000001,
.EmcCttTermCtrl = 0x00000802,
.EmcOdtWrite = 0x00000000,
.EmcOdtRead = 0x00000000,
.EmcZcalInterval = 0x00064000,
.EmcZcalWaitCnt = 0x00000034,
.EmcZcalMrwCmd = 0x000a0056,
.EmcMrsResetDll = 0x00000000,
.EmcZcalInitDev0 = 0x840a00ff,
.EmcZcalInitDev1 = 0x440a00ff,
.EmcZcalInitWait = 0x00000001,
.EmcZcalWarmColdBootEnables = 0x00000003,
.EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab,
.EmcZqCalDdr3WarmBoot = 0x00000000,
.EmcZcalWarmBootWait = 0x00000001,
.EmcMrsWarmBootEnable = 0x00000001,
.EmcMrsResetDllWait = 0x00000000,
.EmcMrsExtra = 0x00000000,
.EmcWarmBootMrsExtra = 0x00000000,
.EmcEmrsDdr2DllEnable = 0x00000000,
.EmcMrsDdr2DllReset = 0x00000000,
.EmcEmrsDdr2OcdCalib = 0x00000000,
.EmcDdr2Wait = 0x00000000,
.EmcClkenOverride = 0x00000000,
.McDisExtraSnapLevels = 0x00000000,
.EmcExtraRefreshNum = 0x00000002,
.EmcClkenOverrideAllWarmBoot = 0x00000000,
.McClkenOverrideAllWarmBoot = 0x00000000,
.EmcCfgDigDllPeriodWarmBoot = 0x00000003,
.PmcVddpSel = 0x00000001,
.PmcVddpSelWait = 0x00000002,
.PmcDdrPwr = 0x00000003,
.PmcDdrCfg = 0x00001000,
.PmcIoDpd3Req = 0x4ffefef7,
.PmcIoDpd3ReqWait = 0x00000000,
.PmcRegShort = 0x0000330f,
.PmcNoIoPower = 0x00000000,
.PmcPorDpdCtrlWait = 0x00000001,
.EmcXm2CmdPadCtrl = 0x00000220,
.EmcXm2CmdPadCtrl2 = 0x770c0000,
.EmcXm2CmdPadCtrl3 = 0x050c0000,
.EmcXm2CmdPadCtrl4 = 0x00000000,
.EmcXm2CmdPadCtrl5 = 0x00100100,
.EmcXm2DqsPadCtrl = 0x770c1414,
.EmcXm2DqsPadCtrl2 = 0x0123123d,
.EmcXm2DqsPadCtrl3 = 0x51451420,
.EmcXm2DqsPadCtrl4 = 0x00514514,
.EmcXm2DqsPadCtrl5 = 0x00514514,
.EmcXm2DqsPadCtrl6 = 0x51451400,
.EmcXm2DqPadCtrl = 0x770c2990,
.EmcXm2DqPadCtrl2 = 0x00000000,
.EmcXm2DqPadCtrl3 = 0x00000000,
.EmcXm2ClkPadCtrl = 0x77ffc004,
.EmcXm2ClkPadCtrl2 = 0x00000000,
.EmcXm2CompPadCtrl = 0x81f1f008,
.EmcXm2VttGenPadCtrl = 0x07070000,
.EmcXm2VttGenPadCtrl2 = 0x0000003f,
.EmcXm2VttGenPadCtrl3 = 0x015ddddd,
.EmcAcpdControl = 0x00000000,
.EmcSwizzleRank0ByteCfg = 0x00001032,
.EmcSwizzleRank0Byte0 = 0x53067142,
.EmcSwizzleRank0Byte1 = 0x73025146,
.EmcSwizzleRank0Byte2 = 0x20136475,
.EmcSwizzleRank0Byte3 = 0x46273150,
.EmcSwizzleRank1ByteCfg = 0x00003210,
.EmcSwizzleRank1Byte0 = 0x73451026,
.EmcSwizzleRank1Byte1 = 0x73025146,
.EmcSwizzleRank1Byte2 = 0x20641735,
.EmcSwizzleRank1Byte3 = 0x42136075,
.EmcDsrVttgenDrv = 0x0000003f,
.EmcTxdsrvttgen = 0x00000000,
.EmcBgbiasCtl0 = 0x00000000,
.McEmemAdrCfg = 0x00000001,
.McEmemAdrCfgDev0 = 0x00080304,
.McEmemAdrCfgDev1 = 0x00080304,
.McEmemAdrCfgBankMask0 = 0x00001248,
.McEmemAdrCfgBankMask1 = 0x00002490,
.McEmemAdrCfgBankMask2 = 0x00000920,
.McEmemAdrCfgBankSwizzle3 = 0x00000001,
.McEmemCfg = 0x00001000,
.McEmemArbCfg = 0x0f000007,
.McEmemArbOutstandingReq = 0x80000040,
.McEmemArbTimingRcd = 0x00000003,
.McEmemArbTimingRp = 0x00000004,
.McEmemArbTimingRc = 0x00000010,
.McEmemArbTimingRas = 0x0000000a,
.McEmemArbTimingFaw = 0x0000000d,
.McEmemArbTimingRrd = 0x00000002,
.McEmemArbTimingRap2Pre = 0x00000002,
.McEmemArbTimingWap2Pre = 0x00000009,
.McEmemArbTimingR2R = 0x00000003,
.McEmemArbTimingW2W = 0x00000001,
.McEmemArbTimingR2W = 0x00000006,
.McEmemArbTimingW2R = 0x00000006,
.McEmemArbDaTurns = 0x06060103,
.McEmemArbDaCovers = 0x00120b10,
.McEmemArbMisc0 = 0x71c81811,
.McEmemArbMisc1 = 0x70000f03,
.McEmemArbRing1Throttle = 0x001f0000,
.McEmemArbOverride = 0x10000000,
.McEmemArbOverride1 = 0x00000000,
.McEmemArbRsv = 0xff00ff00,
.McClkenOverride = 0x00000000,
.McStatControl = 0x00000000,
.McDisplaySnapRing = 0x00000003,
.McVideoProtectBom = 0xfff00000,
.McVideoProtectBomAdrHi = 0x00000000,
.McVideoProtectSizeMb = 0x00000000,
.McVideoProtectVprOverride = 0xe4bac743,
.McVideoProtectVprOverride1 = 0x00000013,
.McVideoProtectGpuOverride0 = 0x00000000,
.McVideoProtectGpuOverride1 = 0x00000000,
.McSecCarveoutBom = 0xfff00000,
.McSecCarveoutAdrHi = 0x00000000,
.McSecCarveoutSizeMb = 0x00000000,
.McVideoProtectWriteAccess = 0x00000000,
.McSecCarveoutProtectWriteAccess = 0x00000000,
.EmcCaTrainingEnable = 0x00000001,
.EmcCaTrainingTimingCntl1 = 0x09257359,
.EmcCaTrainingTimingCntl2 = 0x00000017,
.SwizzleRankByteEncode = 0x00000008,
.BootRomPatchControl = 0x00000000,
.BootRomPatchData = 0x00000000,
.McMtsCarveoutBom = 0x78000000,
.McMtsCarveoutAdrHi = 0x00000001,
.McMtsCarveoutSizeMb = 0x00000080,
.McMtsCarveoutRegCtrl = 0x00000001,
},

311
src/mainboard/google/rush_ryu/bct/sdram-micron-4GB-924.inc
View File

@@ -1,311 +0,0 @@
{ /* generated from sdram-micron-4GB-924.cfg; do not edit. This is Micron LPDDR3 */
.MemoryType = NvBootMemoryType_LpDdr2,
.PllMInputDivider = 0x00000001,
.PllMFeedbackDivider = 0x0000004d,
.PllMStableTime = 0x0000012c,
.PllMSetupControl = 0x00000000,
.PllMSelectDiv2 = 0x00000000,
.PllMPDLshiftPh45 = 0x00000001,
.PllMPDLshiftPh90 = 0x00000001,
.PllMPDLshiftPh135 = 0x00000001,
.PllMKCP = 0x00000000,
.PllMKVCO = 0x00000000,
.EmcBctSpare0 = 0x00000000,
.EmcBctSpare1 = 0x00000000,
.EmcBctSpare2 = 0x00000000,
.EmcBctSpare3 = 0x00000000,
.EmcBctSpare4 = 0x00000000,
.EmcBctSpare5 = 0x00000000,
.EmcBctSpare6 = 0x00000000,
.EmcBctSpare7 = 0x00000000,
.EmcBctSpare8 = 0x00000000,
.EmcBctSpare9 = 0x00000000,
.EmcBctSpare10 = 0x00000000,
.EmcBctSpare11 = 0x00000000,
.EmcClockSource = 0x80000000,
.EmcAutoCalInterval = 0x001fffff,
.EmcAutoCalConfig = 0xa1430000,
.EmcAutoCalConfig2 = 0x00000000,
.EmcAutoCalConfig3 = 0x00000000,
.EmcAutoCalWait = 0x00000190,
.EmcAdrCfg = 0x00000001,
.EmcPinProgramWait = 0x00000000,
.EmcPinExtraWait = 0x00000000,
.EmcTimingControlWait = 0x00000000,
.EmcRc = 0x00000037,
.EmcRfc = 0x00000078,
.EmcRfcSlr = 0x00000000,
.EmcRas = 0x00000026,
.EmcRp = 0x00000010,
.EmcR2r = 0x00000000,
.EmcW2w = 0x00000000,
.EmcR2w = 0x00000010,
.EmcW2r = 0x00000010,
.EmcR2p = 0x00000006,
.EmcW2p = 0x00000017,
.EmcRdRcd = 0x00000010,
.EmcWrRcd = 0x00000010,
.EmcRrd = 0x00000009,
.EmcRext = 0x00000005,
.EmcWext = 0x00000000,
.EmcWdv = 0x00000007,
.EmcWdvMask = 0x00000007,
.EmcQUse = 0x00000011,
.EmcQuseWidth = 0x00000004,
.EmcIbdly = 0x00000000,
.EmcEInput = 0x00000006,
.EmcEInputDuration = 0x00000011,
.EmcPutermExtra = 0x000e0000,
.EmcPutermWidth = 0x00000006,
.EmcPutermAdj = 0x00000000,
.EmcCdbCntl1 = 0x00000000,
.EmcCdbCntl2 = 0x00000000,
.EmcCdbCntl3 = 0x00000000,
.EmcQRst = 0x00000005,
.EmcQSafe = 0x00000018,
.EmcRdv = 0x00000020,
.EmcRdvMask = 0x00000022,
.EmcQpop = 0x00000017,
.EmcCtt = 0x00000000,
.EmcCttDuration = 0x00000006,
.EmcRefresh = 0x00000dd4,
.EmcBurstRefreshNum = 0x00000000,
.EmcPreRefreshReqCnt = 0x00000375,
.EmcPdEx2Wr = 0x00000006,
.EmcPdEx2Rd = 0x00000006,
.EmcPChg2Pden = 0x00000010,
.EmcAct2Pden = 0x00000000,
.EmcAr2Pden = 0x00000001,
.EmcRw2Pden = 0x0000001b,
.EmcTxsr = 0x00000082,
.EmcTxsrDll = 0x00000082,
.EmcTcke = 0x00000007,
.EmcTckesr = 0x0000000e,
.EmcTpd = 0x00000007,
.EmcTfaw = 0x0000002d,
.EmcTrpab = 0x00000014,
.EmcTClkStable = 0x00000003,
.EmcTClkStop = 0x00000003,
.EmcTRefBw = 0x00000f04,
.EmcFbioCfg5 = 0x1363a896,
.EmcFbioCfg6 = 0x00000000,
.EmcFbioSpare = 0x00000000,
.EmcCfgRsv = 0xff00ff00,
.EmcMrs = 0x00000000,
.EmcEmrs = 0x00000000,
.EmcEmrs2 = 0x00000000,
.EmcEmrs3 = 0x00000000,
.EmcMrw1 = 0x00010083,
.EmcMrw2 = 0x0002001c,
.EmcMrw3 = 0x00030001,
.EmcMrw4 = 0x800b0000,
.EmcMrwExtra = 0x00010083,
.EmcWarmBootMrwExtra = 0x0002001c,
.EmcWarmBootExtraModeRegWriteEnable = 0x00000000,
.EmcExtraModeRegWriteEnable = 0x00000000,
.EmcMrwResetCommand = 0x003f00fc,
.EmcMrwResetNInitWait = 0x0000000a,
.EmcMrsWaitCnt = 0x039c0019,
.EmcMrsWaitCnt2 = 0x039c0019,
.EmcCfg = 0xf3300000,
.EmcCfg2 = 0x0000089f,
.EmcCfgPipe = 0x00004080,
.EmcDbg = 0x01000c00,
.EmcCmdQ = 0x10004408,
.EmcMc2EmcQ = 0x06000404,
.EmcDynSelfRefControl = 0x80001c77,
.AhbArbitrationXbarCtrlMemInitDone = 0x00000001,
.EmcCfgDigDll = 0xe00400b9,
.EmcCfgDigDllPeriod = 0x00008000,
.EmcDevSelect = 0x00000000,
.EmcSelDpdCtrl = 0x0004001c,
.EmcDllXformDqs0 = 0x00004006,
.EmcDllXformDqs1 = 0x007f800c,
.EmcDllXformDqs2 = 0x007fc008,
.EmcDllXformDqs3 = 0x007f400c,
.EmcDllXformDqs4 = 0x007fc006,
.EmcDllXformDqs5 = 0x00000006,
.EmcDllXformDqs6 = 0x007f800a,
.EmcDllXformDqs7 = 0x007f800c,
.EmcDllXformDqs8 = 0x007f400a,
.EmcDllXformDqs9 = 0x007f400a,
.EmcDllXformDqs10 = 0x007f400a,
.EmcDllXformDqs11 = 0x007f400a,
.EmcDllXformDqs12 = 0x007f400a,
.EmcDllXformDqs13 = 0x007f400a,
.EmcDllXformDqs14 = 0x007f400a,
.EmcDllXformDqs15 = 0x007f400a,
.EmcDllXformQUse0 = 0x00000000,
.EmcDllXformQUse1 = 0x00000000,
.EmcDllXformQUse2 = 0x00000000,
.EmcDllXformQUse3 = 0x00000000,
.EmcDllXformQUse4 = 0x00000000,
.EmcDllXformQUse5 = 0x00000000,
.EmcDllXformQUse6 = 0x00000000,
.EmcDllXformQUse7 = 0x00000000,
.EmcDllXformAddr0 = 0x00018004,
.EmcDllXformAddr1 = 0x00018004,
.EmcDllXformAddr2 = 0x00000008,
.EmcDllXformAddr3 = 0x00014004,
.EmcDllXformAddr4 = 0x0001c002,
.EmcDllXformAddr5 = 0x00000008,
.EmcDllXformQUse8 = 0x00000000,
.EmcDllXformQUse9 = 0x00000000,
.EmcDllXformQUse10 = 0x00000000,
.EmcDllXformQUse11 = 0x00000000,
.EmcDllXformQUse12 = 0x00000000,
.EmcDllXformQUse13 = 0x00000000,
.EmcDllXformQUse14 = 0x00000000,
.EmcDllXformQUse15 = 0x00000000,
.EmcDliTrimTxDqs0 = 0x00000008,
.EmcDliTrimTxDqs1 = 0x00000008,
.EmcDliTrimTxDqs2 = 0x00000008,
.EmcDliTrimTxDqs3 = 0x00000008,
.EmcDliTrimTxDqs4 = 0x00000008,
.EmcDliTrimTxDqs5 = 0x00000008,
.EmcDliTrimTxDqs6 = 0x00000008,
.EmcDliTrimTxDqs7 = 0x00000008,
.EmcDliTrimTxDqs8 = 0x00000008,
.EmcDliTrimTxDqs9 = 0x00000008,
.EmcDliTrimTxDqs10 = 0x00000008,
.EmcDliTrimTxDqs11 = 0x00000008,
.EmcDliTrimTxDqs12 = 0x00000008,
.EmcDliTrimTxDqs13 = 0x00000008,
.EmcDliTrimTxDqs14 = 0x00000008,
.EmcDliTrimTxDqs15 = 0x00000008,
.EmcDllXformDq0 = 0x0000000a,
.EmcDllXformDq1 = 0x0000000a,
.EmcDllXformDq2 = 0x0000000a,
.EmcDllXformDq3 = 0x0000000a,
.EmcDllXformDq4 = 0x0000000a,
.EmcDllXformDq5 = 0x0000000a,
.EmcDllXformDq6 = 0x0000000a,
.EmcDllXformDq7 = 0x0000000a,
.WarmBootWait = 0x00000001,
.EmcCttTermCtrl = 0x00000802,
.EmcOdtWrite = 0x00000000,
.EmcOdtRead = 0x00000000,
.EmcZcalInterval = 0x00064000,
.EmcZcalWaitCnt = 0x00000058,
.EmcZcalMrwCmd = 0x000a0056,
.EmcMrsResetDll = 0x00000000,
.EmcZcalInitDev0 = 0x840a00ff,
.EmcZcalInitDev1 = 0x440a00ff,
.EmcZcalInitWait = 0x00000001,
.EmcZcalWarmColdBootEnables = 0x00000003,
.EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab,
.EmcZqCalDdr3WarmBoot = 0x00000000,
.EmcZcalWarmBootWait = 0x00000001,
.EmcMrsWarmBootEnable = 0x00000001,
.EmcMrsResetDllWait = 0x00000000,
.EmcMrsExtra = 0x00000000,
.EmcWarmBootMrsExtra = 0x00000000,
.EmcEmrsDdr2DllEnable = 0x00000000,
.EmcMrsDdr2DllReset = 0x00000000,
.EmcEmrsDdr2OcdCalib = 0x00000000,
.EmcDdr2Wait = 0x00000000,
.EmcClkenOverride = 0x00000000,
.McDisExtraSnapLevels = 0x00000000,
.EmcExtraRefreshNum = 0x00000002,
.EmcClkenOverrideAllWarmBoot = 0x00000000,
.McClkenOverrideAllWarmBoot = 0x00000000,
.EmcCfgDigDllPeriodWarmBoot = 0x00000003,
.PmcVddpSel = 0x00000001,
.PmcVddpSelWait = 0x00000002,
.PmcDdrPwr = 0x00000003,
.PmcDdrCfg = 0x00001000,
.PmcIoDpd3Req = 0x4ffefef7,
.PmcIoDpd3ReqWait = 0x00000000,
.PmcRegShort = 0x0000330f,
.PmcNoIoPower = 0x00000000,
.PmcPorDpdCtrlWait = 0x00000001,
.EmcXm2CmdPadCtrl = 0x00000220,
.EmcXm2CmdPadCtrl2 = 0x770c0000,
.EmcXm2CmdPadCtrl3 = 0x050c0000,
.EmcXm2CmdPadCtrl4 = 0x00000000,
.EmcXm2CmdPadCtrl5 = 0x00100100,
.EmcXm2DqsPadCtrl = 0x770c1414,
.EmcXm2DqsPadCtrl2 = 0x0120103d,
.EmcXm2DqsPadCtrl3 = 0x65965920,
.EmcXm2DqsPadCtrl4 = 0x00596596,
.EmcXm2DqsPadCtrl5 = 0x00596596,
.EmcXm2DqsPadCtrl6 = 0x65965900,
.EmcXm2DqPadCtrl = 0x770c2990,
.EmcXm2DqPadCtrl2 = 0x00000000,
.EmcXm2DqPadCtrl3 = 0x00000000,
.EmcXm2ClkPadCtrl = 0x77ffc004,
.EmcXm2ClkPadCtrl2 = 0x00000000,
.EmcXm2CompPadCtrl = 0x81f1f008,
.EmcXm2VttGenPadCtrl = 0x07070000,
.EmcXm2VttGenPadCtrl2 = 0x00000000,
.EmcXm2VttGenPadCtrl3 = 0x015ddddd,
.EmcAcpdControl = 0x00000000,
.EmcSwizzleRank0ByteCfg = 0x00001032,
.EmcSwizzleRank0Byte0 = 0x53067142,
.EmcSwizzleRank0Byte1 = 0x73025146,
.EmcSwizzleRank0Byte2 = 0x20136475,
.EmcSwizzleRank0Byte3 = 0x46273150,
.EmcSwizzleRank1ByteCfg = 0x00003210,
.EmcSwizzleRank1Byte0 = 0x73451026,
.EmcSwizzleRank1Byte1 = 0x73025146,
.EmcSwizzleRank1Byte2 = 0x20641735,
.EmcSwizzleRank1Byte3 = 0x42136075,
.EmcDsrVttgenDrv = 0x0000003f,
.EmcTxdsrvttgen = 0x00000000,
.EmcBgbiasCtl0 = 0x00000000,
.McEmemAdrCfg = 0x00000001,
.McEmemAdrCfgDev0 = 0x00080304,
.McEmemAdrCfgDev1 = 0x00080304,
.McEmemAdrCfgBankMask0 = 0x00001248,
.McEmemAdrCfgBankMask1 = 0x00002490,
.McEmemAdrCfgBankMask2 = 0x00000920,
.McEmemAdrCfgBankSwizzle3 = 0x00000001,
.McEmemCfg = 0x00001000,
.McEmemArbCfg = 0x0e00000d,
.McEmemArbOutstandingReq = 0x80000040,
.McEmemArbTimingRcd = 0x00000007,
.McEmemArbTimingRp = 0x00000008,
.McEmemArbTimingRc = 0x0000001b,
.McEmemArbTimingRas = 0x00000012,
.McEmemArbTimingFaw = 0x00000017,
.McEmemArbTimingRrd = 0x00000004,
.McEmemArbTimingRap2Pre = 0x00000004,
.McEmemArbTimingWap2Pre = 0x0000000e,
.McEmemArbTimingR2R = 0x00000004,
.McEmemArbTimingW2W = 0x00000001,
.McEmemArbTimingR2W = 0x00000009,
.McEmemArbTimingW2R = 0x00000009,
.McEmemArbDaTurns = 0x09090104,
.McEmemArbDaCovers = 0x001e141b,
.McEmemArbMisc0 = 0x71ae2a1c,
.McEmemArbMisc1 = 0x70000f02,
.McEmemArbRing1Throttle = 0x001f0000,
.McEmemArbOverride = 0x10000000,
.McEmemArbOverride1 = 0x00000000,
.McEmemArbRsv = 0xff00ff00,
.McClkenOverride = 0x00000000,
.McStatControl = 0x00000000,
.McDisplaySnapRing = 0x00000003,
.McVideoProtectBom = 0xfff00000,
.McVideoProtectBomAdrHi = 0x00000000,
.McVideoProtectSizeMb = 0x00000000,
.McVideoProtectVprOverride = 0xe4bac743,
.McVideoProtectVprOverride1 = 0x00000013,
.McVideoProtectGpuOverride0 = 0x00000000,
.McVideoProtectGpuOverride1 = 0x00000000,
.McSecCarveoutBom = 0xfff00000,
.McSecCarveoutAdrHi = 0x00000000,
.McSecCarveoutSizeMb = 0x00000000,
.McVideoProtectWriteAccess = 0x00000000,
.McSecCarveoutProtectWriteAccess = 0x00000000,
.EmcCaTrainingEnable = 0x00000001,
.EmcCaTrainingTimingCntl1 = 0x09257359,
.EmcCaTrainingTimingCntl2 = 0x00000017,
.SwizzleRankByteEncode = 0x00000008,
.BootRomPatchControl = 0x00000000,
.BootRomPatchData = 0x00000000,
.McMtsCarveoutBom = 0x78000000,
.McMtsCarveoutAdrHi = 0x00000001,
.McMtsCarveoutSizeMb = 0x00000080,
.McMtsCarveoutRegCtrl = 0x00000001,
},

311
src/mainboard/google/rush_ryu/bct/sdram-samsung-4GB-924.inc
View File

@@ -1,311 +0,0 @@
{ /* generated from sdram-4GB-924.cfg; do not edit. This is SAMSUNG LPDDR3 */
.MemoryType = NvBootMemoryType_LpDdr2,
.PllMInputDivider = 0x00000001,
.PllMFeedbackDivider = 0x0000004d,
.PllMStableTime = 0x0000012c,
.PllMSetupControl = 0x00000000,
.PllMSelectDiv2 = 0x00000000,
.PllMPDLshiftPh45 = 0x00000001,
.PllMPDLshiftPh90 = 0x00000001,
.PllMPDLshiftPh135 = 0x00000001,
.PllMKCP = 0x00000000,
.PllMKVCO = 0x00000000,
.EmcBctSpare0 = 0x00000000,
.EmcBctSpare1 = 0x00000000,
.EmcBctSpare2 = 0x00000000,
.EmcBctSpare3 = 0x00000000,
.EmcBctSpare4 = 0x00000000,
.EmcBctSpare5 = 0x00000000,
.EmcBctSpare6 = 0x00000000,
.EmcBctSpare7 = 0x00000000,
.EmcBctSpare8 = 0x00000000,
.EmcBctSpare9 = 0x00000000,
.EmcBctSpare10 = 0x00000000,
.EmcBctSpare11 = 0x00000000,
.EmcClockSource = 0x80000000,
.EmcAutoCalInterval = 0x001fffff,
.EmcAutoCalConfig = 0xa1430000,
.EmcAutoCalConfig2 = 0x00000000,
.EmcAutoCalConfig3 = 0x00000000,
.EmcAutoCalWait = 0x00000190,
.EmcAdrCfg = 0x00000001,
.EmcPinProgramWait = 0x00000000,
.EmcPinExtraWait = 0x00000000,
.EmcTimingControlWait = 0x00000000,
.EmcRc = 0x00000037,
.EmcRfc = 0x00000078,
.EmcRfcSlr = 0x00000000,
.EmcRas = 0x00000026,
.EmcRp = 0x00000010,
.EmcR2r = 0x00000000,
.EmcW2w = 0x00000000,
.EmcR2w = 0x00000010,
.EmcW2r = 0x00000010,
.EmcR2p = 0x00000006,
.EmcW2p = 0x00000017,
.EmcRdRcd = 0x00000010,
.EmcWrRcd = 0x00000010,
.EmcRrd = 0x00000009,
.EmcRext = 0x00000005,
.EmcWext = 0x00000000,
.EmcWdv = 0x00000007,
.EmcWdvMask = 0x00000007,
.EmcQUse = 0x00000011,
.EmcQuseWidth = 0x00000004,
.EmcIbdly = 0x00000000,
.EmcEInput = 0x00000006,
.EmcEInputDuration = 0x00000011,
.EmcPutermExtra = 0x000e0000,
.EmcPutermWidth = 0x00000006,
.EmcPutermAdj = 0x00000000,
.EmcCdbCntl1 = 0x00000000,
.EmcCdbCntl2 = 0x00000000,
.EmcCdbCntl3 = 0x00000000,
.EmcQRst = 0x00000005,
.EmcQSafe = 0x00000018,
.EmcRdv = 0x00000020,
.EmcRdvMask = 0x00000022,
.EmcQpop = 0x00000017,
.EmcCtt = 0x00000000,
.EmcCttDuration = 0x00000006,
.EmcRefresh = 0x00000dd4,
.EmcBurstRefreshNum = 0x00000000,
.EmcPreRefreshReqCnt = 0x00000375,
.EmcPdEx2Wr = 0x00000006,
.EmcPdEx2Rd = 0x00000006,
.EmcPChg2Pden = 0x00000010,
.EmcAct2Pden = 0x00000000,
.EmcAr2Pden = 0x00000001,
.EmcRw2Pden = 0x0000001b,
.EmcTxsr = 0x00000082,
.EmcTxsrDll = 0x00000082,
.EmcTcke = 0x00000007,
.EmcTckesr = 0x0000000e,
.EmcTpd = 0x00000007,
.EmcTfaw = 0x0000002d,
.EmcTrpab = 0x00000014,
.EmcTClkStable = 0x00000003,
.EmcTClkStop = 0x00000003,
.EmcTRefBw = 0x00000f04,
.EmcFbioCfg5 = 0x1363a896,
.EmcFbioCfg6 = 0x00000000,
.EmcFbioSpare = 0x00000000,
.EmcCfgRsv = 0xff00ff00,
.EmcMrs = 0x00000000,
.EmcEmrs = 0x00000000,
.EmcEmrs2 = 0x00000000,
.EmcEmrs3 = 0x00000000,
.EmcMrw1 = 0x00010083,
.EmcMrw2 = 0x0002001c,
.EmcMrw3 = 0x00030001,
.EmcMrw4 = 0x800b0000,
.EmcMrwExtra = 0x00010083,
.EmcWarmBootMrwExtra = 0x0002001c,
.EmcWarmBootExtraModeRegWriteEnable = 0x00000000,
.EmcExtraModeRegWriteEnable = 0x00000000,
.EmcMrwResetCommand = 0x003f00fc,
.EmcMrwResetNInitWait = 0x0000000a,
.EmcMrsWaitCnt = 0x039c0019,
.EmcMrsWaitCnt2 = 0x039c0019,
.EmcCfg = 0xf3300000,
.EmcCfg2 = 0x0000089f,
.EmcCfgPipe = 0x00004080,
.EmcDbg = 0x01000c00,
.EmcCmdQ = 0x10004408,
.EmcMc2EmcQ = 0x06000404,
.EmcDynSelfRefControl = 0x80001c77,
.AhbArbitrationXbarCtrlMemInitDone = 0x00000001,
.EmcCfgDigDll = 0xe00400b9,
.EmcCfgDigDllPeriod = 0x00008000,
.EmcDevSelect = 0x00000000,
.EmcSelDpdCtrl = 0x0004001c,
.EmcDllXformDqs0 = 0x007fc00a,
.EmcDllXformDqs1 = 0x007fc00a,
.EmcDllXformDqs2 = 0x007fc00a,
.EmcDllXformDqs3 = 0x007fc00a,
.EmcDllXformDqs4 = 0x007f800c,
.EmcDllXformDqs5 = 0x00000008,
.EmcDllXformDqs6 = 0x007f800a,
.EmcDllXformDqs7 = 0x007fc00a,
.EmcDllXformDqs8 = 0x007f400a,
.EmcDllXformDqs9 = 0x007f400a,
.EmcDllXformDqs10 = 0x007f400a,
.EmcDllXformDqs11 = 0x007f400a,
.EmcDllXformDqs12 = 0x007f400a,
.EmcDllXformDqs13 = 0x007f400a,
.EmcDllXformDqs14 = 0x007f400a,
.EmcDllXformDqs15 = 0x007f400a,
.EmcDllXformQUse0 = 0x00000000,
.EmcDllXformQUse1 = 0x00000000,
.EmcDllXformQUse2 = 0x00000000,
.EmcDllXformQUse3 = 0x00000000,
.EmcDllXformQUse4 = 0x00000000,
.EmcDllXformQUse5 = 0x00000000,
.EmcDllXformQUse6 = 0x00000000,
.EmcDllXformQUse7 = 0x00000000,
.EmcDllXformAddr0 = 0x00018002,
.EmcDllXformAddr1 = 0x00018002,
.EmcDllXformAddr2 = 0x00000008,
.EmcDllXformAddr3 = 0x00018002,
.EmcDllXformAddr4 = 0x00018002,
.EmcDllXformAddr5 = 0x00000008,
.EmcDllXformQUse8 = 0x00000000,
.EmcDllXformQUse9 = 0x00000000,
.EmcDllXformQUse10 = 0x00000000,
.EmcDllXformQUse11 = 0x00000000,
.EmcDllXformQUse12 = 0x00000000,
.EmcDllXformQUse13 = 0x00000000,
.EmcDllXformQUse14 = 0x00000000,
.EmcDllXformQUse15 = 0x00000000,
.EmcDliTrimTxDqs0 = 0x00000008,
.EmcDliTrimTxDqs1 = 0x00000008,
.EmcDliTrimTxDqs2 = 0x00000008,
.EmcDliTrimTxDqs3 = 0x00000008,
.EmcDliTrimTxDqs4 = 0x00000008,
.EmcDliTrimTxDqs5 = 0x00000008,
.EmcDliTrimTxDqs6 = 0x00000008,
.EmcDliTrimTxDqs7 = 0x00000008,
.EmcDliTrimTxDqs8 = 0x00000008,
.EmcDliTrimTxDqs9 = 0x00000008,
.EmcDliTrimTxDqs10 = 0x00000008,
.EmcDliTrimTxDqs11 = 0x00000008,
.EmcDliTrimTxDqs12 = 0x00000008,
.EmcDliTrimTxDqs13 = 0x00000008,
.EmcDliTrimTxDqs14 = 0x00000008,
.EmcDliTrimTxDqs15 = 0x00000008,
.EmcDllXformDq0 = 0x0000000c,
.EmcDllXformDq1 = 0x0000000c,
.EmcDllXformDq2 = 0x0000000c,
.EmcDllXformDq3 = 0x0000000c,
.EmcDllXformDq4 = 0x0000000c,
.EmcDllXformDq5 = 0x0000000c,
.EmcDllXformDq6 = 0x0000000c,
.EmcDllXformDq7 = 0x0000000c,
.WarmBootWait = 0x00000001,
.EmcCttTermCtrl = 0x00000802,
.EmcOdtWrite = 0x00000000,
.EmcOdtRead = 0x00000000,
.EmcZcalInterval = 0x00064000,
.EmcZcalWaitCnt = 0x00000058,
.EmcZcalMrwCmd = 0x000a0056,
.EmcMrsResetDll = 0x00000000,
.EmcZcalInitDev0 = 0x840a00ff,
.EmcZcalInitDev1 = 0x440a00ff,
.EmcZcalInitWait = 0x00000001,
.EmcZcalWarmColdBootEnables = 0x00000003,
.EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab,
.EmcZqCalDdr3WarmBoot = 0x00000000,
.EmcZcalWarmBootWait = 0x00000001,
.EmcMrsWarmBootEnable = 0x00000001,
.EmcMrsResetDllWait = 0x00000000,
.EmcMrsExtra = 0x00000000,
.EmcWarmBootMrsExtra = 0x00000000,
.EmcEmrsDdr2DllEnable = 0x00000000,
.EmcMrsDdr2DllReset = 0x00000000,
.EmcEmrsDdr2OcdCalib = 0x00000000,
.EmcDdr2Wait = 0x00000000,
.EmcClkenOverride = 0x00000000,
.McDisExtraSnapLevels = 0x00000000,
.EmcExtraRefreshNum = 0x00000002,
.EmcClkenOverrideAllWarmBoot = 0x00000000,
.McClkenOverrideAllWarmBoot = 0x00000000,
.EmcCfgDigDllPeriodWarmBoot = 0x00000003,
.PmcVddpSel = 0x00000001,
.PmcVddpSelWait = 0x00000002,
.PmcDdrPwr = 0x00000003,
.PmcDdrCfg = 0x00001000,
.PmcIoDpd3Req = 0x4ffefef7,
.PmcIoDpd3ReqWait = 0x00000000,
.PmcRegShort = 0x0000330f,
.PmcNoIoPower = 0x00000000,
.PmcPorDpdCtrlWait = 0x00000001,
.EmcXm2CmdPadCtrl = 0x00000220,
.EmcXm2CmdPadCtrl2 = 0x770c0000,
.EmcXm2CmdPadCtrl3 = 0x050c0000,
.EmcXm2CmdPadCtrl4 = 0x00000000,
.EmcXm2CmdPadCtrl5 = 0x00100100,
.EmcXm2DqsPadCtrl = 0x770c1414,
.EmcXm2DqsPadCtrl2 = 0x0120103d,
.EmcXm2DqsPadCtrl3 = 0x55555520,
.EmcXm2DqsPadCtrl4 = 0x00596596,
.EmcXm2DqsPadCtrl5 = 0x00596596,
.EmcXm2DqsPadCtrl6 = 0x55555500,
.EmcXm2DqPadCtrl = 0x770c2990,
.EmcXm2DqPadCtrl2 = 0x00000000,
.EmcXm2DqPadCtrl3 = 0x00000000,
.EmcXm2ClkPadCtrl = 0x77ffc004,
.EmcXm2ClkPadCtrl2 = 0x00000000,
.EmcXm2CompPadCtrl = 0x81f1f008,
.EmcXm2VttGenPadCtrl = 0x07070000,
.EmcXm2VttGenPadCtrl2 = 0x00000000,
.EmcXm2VttGenPadCtrl3 = 0x015ddddd,
.EmcAcpdControl = 0x00000000,
.EmcSwizzleRank0ByteCfg = 0x00001032,
.EmcSwizzleRank0Byte0 = 0x53067142,
.EmcSwizzleRank0Byte1 = 0x73025146,
.EmcSwizzleRank0Byte2 = 0x20136475,
.EmcSwizzleRank0Byte3 = 0x46273150,
.EmcSwizzleRank1ByteCfg = 0x00003210,
.EmcSwizzleRank1Byte0 = 0x73451026,
.EmcSwizzleRank1Byte1 = 0x73025146,
.EmcSwizzleRank1Byte2 = 0x20641735,
.EmcSwizzleRank1Byte3 = 0x42136075,
.EmcDsrVttgenDrv = 0x0000003f,
.EmcTxdsrvttgen = 0x00000000,
.EmcBgbiasCtl0 = 0x00000000,
.McEmemAdrCfg = 0x00000001,
.McEmemAdrCfgDev0 = 0x00080304,
.McEmemAdrCfgDev1 = 0x00080304,
.McEmemAdrCfgBankMask0 = 0x00001248,
.McEmemAdrCfgBankMask1 = 0x00002490,
.McEmemAdrCfgBankMask2 = 0x00000920,
.McEmemAdrCfgBankSwizzle3 = 0x00000001,
.McEmemCfg = 0x00001000,
.McEmemArbCfg = 0x0e00000d,
.McEmemArbOutstandingReq = 0x80000040,
.McEmemArbTimingRcd = 0x00000007,
.McEmemArbTimingRp = 0x00000008,
.McEmemArbTimingRc = 0x0000001b,
.McEmemArbTimingRas = 0x00000012,
.McEmemArbTimingFaw = 0x00000017,
.McEmemArbTimingRrd = 0x00000004,
.McEmemArbTimingRap2Pre = 0x00000004,
.McEmemArbTimingWap2Pre = 0x0000000e,
.McEmemArbTimingR2R = 0x00000004,
.McEmemArbTimingW2W = 0x00000001,
.McEmemArbTimingR2W = 0x00000009,
.McEmemArbTimingW2R = 0x00000009,
.McEmemArbDaTurns = 0x09090104,
.McEmemArbDaCovers = 0x001e141b,
.McEmemArbMisc0 = 0x71ae2a1c,
.McEmemArbMisc1 = 0x70000f02,
.McEmemArbRing1Throttle = 0x001f0000,
.McEmemArbOverride = 0x10000000,
.McEmemArbOverride1 = 0x00000000,
.McEmemArbRsv = 0xff00ff00,
.McClkenOverride = 0x00000000,
.McStatControl = 0x00000000,
.McDisplaySnapRing = 0x00000003,
.McVideoProtectBom = 0xfff00000,
.McVideoProtectBomAdrHi = 0x00000000,
.McVideoProtectSizeMb = 0x00000000,
.McVideoProtectVprOverride = 0xe4bac743,
.McVideoProtectVprOverride1 = 0x00000013,
.McVideoProtectGpuOverride0 = 0x00000000,
.McVideoProtectGpuOverride1 = 0x00000000,
.McSecCarveoutBom = 0xfff00000,
.McSecCarveoutAdrHi = 0x00000000,
.McSecCarveoutSizeMb = 0x00000000,
.McVideoProtectWriteAccess = 0x00000000,
.McSecCarveoutProtectWriteAccess = 0x00000000,
.EmcCaTrainingEnable = 0x00000001,
.EmcCaTrainingTimingCntl1 = 0x09257359,
.EmcCaTrainingTimingCntl2 = 0x00000017,
.SwizzleRankByteEncode = 0x00000008,
.BootRomPatchControl = 0x00000000,
.BootRomPatchData = 0x00000000,
.McMtsCarveoutBom = 0x78000000,
.McMtsCarveoutAdrHi = 0x00000001,
.McMtsCarveoutSizeMb = 0x00000080,
.McMtsCarveoutRegCtrl = 0x00000001,
},

31
src/mainboard/google/rush_ryu/bct/spi.cfg
View File

@@ -1,31 +0,0 @@
# Copyright (c) 2013 The Chromium OS Authors. All rights reserved.
# Distributed under the terms of the GNU General Public License v2
Version = 0x00130001;
BlockSize = 32768;
PageSize = 2048;
PartitionSize = 4194304;
DevType[0] = NvBootDevType_Spi;
DeviceParam[0].SpiFlashParams.ReadCommandTypeFast = NV_FALSE;
DeviceParam[0].SpiFlashParams.ClockDivider = 0x16;
DeviceParam[0].SpiFlashParams.ClockSource = NvBootSpiClockSource_PllPOut0;
DeviceParam[0].SpiFlashParams.PageSize2kor16k = 0;
DevType[1] = NvBootDevType_Spi;
DeviceParam[1].SpiFlashParams.ReadCommandTypeFast = NV_FALSE;
DeviceParam[1].SpiFlashParams.ClockDivider = 0x16;
DeviceParam[1].SpiFlashParams.ClockSource = NvBootSpiClockSource_PllPOut0;
DeviceParam[1].SpiFlashParams.PageSize2kor16k = 0;
DevType[2] = NvBootDevType_Spi;
DeviceParam[2].SpiFlashParams.ReadCommandTypeFast = NV_FALSE;
DeviceParam[2].SpiFlashParams.ClockDivider = 0x16;
DeviceParam[2].SpiFlashParams.ClockSource = NvBootSpiClockSource_PllPOut0;
DeviceParam[2].SpiFlashParams.PageSize2kor16k = 0;
DevType[3] = NvBootDevType_Spi;
DeviceParam[3].SpiFlashParams.ReadCommandTypeFast = NV_FALSE;
DeviceParam[3].SpiFlashParams.ClockDivider = 0x16;
DeviceParam[3].SpiFlashParams.ClockSource = NvBootSpiClockSource_PllPOut0;
DeviceParam[3].SpiFlashParams.PageSize2kor16k = 0;

6
src/mainboard/google/rush_ryu/board_info.txt
View File

@@ -1,6 +0,0 @@
Vendor name: Google
Board name: Rush Ryu Nvidia Tegra132 board
Category: eval
ROM protocol: SPI
ROM socketed: n
Flashrom support: y

33
src/mainboard/google/rush_ryu/boardid.c
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@@ -1,33 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <boardid.h>
#include <console/console.h>
#include <stdlib.h>
#include "gpio.h"
uint8_t board_id(void)
{
static int id = -1;
if (id < 0) {
gpio_t gpio[] = {[1] = BD_ID1, [0] = BD_ID0}; /* ID0 is LSB */
id = gpio_base3_value(gpio, ARRAY_SIZE(gpio));
}
return id;
}

89
src/mainboard/google/rush_ryu/bootblock.c
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@@ -1,89 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <arch/io.h>
#include <bootblock_common.h>
#include <console/console.h>
#include <device/i2c.h>
#include <soc/addressmap.h>
#include <soc/clk_rst.h>
#include <soc/clock.h>
#include <soc/funitcfg.h>
#include <soc/nvidia/tegra/i2c.h>
#include <soc/padconfig.h>
#include "pmic.h"
static const struct pad_config uart_console_pads[] = {
/* UARTA: tx and rx. */
PAD_CFG_SFIO(KB_ROW9, PINMUX_PULL_NONE, UA3),
PAD_CFG_SFIO(KB_ROW10, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, UA3),
/*
* Disable UART2 pads as they are default connected to UARTA controller.
*/
PAD_CFG_UNUSED(UART2_RXD),
PAD_CFG_UNUSED(UART2_TXD),
PAD_CFG_UNUSED(UART2_RTS_N),
PAD_CFG_UNUSED(UART2_CTS_N),
};
static const struct pad_config pmic_pads[] = {
PAD_CFG_SFIO(PWR_I2C_SCL, PINMUX_INPUT_ENABLE, I2CPMU),
PAD_CFG_SFIO(PWR_I2C_SDA, PINMUX_INPUT_ENABLE, I2CPMU),
};
static const struct pad_config spiflash_pads[] = {
/* mosi, miso, clk, cs0 */
PAD_CFG_SFIO(GPIO_PG6, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, SPI4),
PAD_CFG_SFIO(GPIO_PG7, PINMUX_INPUT_ENABLE | PINMUX_PULL_UP, SPI4),
PAD_CFG_SFIO(GPIO_PG5, PINMUX_INPUT_ENABLE, SPI4),
PAD_CFG_SFIO(GPIO_PI3, PINMUX_INPUT_ENABLE, SPI4),
};
static const struct funit_cfg funits[] = {
/* PMIC on I2C5 (PWR_I2C* pads) at 400kHz. */
FUNIT_CFG(I2C5, PLLP, 400, pmic_pads, ARRAY_SIZE(pmic_pads)),
/* SPI flash at 33MHz on SPI4 controller. */
FUNIT_CFG(SBC4, PLLP, 33333, spiflash_pads, ARRAY_SIZE(spiflash_pads)),
};
void bootblock_mainboard_early_init(void)
{
soc_configure_pads(uart_console_pads, ARRAY_SIZE(uart_console_pads));
}
static void set_clock_sources(void)
{
/* UARTA gets PLLP, deactivate CLK_UART_DIV_OVERRIDE */
write32(CLK_RST_REG(clk_src_uarta), PLLP << CLK_SOURCE_SHIFT);
}
static const struct pad_config padcfgs[] = {
/* Board build id bits 1:0 */
PAD_CFG_GPIO_INPUT(KB_COL4, PINMUX_PULL_NONE),
PAD_CFG_GPIO_INPUT(KB_COL3, PINMUX_PULL_NONE),
};
void bootblock_mainboard_init(void)
{
set_clock_sources();
/* Set up controllers and pads to load romstage. */
soc_configure_funits(funits, ARRAY_SIZE(funits));
soc_configure_pads(padcfgs, ARRAY_SIZE(padcfgs));
i2c_init(I2CPWR_BUS);
pmic_init(I2CPWR_BUS);
}

67
src/mainboard/google/rush_ryu/chromeos.c
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@@ -1,67 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <boardid.h>
#include <boot/coreboot_tables.h>
#include <console/console.h>
#include <ec/google/chromeec/ec.h>
#include <ec/google/chromeec/ec_commands.h>
#include <string.h>
#include <vendorcode/google/chromeos/chromeos.h>
#include "gpio.h"
static inline uint32_t get_pwr_btn_polarity(void)
{
if (board_id() < BOARD_ID_PROTO_3)
return ACTIVE_HIGH;
return ACTIVE_LOW;
}
void fill_lb_gpios(struct lb_gpios *gpios)
{
struct lb_gpio chromeos_gpios[] = {
{WRITE_PROTECT_L, ACTIVE_LOW, gpio_get(WRITE_PROTECT_L),
"write protect"},
{-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"},
/* TODO(adurbin): add lid switch */
{POWER_BUTTON, get_pwr_btn_polarity(), -1, "power"},
{-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"},
{EC_IN_RW, ACTIVE_HIGH, -1, "EC in RW"},
{AP_SYS_RESET_L, ACTIVE_LOW, -1, "reset"},
};
lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
}
int get_developer_mode_switch(void)
{
return 0;
}
int get_recovery_mode_switch(void)
{
uint32_t ec_events;
ec_events = google_chromeec_get_events_b();
return !!(ec_events &
EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY));
}
int get_write_protect_state(void)
{
return !gpio_get(WRITE_PROTECT_L);
}

27
src/mainboard/google/rush_ryu/chromeos.fmd
View File

@@ -1,27 +0,0 @@
FLASH@0x0 0x800000 {
WP_RO@0x0 0x300000 {
RO_SECTION@0x0 0x2f0000 {
BOOTBLOCK@0 128K
COREBOOT(CBFS)@0x20000 0x1e0000
FMAP@0x200000 0x1000
GBB@0x201000 0xeef00
RO_FRID@0x2eff00 0x100
}
RO_VPD@0x2f0000 0x10000
}
RW_SECTION_A@0x300000 0x278000 {
VBLOCK_A@0x0 0x2000
FW_MAIN_A(CBFS)@0x2000 0x275f00
RW_FWID_A@0x277f00 0x100
}
RW_SHARED@0x578000 0x4000 {
SHARED_DATA@0x0 0x4000
}
RW_ELOG@0x57c000 0x4000
RW_SECTION_B@0x580000 0x278000 {
VBLOCK_B@0x0 0x2000
FW_MAIN_B(CBFS)@0x2000 0x275f00
RW_FWID_B@0x277f00 0x100
}
RW_VPD@0x7f8000 0x8000
}

47
src/mainboard/google/rush_ryu/devicetree.cb
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@@ -1,47 +0,0 @@
##
## This file is part of the coreboot project.
##
## Copyright 2014 Google Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
chip soc/nvidia/tegra132
device cpu_cluster 0 on
end
register "display_controller" = "TEGRA_ARM_DISPLAYA"
register "xres" = "2560"
register "yres" = "1800"
# bits per pixel and color depth
register "framebuffer_bits_per_pixel" = "32"
register "color_depth" = "12"
# framebuffer resolution
register "display_xres" = "1280"
register "display_yres" = "800"
register "href_to_sync" = "1"
register "hfront_porch" = "80"
register "hsync_width" = "80"
register "hback_porch" = "80"
register "vref_to_sync" = "1"
register "vfront_porch" = "4"
register "vsync_width" = "4"
register "vback_porch" = "4"
register "refresh" = "60"
# kernel driver
register "pixel_clock" = "301620000"
register "win_opt" = "DSI_ENABLE"
end

70
src/mainboard/google/rush_ryu/gpio.h
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@@ -1,70 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __MAINBOARD_GOOGLE_RUSH_RYU_GPIO_H__
#define __MAINBOARD_GOOGLE_RUSH_RYU_GPIO_H__
#include <gpio.h>
#include <base3.h>
/* Board ID definitions. */
enum {
BOARD_REV0 = BASE3(0, 0),
BOARD_REV1 = BASE3(0, 1),
BOARD_REV2 = BASE3(0, Z),
BOARD_REV3 = BASE3(1, 0),
BOARD_REV4 = BASE3(1, 1),
BOARD_REV5 = BASE3(1, Z),
BOARD_REV6 = BASE3(Z, 0),
BOARD_REV7 = BASE3(Z, 1),
BOARD_REV8 = BASE3(Z, Z),
BOARD_ID_PROTO_0 = BOARD_REV0,
BOARD_ID_PROTO_1 = BOARD_REV1,
BOARD_ID_PROTO_3 = BOARD_REV2,
BOARD_ID_PROTO_4 = BOARD_REV3,
BOARD_ID_EVT = BOARD_REV4,
BOARD_ID_DVT = BOARD_REV5,
BOARD_ID_PVT = BOARD_REV6,
BOARD_ID_MP = BOARD_REV7,
};
enum {
/* Board ID related GPIOS. */
BD_ID0 = GPIO(Q3),
BD_ID1 = GPIO(Q4),
/* LTE modem related GPIOs */
MODEM_RESET = GPIO(S3),
MODEM_PWR_ON = GPIO(S4),
MDM_DET = GPIO(V1),
/* Warm reset */
AP_SYS_RESET_L = GPIO(I5),
/* Write Protect */
SPI_1V8_WP_L = GPIO(R1),
WRITE_PROTECT_L = SPI_1V8_WP_L,
/* Power button - Depending on board id, maybe active high / low */
BTN_AP_PWR = GPIO(Q0),
POWER_BUTTON = BTN_AP_PWR,
/* EC in RW signal */
EC_IN_RW = GPIO(U4),
/* Panel related GPIOs */
LCD_EN = GPIO(H5),
LCD_RST_L = GPIO(H3),
EN_VDD18_LCD = GPIO(X0),
EN_VDD_LCD = GPIO(BB6), /* P1/P3 board */
};
#endif /* __MAINBOARD_GOOGLE_RUSH_RYU_GPIO_H__ */

302
src/mainboard/google/rush_ryu/mainboard.c
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@@ -1,302 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <arch/mmu.h>
#include <boardid.h>
#include <bootmode.h>
#include <boot/coreboot_tables.h>
#include <cbmem.h>
#include <delay.h>
#include <device/device.h>
#include <device/i2c.h>
#include <elog.h>
#include <memrange.h>
#include <soc/addressmap.h>
#include <soc/clk_rst.h>
#include <soc/clock.h>
#include <soc/funitcfg.h>
#include <soc/nvidia/tegra/i2c.h>
#include <soc/padconfig.h>
#include <soc/nvidia/tegra/dc.h>
#include <soc/display.h>
#include <vendorcode/google/chromeos/chromeos.h>
#include <vendorcode/google/chromeos/cros_vpd.h>
#if IS_ENABLED(CONFIG_CHROMEOS)
#include <vboot_struct.h>
#include <vboot/misc.h>
#include <vboot/vboot_common.h>
#endif
#include "gpio.h"
#include "pmic.h"
static const struct pad_config mmcpads[] = {
/* MMC4 (eMMC) */
PAD_CFG_SFIO(SDMMC4_CLK, PINMUX_INPUT_ENABLE|PINMUX_PULL_DOWN, SDMMC4),
PAD_CFG_SFIO(SDMMC4_CMD, PINMUX_INPUT_ENABLE|PINMUX_PULL_UP, SDMMC4),
PAD_CFG_SFIO(SDMMC4_DAT0, PINMUX_INPUT_ENABLE|PINMUX_PULL_UP, SDMMC4),
PAD_CFG_SFIO(SDMMC4_DAT1, PINMUX_INPUT_ENABLE|PINMUX_PULL_UP, SDMMC4),
PAD_CFG_SFIO(SDMMC4_DAT2, PINMUX_INPUT_ENABLE|PINMUX_PULL_UP, SDMMC4),
PAD_CFG_SFIO(SDMMC4_DAT3, PINMUX_INPUT_ENABLE|PINMUX_PULL_UP, SDMMC4),
PAD_CFG_SFIO(SDMMC4_DAT4, PINMUX_INPUT_ENABLE|PINMUX_PULL_UP, SDMMC4),
PAD_CFG_SFIO(SDMMC4_DAT5, PINMUX_INPUT_ENABLE|PINMUX_PULL_UP, SDMMC4),
PAD_CFG_SFIO(SDMMC4_DAT6, PINMUX_INPUT_ENABLE|PINMUX_PULL_UP, SDMMC4),
PAD_CFG_SFIO(SDMMC4_DAT7, PINMUX_INPUT_ENABLE|PINMUX_PULL_UP, SDMMC4),
};
static const struct pad_config audio_codec_pads[] = {
/* H1 is CODEC_RST_L and R2(ROW2) is AUDIO_ENABLE */
PAD_CFG_GPIO_OUT1(GPIO_PH1, PINMUX_PULL_DOWN),
PAD_CFG_GPIO_OUT1(KB_ROW2, PINMUX_PULL_DOWN),
};
static const struct funit_cfg funits[] = {
/* MMC on SDMMC4 controller at 48MHz. */
FUNIT_CFG(SDMMC4, PLLP, 48000, mmcpads, ARRAY_SIZE(mmcpads)),
/* I2C6 for audio, temp sensor, etc. Enable codec via GPIOs/muxes */
FUNIT_CFG(I2C6, PLLP, 400, audio_codec_pads, ARRAY_SIZE(audio_codec_pads)),
FUNIT_CFG_USB(USBD),
};
/* HACK: For proto boards before proto3, we want to disable ec sw sync */
static void fix_ec_sw_sync(void)
{
#if IS_ENABLED(CONFIG_CHROMEOS)
struct vboot_handoff *vh;
if (board_id() >= BOARD_ID_PROTO_3)
return;
vh = cbmem_find(CBMEM_ID_VBOOT_HANDOFF);
if (vh == NULL) {
printk(BIOS_ERR, "No vboot handoff struct found\n");
return;
}
VbSharedDataHeader *vb_sd = (VbSharedDataHeader *)vh->shared_data;
vb_sd->flags &= ~VBSD_EC_SOFTWARE_SYNC;
#endif
}
static const struct pad_config lcd_gpio_padcfgs[] = {
/* LCD_EN */
PAD_CFG_GPIO_OUT0(GPIO_PH5, PINMUX_PULL_UP),
/* LCD_RST_L */
PAD_CFG_GPIO_OUT0(GPIO_PH3, PINMUX_PULL_UP),
/* EN_VDD_LCD */
PAD_CFG_GPIO_OUT0(GPIO_PBB6, PINMUX_PULL_NONE),
/* EN_VDD18_LCD */
PAD_CFG_GPIO_OUT0(DVFS_PWM, PINMUX_PULL_DOWN),
};
static void configure_display_clocks(void)
{
u32 lclks = CLK_L_HOST1X | CLK_L_DISP1; /* dc */
u32 hclks = CLK_H_MIPI_CAL | CLK_H_DSI; /* mipi phy, mipi-dsi a */
u32 uclks = CLK_U_DSIB; /* mipi-dsi b */
u32 xclks = CLK_X_CLK72MHZ; /* clk src of mipi_cal */
clock_enable_clear_reset(lclks, hclks, uclks, 0, 0, xclks);
/* Give clocks time to stabilize. */
udelay(IO_STABILIZATION_DELAY);
}
static int enable_lcd_vdd(void)
{
uint8_t data;
/* Set 1.20V to power AVDD_DSI_CSI */
pmic_write_reg(I2CPWR_BUS, TI65913_LDO5_VOLTAGE,
VSEL_1200, 1);
pmic_write_reg(I2CPWR_BUS, TI65913_LDO5_CTRL,
TI65913_MODE_ACTIVE_ON, 1);
/*
* Enable VDD_LCD
*
* Use different GPIO based on board id
*/
switch (board_id()) {
case BOARD_ID_PROTO_0:
/* Select PMIC GPIO_6's primary function */
pmic_read_reg(I2CPWR_BUS, TI65913_PAD2, &data);
pmic_write_reg(I2CPWR_BUS, TI65913_PAD2,
PAD2_GPIO_6_PRIMARY(data), 0);
/* Set PMIC_GPIO_6 as output */
pmic_read_reg(I2CPWR_BUS, TI65913_GPIO_DATA_DIR, &data);
pmic_write_reg(I2CPWR_BUS, TI65913_GPIO_DATA_DIR,
TI65913_GPIO_6_OUTPUT, 0);
/* Set PMIC_GPIO_6 output high */
pmic_read_reg(I2CPWR_BUS, TI65913_GPIO_DATA_OUT, &data);
pmic_write_reg(I2CPWR_BUS, TI65913_GPIO_DATA_OUT,
TI65913_GPIO_6_HIGH, 1);
break;
case BOARD_ID_PROTO_1:
case BOARD_ID_PROTO_3:
case BOARD_ID_PROTO_4:
case BOARD_ID_EVT:
gpio_set(EN_VDD_LCD, 1);
break;
default: /* unknown board */
return -1;
}
/* wait for 2ms */
mdelay(2);
/* Enable PP1800_LCDIO to panel */
gpio_set(EN_VDD18_LCD, 1);
/* wait for 1ms */
mdelay(1);
/* Set panel EN and RST signals */
gpio_set(LCD_EN, 1); /* enable */
/* wait for min 10ms */
mdelay(10);
gpio_set(LCD_RST_L, 1); /* clear reset */
/* wait for min 3ms */
mdelay(3);
return 0;
}
static const struct pad_config i2s1_pad[] = {
/* I2S1 */
PAD_CFG_SFIO(DAP2_SCLK, PINMUX_INPUT_ENABLE, I2S1),
PAD_CFG_SFIO(DAP2_FS, PINMUX_INPUT_ENABLE, I2S1),
PAD_CFG_SFIO(DAP2_DOUT, PINMUX_INPUT_ENABLE, I2S1),
PAD_CFG_SFIO(DAP2_DIN, PINMUX_INPUT_ENABLE | PINMUX_TRISTATE, I2S1),
/* codec MCLK via EXTPERIPH1 */
PAD_CFG_SFIO(DAP_MCLK1, PINMUX_PULL_NONE, EXTPERIPH1),
};
static const struct funit_cfg audio_funit[] = {
/* We need 1.5MHz for I2S1. So we use CLK_M */
FUNIT_CFG(I2S1, CLK_M, 1500, i2s1_pad, ARRAY_SIZE(i2s1_pad)),
};
static int configure_display_blocks(void)
{
/* set and enable panel related vdd */
if (enable_lcd_vdd())
return -1;
/* enable display related clocks */
configure_display_clocks();
return 0;
}
/* Audio init: clocks and enables/resets */
static void setup_audio(void)
{
/*
* External peripheral 1: audio codec (RT5677) uses 12MHz CLK1
* NOTE: We can't use a funits struct/call here because EXTPERIPH1/2/3
* don't have BASE regs or CAR RST/ENA bits. Also, the mux setting for
* EXTPERIPH1/DAP_MCLK1 is rolled into the I2S1 padcfg.
*/
clock_configure_source(extperiph1, CLK_M, 12000);
soc_configure_funits(audio_funit, ARRAY_SIZE(audio_funit));
clock_external_output(1); /* For external RT5677 audio codec. */
/*
* Confirmed by NVIDIA hardware team, we need to take ALL audio devices
* connected to AHUB (AUDIO, APBIF, I2S, DAM, AMX, ADX, SPDIF, AFC) out
* of reset and clock-enabled, otherwise reading AHUB devices (in our
* case, I2S/APBIF/AUDIO<XBAR>) will hang.
*/
clock_enable_audio();
}
#define AD4567_DEV 0x34
#define PWR_CTL 0
#define DAC_CTL 2
#define SPWDN (1 << 0)
#define DAC_MUTE (1 << 6)
#define DAC_FS (0x7 << 0)
#define SR_32K_48KHZ 0x2
static void enable_ad4567_spkr_amp(void)
{
uint8_t reg_byte;
if (board_id() >= BOARD_ID_PROTO_3)
return;
/*
* I2C6, device 0x34 is an AD4567 speaker amp on P0/P1.
* It needs to have a couple of regs tweaked to turn it on
* so it can provide audio output to the mono speaker on P0/P1.
*/
i2c_readb(I2C6_BUS, AD4567_DEV, PWR_CTL, &reg_byte);
reg_byte &= ~SPWDN; // power up amp
i2c_writeb(I2C6_BUS, AD4567_DEV, PWR_CTL, reg_byte);
/* The next 2 settings are defaults, but set them anyway */
i2c_readb(I2C6_BUS, AD4567_DEV, DAC_CTL, &reg_byte);
reg_byte &= ~DAC_MUTE; // unmute DAC (default)
reg_byte &= ~DAC_FS; // mask sample rate bits
reg_byte |= SR_32K_48KHZ; // set 32K-48KHz sample rate (default)
i2c_writeb(I2C6_BUS, AD4567_DEV, DAC_CTL, reg_byte);
}
static void mainboard_init(device_t dev)
{
soc_configure_funits(funits, ARRAY_SIZE(funits));
/* I2C6 bus (audio, etc.) */
soc_configure_i2c6pad();
i2c_init(I2C6_BUS);
setup_audio();
/* Temp hack for P1 board: Enable speaker amp (powerup, etc.) */
enable_ad4567_spkr_amp();
fix_ec_sw_sync();
/* configure panel gpio pads */
soc_configure_pads(lcd_gpio_padcfgs, ARRAY_SIZE(lcd_gpio_padcfgs));
/* if panel needs to bringup */
if (display_init_required())
configure_display_blocks();
}
void display_startup(device_t dev)
{
dsi_display_startup(dev);
}
static void mainboard_enable(device_t dev)
{
dev->ops->init = &mainboard_init;
}
struct chip_operations mainboard_ops = {
.name = "rush_ryu",
.enable_dev = mainboard_enable,
};
#if IS_ENABLED(CONFIG_CHROMEOS)
void lb_board(struct lb_header *header)
{
lb_table_add_serialno_from_vpd(header);
}
#endif

14
src/mainboard/google/rush_ryu/memlayout.ld
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@@ -1,14 +0,0 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <soc/memlayout.ld>

86
src/mainboard/google/rush_ryu/pmic.c
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@@ -1,86 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2014 Google Inc.
* Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <console/console.h>
#include <delay.h>
#include <device/i2c.h>
#include <stdint.h>
#include <stdlib.h>
#include "pmic.h"
#include "reset.h"
#define PAGE_ADDR(reg) ((reg >> 8) & 0xff)
#define PAGE_OFFSET(reg) (reg & 0xff)
struct ti65913_init_reg {
u16 reg;
u8 val;
u8 delay;
};
static struct ti65913_init_reg init_list[] = {
//TODO(twarren@nvidia.com): Add slams back to defaults
// {TI65913_SMPS12_VOLTAGE, 0x38, 0},
// {TI65913_SMPS12_CTRL, 0x01, 1},
//etc.
};
int pmic_read_reg(unsigned bus, uint16_t reg, uint8_t *data)
{
if (i2c_readb(bus, PAGE_ADDR(reg), PAGE_OFFSET(reg), data)) {
printk(BIOS_ERR, "%s: page = 0x%02X, reg = 0x%02X failed!\n",
__func__, PAGE_ADDR(reg), PAGE_OFFSET(reg));
return -1;
}
return 0;
}
void pmic_write_reg(unsigned bus, uint16_t reg, uint8_t val, int delay)
{
if (i2c_writeb(bus, PAGE_ADDR(reg), PAGE_OFFSET(reg), val)) {
printk(BIOS_ERR, "%s: page = 0x%02X, reg = 0x%02X, "
"value = 0x%02X failed!\n",
__func__, PAGE_ADDR(reg), PAGE_OFFSET(reg), val);
/* Reset the SoC on any PMIC write error */
cpu_reset();
} else {
if (delay)
udelay(500);
}
}
static void pmic_slam_defaults(unsigned bus)
{
int i;
for (i = 0; i < ARRAY_SIZE(init_list); i++) {
struct ti65913_init_reg *reg = &init_list[i];
pmic_write_reg(bus, reg->reg, reg->val, reg->delay);
}
}
void pmic_init(unsigned bus)
{
/* Restore PMIC POR defaults, in case kernel changed 'em */
pmic_slam_defaults(bus);
/* A44: Set VDD_CPU to 1.0V. */
pmic_write_reg(bus, TI65913_SMPS12_VOLTAGE, 0x38, 0);
pmic_write_reg(bus, TI65913_SMPS12_CTRL, 0x01, 1);
printk(BIOS_DEBUG, "PMIC init done\n");
}

131
src/mainboard/google/rush_ryu/pmic.h
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@@ -1,131 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __MAINBOARD_GOOGLE_RUSH_RYU_PMIC_H__
#define __MAINBOARD_GOOGLE_RUSH_RYU_PMIC_H__
#include <stdint.h>
/* A44/Ryu has a TI 65913 PMIC on bus 4 (PWR_I2C) */
enum {
TI65913_I2C_ADDR_PAGE1 = 0x58,
TI65913_I2C_ADDR_PAGE2 = 0x59
};
enum {
/* Registers in PAGE1 */
TI65913_SMPS12_CTRL = (TI65913_I2C_ADDR_PAGE1 << 8) | 0x20,
TI65913_SMPS12_TSTEP,
TI65913_SMPS12_FORCE,
TI65913_SMPS12_VOLTAGE,
TI65913_SMPS3_CTRL,
TI65913_SMPS3_VOLTAGE = (TI65913_I2C_ADDR_PAGE1 << 8) | 0x27,
TI65913_SMPS45_CTRL = (TI65913_I2C_ADDR_PAGE1 << 8) | 0x28,
TI65913_SMPS45_TSTEP,
TI65913_SMPS45_FORCE,
TI65913_SMPS45_VOLTAGE,
TI65913_SMPS6_CTRL = (TI65913_I2C_ADDR_PAGE1 << 8) | 0x2C,
TI65913_SMPS6_TSTEP,
TI65913_SMPS6_FORCE,
TI65913_SMPS6_VOLTAGE,
TI65913_SMPS7_CTRL = (TI65913_I2C_ADDR_PAGE1 << 8) | 0x30,
TI65913_SMPS7_VOLTAGE = (TI65913_I2C_ADDR_PAGE1 << 8) | 0x33,
TI65913_SMPS8_CTRL = (TI65913_I2C_ADDR_PAGE1 << 8) | 0x34,
TI65913_SMPS8_TSTEP,
TI65913_SMPS8_FORCE,
TI65913_SMPS8_VOLTAGE,
TI65913_SMPS9_CTRL = (TI65913_I2C_ADDR_PAGE1 << 8) | 0x38,
TI65913_SMPS9_VOLTAGE = (TI65913_I2C_ADDR_PAGE1 << 8) | 0x3B,
TI65913_SMPS10_CTRL = (TI65913_I2C_ADDR_PAGE1 << 8) | 0x3C,
TI65913_SMPS10_STATUS = (TI65913_I2C_ADDR_PAGE1 << 8) | 0x3F,
TI65913_LDO1_CTRL = (TI65913_I2C_ADDR_PAGE1 << 8) | 0x50,
TI65913_LDO1_VOLTAGE,
TI65913_LDO2_CTRL,
TI65913_LDO2_VOLTAGE,
TI65913_LDO3_CTRL,
TI65913_LDO3_VOLTAGE,
TI65913_LDO4_CTRL,
TI65913_LDO4_VOLTAGE,
TI65913_LDO5_CTRL,
TI65913_LDO5_VOLTAGE,
TI65913_LDO6_CTRL,
TI65913_LDO6_VOLTAGE,
TI65913_LDO7_CTRL,
TI65913_LDO7_VOLTAGE,
TI65913_LDO8_CTRL,
TI65913_LDO8_VOLTAGE,
TI65913_LDO9_CTRL,
TI65913_LDO9_VOLTAGE,
TI65913_LDOLN_CTRL = (TI65913_I2C_ADDR_PAGE1 << 8) | 0x62,
TI65913_LDOLN_VOLTAGE,
TI65913_LDOUSB_CTRL,
TI65913_LDOUSB_VOLTAGE,
TI65913_LDO_CTRL = (TI65913_I2C_ADDR_PAGE1 << 8) | 0x6A,
TI65913_LDO_PD_CTRL1,
TI65913_LDO_PD_CTRL2,
TI65913_LDO_SHORT_STATUS1 = (TI65913_I2C_ADDR_PAGE1 << 8) | 0x6D,
TI65913_LDO_SHORT_STATUS2,
TI65913_CLK32KGAUDIO_CTRL = (TI65913_I2C_ADDR_PAGE1 << 8) | 0xD5,
TI65913_PAD2 = (TI65913_I2C_ADDR_PAGE1 << 8) | 0xFB,
/* Registers in PAGE2 */
TI65913_GPIO_DATA_IN = (TI65913_I2C_ADDR_PAGE2 << 8) | 0x80,
TI65913_GPIO_DATA_DIR,
TI65913_GPIO_DATA_OUT,
};
/* Voltage selection */
enum {
VSEL_1200 = 0x07,
};
/*
* TI65913_LDO5_CTRL
* TI65913_CLK32KGAUDIO_CTRL
*/
#define TI65913_MODE_ACTIVE_ON (1 << 0)
/*
* select PRIMARY or SECONDARY function on PAD2
*/
#define PAD2_GPIO_6_PRIMARY(data) \
((data) & ~(1 << 3)) /* clear bit 3 */
#define PAD2_GPIO_5_SEC_CLK32KGAUDIO(data) \
(((data) & ~(0x03 << 1)) | (0x01 << 1)) /* bit 2:1 = 01 */
/* TI65913_GPIO_DATA_DIR */
#define TI65913_GPIO_6_OUTPUT (1 << 6)
/* TI65913_GPIO_DATA_OUT */
#define TI65913_GPIO_6_HIGH (1 << 6)
int pmic_read_reg(unsigned bus, uint16_t reg, uint8_t *data);
void pmic_write_reg(unsigned bus, uint16_t reg, uint8_t val, int delay);
void pmic_init(unsigned bus);
#endif /* __MAINBOARD_GOOGLE_RUSH_RYU_PMIC_H__ */

25
src/mainboard/google/rush_ryu/reset.c
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@@ -1,25 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <arch/io.h>
#include <reset.h>
#include "gpio.h"
void hard_reset(void)
{
gpio_output(AP_SYS_RESET_L, 0);
while(1);
}

115
src/mainboard/google/rush_ryu/romstage.c
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@@ -1,115 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <delay.h>
#include <soc/addressmap.h>
#include <device/i2c.h>
#include <soc/clock.h>
#include <soc/funitcfg.h>
#include <soc/nvidia/tegra/i2c.h>
#include <soc/padconfig.h>
#include <soc/romstage.h>
#include "gpio.h"
#include "pmic.h"
static const struct pad_config padcfgs[] = {
/* AP_SYS_RESET_L */
PAD_CFG_GPIO_OUT1(GPIO_PI5, PINMUX_PULL_UP),
/* WP_L */
PAD_CFG_GPIO_INPUT(KB_ROW1, PINMUX_PULL_NONE),
/* MODEM_RESET */
PAD_CFG_GPIO_OUT0(KB_ROW11, PINMUX_PULL_DOWN),
/* MODEM_PWR_ON */
PAD_CFG_GPIO_OUT0(KB_ROW12, PINMUX_PULL_DOWN),
/* MDM_DET - expected to be pulled down by LTE modem */
PAD_CFG_GPIO_INPUT(GPIO_PV1, PINMUX_PULL_UP),
/* Power Button - active high / low depending on board id */
PAD_CFG_GPIO_INPUT(KB_COL0, PINMUX_PULL_UP),
/* BTN_AP_VOLD_L - active low */
PAD_CFG_GPIO_INPUT(KB_COL6, PINMUX_PULL_UP),
/* BTN_AP_VOLU_L - active low */
PAD_CFG_GPIO_INPUT(KB_COL7, PINMUX_PULL_UP),
};
static const struct pad_config tpm_pads[] = {
PAD_CFG_SFIO(CAM_I2C_SCL, PINMUX_INPUT_ENABLE, I2C3),
PAD_CFG_SFIO(CAM_I2C_SDA, PINMUX_INPUT_ENABLE, I2C3),
};
static const struct pad_config ec_i2c_pads[] = {
PAD_CFG_SFIO(GEN2_I2C_SCL, PINMUX_OPEN_DRAIN|PINMUX_INPUT_ENABLE, I2C2),
PAD_CFG_SFIO(GEN2_I2C_SDA, PINMUX_OPEN_DRAIN|PINMUX_INPUT_ENABLE, I2C2),
};
static const struct funit_cfg funits[] = {
/* TPM on I2C3 @ 400kHz */
FUNIT_CFG(I2C3, PLLP, 400, tpm_pads, ARRAY_SIZE(tpm_pads)),
/* EC on I2C2 - pulled to 3.3V @ 100kHz */
FUNIT_CFG(I2C2, PLLP, 100, ec_i2c_pads, ARRAY_SIZE(ec_i2c_pads)),
};
static void lte_modem_init(void)
{
int mdm_det;
uint8_t data;
/* A LTE modem is present if MDM_DET is pulled down by the modem */
mdm_det = gpio_get(MDM_DET);
if (mdm_det == 1)
return;
printk(BIOS_DEBUG, "Found LTE modem\n");
/* Enable PMIC CLK32KGAUDIO to drive CLK_MDM_32K */
pmic_read_reg(I2CPWR_BUS, TI65913_PAD2, &data);
pmic_write_reg(I2CPWR_BUS, TI65913_PAD2,
PAD2_GPIO_5_SEC_CLK32KGAUDIO(data), 0);
pmic_write_reg(I2CPWR_BUS, TI65913_CLK32KGAUDIO_CTRL,
TI65913_MODE_ACTIVE_ON, 0);
/* FULL_CARD_POWER_OFF# (A44: MODEM_PWR_ON) and RESET#
* (A44: MODEM_RESET) of the LTE modem are actively low and initially
* pulled down by the pad config. To properly enable the LTE modem,
* de-assert FULL_CARD_POWER_OFF#, wait for at least 10ms, and then
* de-assert RESET#.
*/
gpio_output(MODEM_PWR_ON, 1);
udelay(15000);
gpio_output(MODEM_RESET, 1);
}
void romstage_mainboard_init(void)
{
/* Bring up controller interfaces for ramstage loading. */
soc_configure_funits(funits, ARRAY_SIZE(funits));
soc_configure_pads(padcfgs, ARRAY_SIZE(padcfgs));
/* TPM */
i2c_init(I2C3_BUS);
/* EC */
i2c_init(I2C2_BUS);
lte_modem_init();
}
void mainboard_configure_pmc(void)
{
}
void mainboard_enable_vdd_cpu(void)
{
/* VDD_CPU is already enabled in bootblock. */
}

45
src/mainboard/google/rush_ryu/sdram_configs.c
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@@ -1,45 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <console/console.h>
#include <soc/sdram_configs.h>
#include <stdlib.h>
static const struct sdram_params sdram_configs[] = {
#include "bct/sdram-samsung-4GB-924.inc" /* ram_code = 00 */
#include "bct/sdram-hynix-4GB-924.inc" /* ram_code = 01 */
#include "bct/sdram-micron-4GB-924.inc" /* ram_code = 10 */
#include "bct/sdram-micron-4GB-528.inc" /* ram_code = 11 */
};
const struct sdram_params *get_sdram_config()
{
uint32_t ramcode = sdram_get_ram_code();
/*
* If we need to apply some special hacks to RAMCODE mapping (ex, by
* board_id), do that now.
*/
ramcode &= 0x3; /* Only bits 1:0 used on Ryu */
printk(BIOS_SPEW, "%s: RAMCODE=%d\n", __func__, ramcode);
if (ramcode >= ARRAY_SIZE(sdram_configs) ||
sdram_configs[ramcode].MemoryType == NvBootMemoryType_Unused) {
die("Invalid RAMCODE.");
}
return &sdram_configs[ramcode];
}

49
src/mainboard/google/rush_ryu/verstage.c
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@@ -1,49 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <soc/addressmap.h>
#include <soc/funitcfg.h>
#include <soc/padconfig.h>
#include <soc/verstage.h>
#include <soc/nvidia/tegra/i2c.h>
#include "gpio.h"
#include "pmic.h"
static const struct pad_config tpm_pads[] = {
PAD_CFG_SFIO(CAM_I2C_SCL, PINMUX_INPUT_ENABLE, I2C3),
PAD_CFG_SFIO(CAM_I2C_SDA, PINMUX_INPUT_ENABLE, I2C3),
};
static const struct pad_config ec_i2c_pads[] = {
PAD_CFG_SFIO(GEN2_I2C_SCL, PINMUX_OPEN_DRAIN|PINMUX_INPUT_ENABLE, I2C2),
PAD_CFG_SFIO(GEN2_I2C_SDA, PINMUX_OPEN_DRAIN|PINMUX_INPUT_ENABLE, I2C2),
};
static const struct funit_cfg funits[] = {
/* TPM on I2C3 @ 400kHz */
FUNIT_CFG(I2C3, PLLP, 400, tpm_pads, ARRAY_SIZE(tpm_pads)),
/* EC on I2C2 - pulled to 3.3V @ 100kHz */
FUNIT_CFG(I2C2, PLLP, 100, ec_i2c_pads, ARRAY_SIZE(ec_i2c_pads)),
};
void verstage_mainboard_init(void)
{
soc_configure_funits(funits, ARRAY_SIZE(funits));
/* TPM */
i2c_init(I2C3_BUS);
/* EC */
i2c_init(I2C2_BUS);
}