-Â get rid of ASM_CONSOLE_LOGLEVEL except in two assembler files.
- start naming all versions of post code output "post_code()" Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5344 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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committed by
Stefan Reinauer
parent
84b685af5f
commit
0c781b2694
@@ -17,6 +17,10 @@
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef ASM_CONSOLE_LOGLEVEL
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#define ASM_CONSOLE_LOGLEVEL CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
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#endif
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#define LX_STACK_BASE CONFIG_DCACHE_RAM_BASE /* this is where the DCache will be mapped and be used as stack, It would be cool if it was the same base as coreboot normal stack */
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#define LX_STACK_END LX_STACK_BASE+(CONFIG_DCACHE_RAM_SIZE-1)
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@@ -206,7 +210,7 @@ __main:
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* isn\'t really that big we just copy/clear using bytes, not
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* double words.
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*/
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intel_chip_post_macro(0x11) /* post 11 */
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post_code(0x11) /* post 11 */
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cld /* clear direction flag */
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@@ -220,7 +224,7 @@ __main:
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call cbfs_and_run_core
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.Lhlt:
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intel_chip_post_macro(0xee) /* post fail ee */
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post_code(0xee) /* post fail ee */
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hlt
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jmp .Lhlt
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@@ -20,7 +20,6 @@
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#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
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#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
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#define post_code(x) intel_chip_post_macro(x)
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#include <cpu/x86/mtrr.h>
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#include <cpu/amd/mtrr.h>
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@@ -20,7 +20,6 @@
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#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
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#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
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#define post_code(x) intel_chip_post_macro(x)
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#include <cpu/x86/mtrr.h>
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#include <cpu/amd/mtrr.h>
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@@ -20,7 +20,6 @@
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#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
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#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
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#define post_code(x) intel_chip_post_macro(x)
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#include <cpu/x86/mtrr.h>
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#include <cpu/amd/mtrr.h>
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@@ -50,7 +50,7 @@ __protected_start:
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/* Save the BIST value */
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movl %eax, %ebp
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intel_chip_post_macro(0x10) /* post 10 */
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post_code(0x10) /* post 10 */
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movw $ROM_DATA_SEG, %ax
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movw %ax, %ds
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