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- get rid of ASM_CONSOLE_LOGLEVEL except in two assembler files.

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- start naming all versions of post code output "post_code()"

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5344 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer
2010-04-01 09:50:32 +00:00
committed by Stefan Reinauer
parent 84b685af5f
commit 0c781b2694
44 changed files with 76 additions and 349 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
src/cpu/amd/model_lx/cache_as_ram.inc
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@@ -17,6 +17,10 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef ASM_CONSOLE_LOGLEVEL
#define ASM_CONSOLE_LOGLEVEL CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
#endif
#define LX_STACK_BASE CONFIG_DCACHE_RAM_BASE /* this is where the DCache will be mapped and be used as stack, It would be cool if it was the same base as coreboot normal stack */
#define LX_STACK_END LX_STACK_BASE+(CONFIG_DCACHE_RAM_SIZE-1)
@@ -206,7 +210,7 @@ __main:
* isn\'t really that big we just copy/clear using bytes, not
* double words.
*/
intel_chip_post_macro(0x11) /* post 11 */
post_code(0x11) /* post 11 */
cld /* clear direction flag */
@@ -220,7 +224,7 @@ __main:
call cbfs_and_run_core
.Lhlt:
intel_chip_post_macro(0xee) /* post fail ee */
post_code(0xee) /* post fail ee */
hlt
jmp .Lhlt

1
src/cpu/intel/model_106cx/cache_as_ram.inc
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@@ -20,7 +20,6 @@
#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
#define post_code(x) intel_chip_post_macro(x)
#include <cpu/x86/mtrr.h>
#include <cpu/amd/mtrr.h>

1
src/cpu/intel/model_6ex/cache_as_ram.inc
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@@ -20,7 +20,6 @@
#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
#define post_code(x) intel_chip_post_macro(x)
#include <cpu/x86/mtrr.h>
#include <cpu/amd/mtrr.h>

1
src/cpu/intel/model_6fx/cache_as_ram.inc
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@@ -20,7 +20,6 @@
#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
#define post_code(x) intel_chip_post_macro(x)
#include <cpu/x86/mtrr.h>
#include <cpu/amd/mtrr.h>

2
src/cpu/x86/32bit/entry32.inc
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@@ -50,7 +50,7 @@ __protected_start:
/* Save the BIST value */
movl %eax, %ebp
intel_chip_post_macro(0x10) /* post 10 */
post_code(0x10) /* post 10 */
movw $ROM_DATA_SEG, %ax
movw %ax, %ds