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soc/intel/elkhartlake: Update FSP-S FuSa related settings

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Further add initial Silicon UPD settings for FuSa
(Functional Safety). Disable all by default, due to FSP binary
enable all by default.

Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: I88264ba3e3f9f54ad949c55b230082d1fa289fa4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55342
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Lean Sheng Tan
2021-06-08 23:41:15 -07:00
committed by Patrick Georgi
parent dea42e011a
commit 0cdcdc736e
2 changed files with 11 additions and 0 deletions
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3
src/soc/intel/elkhartlake/chip.h
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@@ -68,6 +68,9 @@ struct soc_intel_elkhartlake_config {
/* Memory Thermal Throttling: Enable - Default (0) / Disable (1) */
bool MemoryThermalThrottlingDisable;
/* FuSa (Functional Safety): Disable - Default (0) / Enable (1) */
bool FuSaEnable;
/* System Agent dynamic frequency support.
* When enabled memory will be trained at different frequencies.
* 0:Disabled, 1:FixedPoint0(low), 2:FixedPoint1(mid), 3:FixedPoint2

8
src/soc/intel/elkhartlake/fsp_params.c
View File

@@ -344,6 +344,14 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->PchFivrVccinAuxOffToHighCurModeVolTranTime = 0x0096;
params->FivrSpreadSpectrum = 0xF;
/* FuSa (Functional Safety) config */
if (!config->FuSaEnable) {
params->DisplayFusaConfigEnable = 0;
params->GraphicFusaConfigEnable = 0;
params->OpioFusaConfigEnable = 0;
params->PsfFusaConfigEnable = 0;
}
/* Override/Fill FSP Silicon Param for mainboard */
mainboard_silicon_init_params(params);
}