purism/librem_bdl: Add support for Librem 15 v2

Adding new librem_bdl variant for the Librem 15 v2, which is very similar
to Librem 13 v1, with the following differences:
- SATA ports 0 and 1 instead of 0 and 3
- SATA DTLE IOBP value is 7 instead of 9 for port 0
- There is no LAN device
- There are two SODIMM slots, and DQs are interleaved
- USB ports are different

Change-Id: Ifaca382a540d085e6c919daa992a0fbd52643a5b
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/26184
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

src/mainboard/purism/librem_bdl/Kconfig

@@ -13,10 +13,12 @@ if BOARD_PURISM_BASEBOARD_LIBREM_BDL
 config VARIANT_DIR
 	string
 	default "librem13v1" if BOARD_PURISM_LIBREM13_V1
+	default "librem15v2" if BOARD_PURISM_LIBREM15_V2
 
 config DEVICETREE
 	string
 	default "variants/librem13v1/devicetree.cb" if BOARD_PURISM_LIBREM13_V1
+	default "variants/librem15v2/devicetree.cb" if BOARD_PURISM_LIBREM15_V2
 
 config DRIVERS_PS2_KEYBOARD
 	def_bool y
@@ -54,14 +56,17 @@ config MAINBOARD_VENDOR
 config MAINBOARD_PART_NUMBER
 	string
 	default "Librem 13 v1" if BOARD_PURISM_LIBREM13_V1
+	default "Librem 15 v2" if BOARD_PURISM_LIBREM15_V2
 
 config MAINBOARD_FAMILY
 	string
 	default "Librem 13" if BOARD_PURISM_LIBREM13_V1
+	default "Librem 15" if BOARD_PURISM_LIBREM15_V2
 
 config MAINBOARD_VERSION
 	string
 	default "1.0" if BOARD_PURISM_LIBREM13_V1
+	default "2.0" if BOARD_PURISM_LIBREM15_V2
 
 config MAX_CPUS
 	int
@@ -79,6 +84,8 @@ config PRE_GRAPHICS_DELAY
 
 config VGA_BIOS_ID
 	string
-	default "8086,1616"
+	default "8086,1616" if BOARD_PURISM_LIBREM13_V1
+	default "8086,162b" if BOARD_PURISM_LIBREM15_V2
+
 
 endif

src/mainboard/purism/librem_bdl/Kconfig.name

@@ -1,3 +1,7 @@
 config BOARD_PURISM_LIBREM13_V1
 	bool "Librem 13 v1"
 	select BOARD_PURISM_BASEBOARD_LIBREM_BDL
+
+config BOARD_PURISM_LIBREM15_V2
+	bool "Librem 15 v2"
+	select BOARD_PURISM_BASEBOARD_LIBREM_BDL

src/mainboard/purism/librem_bdl/variants/librem15v2/board_info.txt

@@ -0,0 +1,9 @@
+Category: laptop
+Vendor name: Purism
+Board name: Librem 15 v2
+Board URL: https://web.archive.org/web/20160529052744/https://puri.sm/librem-15/
+ROM package: SOIC8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
+Release year: 2015

src/mainboard/purism/librem_bdl/variants/librem15v2/devicetree.cb

@@ -0,0 +1,75 @@
+chip soc/intel/broadwell
+
+	# Enable eDP Hotplug with 6ms pulse
+	register "gpu_dp_d_hotplug" = "0x06"
+
+	# Enable DDI1 Hotplug with 6ms pulse
+	register "gpu_dp_b_hotplug" = "0x06"
+
+	# Set backlight PWM values for eDP
+	register "gpu_cpu_backlight" = "0x00000200"
+	register "gpu_pch_backlight" = "0x04000200"
+
+	# Enable Panel and configure power delays
+	register "gpu_panel_port_select" = "1"			# eDP
+	register "gpu_panel_power_cycle_delay" = "6"		# 500ms
+	register "gpu_panel_power_up_delay" = "2000"		# 200ms
+	register "gpu_panel_power_down_delay" = "500"		# 50ms
+	register "gpu_panel_power_backlight_on_delay" = "2000"	# 200ms
+	register "gpu_panel_power_backlight_off_delay" = "2000"	# 200ms
+
+	# EC host command ranges are in 0x380-0x383 & 0x80-0x8f
+	register "gen1_dec" = "0x00000381"
+	register "gen2_dec" = "0x000c0081"
+
+	# Port 0 is HDD
+	# Port 1 is M.2 NGFF
+	register "sata_port_map" = "0x3"
+
+	# Port tuning for link stability
+	register "sata_port0_gen3_dtle" = "7"
+	register "sata_port1_gen3_dtle" = "9"
+	register "sata_port2_gen3_dtle" = "9"
+	register "sata_port3_gen3_dtle" = "7"
+
+	device cpu_cluster 0 on
+		device lapic 0 on end
+	end
+	device domain 0 on
+		device pci 00.0 on  end # host bridge
+		device pci 02.0 on  end # vga controller
+		device pci 03.0 on  end # mini-hd audio
+		device pci 13.0 off end # Smart Sound Audio DSP
+		device pci 14.0 on  end # USB3 XHCI
+		device pci 15.0 off end # Serial I/O DMA
+		device pci 15.1 off end # I2C0
+		device pci 15.2 off end # I2C1
+		device pci 15.3 off end # GSPI0
+		device pci 15.4 off end # GSPI1
+		device pci 15.5 off end # UART0
+		device pci 15.6 off end # UART1
+		device pci 16.0 off end # Management Engine Interface 1
+		device pci 16.1 off end # Management Engine Interface 2
+		device pci 16.2 off end # Management Engine IDE-R
+		device pci 16.3 off end # Management Engine KT
+		device pci 17.0 off end # SDIO
+		device pci 19.0 off end # GbE
+		device pci 1b.0 on  end # High Definition Audio
+		device pci 1c.0 on  end # PCIe Port #1
+		device pci 1c.1 off end # PCIe Port #2
+		device pci 1c.2 off end # PCIe Port #3 - LAN
+		device pci 1c.3 on  end # PCIe Port #4 - WiFi
+		device pci 1c.4 on  end # PCIe Port #5
+		device pci 1c.5 on  end # PCIe Port #6 - M.2 NVMe
+		device pci 1d.0 on  end # USB2 EHCI
+		device pci 1e.0 off end # PCI bridge
+		device pci 1f.0 on
+			chip ec/purism/librem
+				device pnp 0c09.0 on end
+			end
+		end # LPC bridge
+		device pci 1f.2 on  end # SATA Controller
+		device pci 1f.3 on  end # SMBus
+		device pci 1f.6 off end # Thermal
+	end
+end

src/mainboard/purism/librem_bdl/variants/librem15v2/pei_data.c

@@ -0,0 +1,64 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/pei_data.h>
+#include <soc/pei_wrapper.h>
+
+void mainboard_fill_pei_data(struct pei_data *pei_data)
+{
+	pei_data->ec_present = 1;
+	pei_data->dq_pins_interleaved = 1;
+
+	/* One DIMM slot */
+	pei_data->dimm_channel0_disabled = 2;
+	pei_data->dimm_channel1_disabled = 2;
+
+	pei_data->spd_addresses[0] = 0xa0;
+	pei_data->spd_addresses[2] = 0xa4;
+
+	/* P1: Right Side Port (USB2) */
+	pei_data_usb2_port(pei_data, 0, 0x0080, 1, USB_OC_PIN_SKIP,
+			   USB_PORT_BACK_PANEL);
+	/* P2: Right Side Port (USB2) */
+	pei_data_usb2_port(pei_data, 1, 0x0080, 1, USB_OC_PIN_SKIP,
+			   USB_PORT_BACK_PANEL);
+	/* P3: Left Side Port (USB2 only) */
+	pei_data_usb2_port(pei_data, 2, 0x0080, 1, USB_OC_PIN_SKIP,
+			   USB_PORT_BACK_PANEL);
+	/* P4: Left Side Port (USB2 only) */
+	pei_data_usb2_port(pei_data, 3, 0x0080, 1, USB_OC_PIN_SKIP,
+			   USB_PORT_BACK_PANEL);
+	/* P5: Empty */
+	pei_data_usb2_port(pei_data, 4, 0x0080, 0, USB_OC_PIN_SKIP,
+			   USB_PORT_BACK_PANEL);
+	/* P6: Bluetooth */
+	pei_data_usb2_port(pei_data, 5, 0x0080, 1, USB_OC_PIN_SKIP,
+			   USB_PORT_SKIP);
+	/* P7: Camera */
+	pei_data_usb2_port(pei_data, 6, 0x0080, 1, USB_OC_PIN_SKIP,
+			   USB_PORT_SKIP);
+	/* P8: SD Card */
+	pei_data_usb2_port(pei_data, 7, 0x0080, 1, USB_OC_PIN_SKIP,
+			   USB_PORT_BACK_PANEL);
+
+	/* P1: Right Side Port (USB3) */
+	pei_data_usb3_port(pei_data, 0, 1, USB_OC_PIN_SKIP, 0);
+	/* P2: Right Side Port (USB3) */
+	pei_data_usb3_port(pei_data, 1, 1, USB_OC_PIN_SKIP, 0);
+	/* P3: Empty */
+	pei_data_usb3_port(pei_data, 2, 0, USB_OC_PIN_SKIP, 0);
+	/* P4: Empty */
+	pei_data_usb3_port(pei_data, 3, 0, USB_OC_PIN_SKIP, 0);
+}