soc/amd/picasso/romstage: factor out chipset state saving functionality

Since Cezanne needs the exact same code, move it to the common directory
and add a Kconfig option to add this functionality to the build.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I04c4295071a3df7afcb4dfd5435b11fb0bf6963f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52272
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Raul Rangel <rrangel@chromium.org>

src/soc/amd/picasso/Kconfig

@@ -40,6 +40,8 @@ config CPU_SPECIFIC_OPTIONS
 	select SOC_AMD_COMMON_BLOCK_LPC
 	select SOC_AMD_COMMON_BLOCK_NONCAR
 	select SOC_AMD_COMMON_BLOCK_PCI
+	select SOC_AMD_COMMON_BLOCK_PM
+	select SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE
 	select SOC_AMD_COMMON_BLOCK_PSP_GEN2
 	select SOC_AMD_COMMON_BLOCK_SATA
 	select SOC_AMD_COMMON_BLOCK_SMBUS