Synchronize rdtsc instructions

The CPU can arbitrarily reorder calls to rdtsc, significantly
reducing the precision of timing using the CPUs time stamp counter.
Unfortunately the method of synchronizing rdtsc is different
on AMD and Intel CPUs. There is a generic method, using the cpuid
instruction, but that uses up a lot of registers, and is very slow.
Hence, use the correct lfence/mfence instructions (for CPUs that
we know support it)

Change-Id: I17ecb48d283f38f23148c13159aceda704c64ea5
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1422
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)

src/cpu/intel/model_1067x/Kconfig

@@ -2,3 +2,4 @@ config CPU_INTEL_MODEL_1067X
 	bool
 	select SMP
 	select SSE2
+	select TSC_SYNC_MFENCE

src/cpu/intel/model_106cx/Kconfig

@@ -4,9 +4,9 @@ config CPU_INTEL_MODEL_106CX
 	select SSE2
 	select UDELAY_LAPIC
 	select AP_IN_SIPI_WAIT
+	select TSC_SYNC_MFENCE
 
 config CPU_ADDR_BITS
 	int
 	default 32
 
-

src/cpu/intel/model_206ax/Kconfig

@@ -14,6 +14,7 @@ config CPU_SPECIFIC_OPTIONS
 	select SMM_TSEG
 	select MICROCODE_IN_CBFS
 	#select AP_IN_SIPI_WAIT
+	select TSC_SYNC_MFENCE
 
 config BOOTBLOCK_CPU_INIT
 	string

src/cpu/intel/model_6ex/Kconfig

@@ -4,3 +4,4 @@ config CPU_INTEL_MODEL_6EX
 	select SSE2
 	select UDELAY_LAPIC
 	select AP_IN_SIPI_WAIT
+	select TSC_SYNC_MFENCE

src/cpu/intel/model_6fx/Kconfig

@@ -4,3 +4,4 @@ config CPU_INTEL_MODEL_6FX
 	select SSE2
 	select UDELAY_LAPIC
 	select AP_IN_SIPI_WAIT
+	select TSC_SYNC_MFENCE