Synchronize rdtsc instructions
The CPU can arbitrarily reorder calls to rdtsc, significantly reducing the precision of timing using the CPUs time stamp counter. Unfortunately the method of synchronizing rdtsc is different on AMD and Intel CPUs. There is a generic method, using the cpuid instruction, but that uses up a lot of registers, and is very slow. Hence, use the correct lfence/mfence instructions (for CPUs that we know support it) Change-Id: I17ecb48d283f38f23148c13159aceda704c64ea5 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1422 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
This commit is contained in:
committed by
Stefan Reinauer
parent
4c29d7f27d
commit
0db6820b10
@@ -23,6 +23,22 @@ config TSC_CALIBRATE_WITH_IO
|
||||
bool
|
||||
default n
|
||||
|
||||
config TSC_SYNC_LFENCE
|
||||
bool
|
||||
default n
|
||||
help
|
||||
The CPU driver should select this if the CPU needs
|
||||
to execute an lfence instruction in order to synchronize
|
||||
rdtsc. This is true for all modern AMD CPUs.
|
||||
|
||||
config TSC_SYNC_MFENCE
|
||||
bool
|
||||
default n
|
||||
help
|
||||
The CPU driver should select this if the CPU needs
|
||||
to execute an mfence instruction in order to synchronize
|
||||
rdtsc. This is true for all modern Intel CPUs.
|
||||
|
||||
config XIP_ROM_SIZE
|
||||
hex
|
||||
default ROM_SIZE if ROMCC
|
||||
|
Reference in New Issue
Block a user