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Synchronize rdtsc instructions

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The CPU can arbitrarily reorder calls to rdtsc, significantly
reducing the precision of timing using the CPUs time stamp counter.
Unfortunately the method of synchronizing rdtsc is different
on AMD and Intel CPUs. There is a generic method, using the cpuid
instruction, but that uses up a lot of registers, and is very slow.
Hence, use the correct lfence/mfence instructions (for CPUs that
we know support it)

Change-Id: I17ecb48d283f38f23148c13159aceda704c64ea5
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1422
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
This commit is contained in:
Stefan Reinauer
2012-08-07 14:44:51 -07:00
committed by Stefan Reinauer
parent 4c29d7f27d
commit 0db6820b10
10 changed files with 40 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

19
src/include/cpu/x86/tsc.h
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@ -1,6 +1,14 @@
#ifndef CPU_X86_TSC_H
#define CPU_X86_TSC_H
#if CONFIG_TSC_SYNC_MFENCE
#define TSC_SYNC "mfence\n"
#elif CONFIG_TSC_SYNC_LFENCE
#define TSC_SYNC "lfence\n"
#else
#define TSC_SYNC
#endif
struct tsc_struct {
unsigned lo;
unsigned hi;
@ -10,10 +18,11 @@ typedef struct tsc_struct tsc_t;
static inline tsc_t rdtsc(void)
{
tsc_t res;
__asm__ __volatile__ (
asm volatile (
TSC_SYNC
"rdtsc"
: "=a" (res.lo), "=d"(res.hi) /* outputs */
);
);
return res;
}
@ -22,7 +31,11 @@ static inline tsc_t rdtsc(void)
static inline unsigned long long rdtscll(void)
{
unsigned long long val;
asm volatile ("rdtsc" : "=A" (val));
asm volatile (
TSC_SYNC
"rdtsc"
: "=A" (val)
);
return val;
}
#endif