mb/starlabs/starbook/rpl: Merge and alphabetise FSP UPDs
Change-Id: I3c4a963b233f549c7a76c76333af87c887550ac3 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83622 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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chip soc/intel/alderlake
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# FSP Memory
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register "enable_c6dram" = "1"
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# FSP UPDs
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register "disable_dynamic_tccold_handshake" = "true"
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register "eist_enable" = "true"
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register "enable_c1e" = "true"
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register "enable_c6dram" = "true"
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register "sagv" = "SaGv_Enabled"
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# FSP Silicon
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register "eist_enable" = "1"
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register "enable_c1e" = "1"
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register "disable_dynamic_tccold_handshake" = "1"
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# Serial I/O
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register "serial_io_i2c_mode" = "{
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[PchSerialIoIndexI2C0] = PchSerialIoPci,
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