sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

mb/starlabs/starbook/rpl: Merge and alphabetise FSP UPDs

Browse Source 
Change-Id: I3c4a963b233f549c7a76c76333af87c887550ac3
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83622
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This commit is contained in:
Sean Rhodes
2024-07-23 20:38:06 +01:00
committed by Felix Held
parent e4592e4996
commit 0dba005f04
1 changed files with 15 additions and 18 deletions
Download Patch File Download Diff File Expand all files Collapse all files

13
src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb
View File

@@ -1,14 +1,11 @@
chip soc/intel/alderlake
# FSP Memory
register "enable_c6dram" = "1"
# FSP UPDs
register "disable_dynamic_tccold_handshake" = "true"
register "eist_enable" = "true"
register "enable_c1e" = "true"
register "enable_c6dram" = "true"
register "sagv" = "SaGv_Enabled"
# FSP Silicon
register "eist_enable" = "1"
register "enable_c1e" = "1"
register "disable_dynamic_tccold_handshake" = "1"
# Serial I/O
register "serial_io_i2c_mode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci,