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mb/starlabs/starbook/rpl: Merge and alphabetise FSP UPDs

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Change-Id: I3c4a963b233f549c7a76c76333af87c887550ac3
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83622
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This commit is contained in:
Sean Rhodes 2024-07-23 20:38:06 +01:00 committed by Felix Held
parent e4592e4996
commit 0dba005f04
1 changed files with 15 additions and 18 deletions
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33
src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb
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@ -1,33 +1,30 @@
chip soc/intel/alderlake
# FSP Memory
register "enable_c6dram" = "1"
register "sagv" = "SaGv_Enabled"
# FSP Silicon
register "eist_enable" = "1"
register "enable_c1e" = "1"
register "disable_dynamic_tccold_handshake" = "1"
# FSP UPDs
register "disable_dynamic_tccold_handshake" = "true"
register "eist_enable" = "true"
register "enable_c1e" = "true"
register "enable_c6dram" = "true"
register "sagv" = "SaGv_Enabled"
# Serial I/O
register "serial_io_i2c_mode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci,
[PchSerialIoIndexI2C0] = PchSerialIoPci,
}"
register "serial_io_uart_mode" = "{
[PchSerialIoIndexUART0] = PchSerialIoSkipInit,
[PchSerialIoIndexUART0] = PchSerialIoSkipInit,
}"
# Power
register "pch_slp_s3_min_assertion_width" = "2" # 50ms
register "pch_slp_s4_min_assertion_width" = "3" # 1s
register "pch_slp_sus_min_assertion_width" = "3" # 500ms
register "pch_slp_a_min_assertion_width" = "3" # 2s
register "pch_slp_s3_min_assertion_width" = "2" # 50ms
register "pch_slp_s4_min_assertion_width" = "3" # 1s
register "pch_slp_sus_min_assertion_width" = "3" # 500ms
register "pch_slp_a_min_assertion_width" = "3" # 2s
# PM Util
register "pmc_gpe0_dw0" = "GPP_B"
register "pmc_gpe0_dw1" = "GPP_C"
register "pmc_gpe0_dw2" = "GPP_E"
register "pmc_gpe0_dw0" = "GPP_B"
register "pmc_gpe0_dw1" = "GPP_C"
register "pmc_gpe0_dw2" = "GPP_E"
# Device Tree
device domain 0 on