sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

soc/intel/apollolake: Handle CAR sizes other than 1 MiB

Browse Source 
Since whole L2 (1MiB) is not used, it is possible to shrink CAR size
to 768 KiB. Since 768 KiB is not power of two, 2 MTRRs are used to
set it up. This is a part of CQOS enabling.

BUG=chrome-os-partner:51959

Change-Id: I56326a1790df202a0e428e092dd90286c58763c5
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/15453
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Andrey Petrov
2016-06-27 15:21:26 -07:00
committed by Martin Roth
parent 7c8d74c103
commit 0dde2917a5
2 changed files with 28 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/soc/intel/apollolake/Kconfig
View File

@@ -97,7 +97,7 @@ config DCACHE_RAM_BASE
config DCACHE_RAM_SIZE
hex "Length in bytes of cache-as-RAM"
default 0x100000
default 0xc0000
help
The size of the cache-as-ram region required during bootblock
and/or romstage.