sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

soc/amd/stoneyridge/acpi/sb_pci0_fch: report correct number of PCI buses

Browse Source 
This ports commit 8c28e51a16e1 ("soc/amd/picasso: fix host bridge bus
numbers") back to Stoneyridge so that the correct number of PCI buses
gets reported from PCI0's _CRS method. The MCFG ACPI table already had
the correct last bus number.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I40121ab0e0438281192b6a0bec8dbecdc1749379
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74804
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
This commit is contained in:
Felix Held 2023-04-26 16:04:44 +02:00
parent 4c98dfb4e3
commit 0de53be394
1 changed files with 5 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl
View File

@ -111,6 +111,11 @@ Method(_CRS, 0) {
Local0 -= TOM1 Local0 -= TOM1
MM1L = Local0 MM1L = Local0
CreateWordField(CRES, ^PSB0._MAX, BMAX)
CreateWordField(CRES, ^PSB0._LEN, BLEN)
BMAX = CONFIG_ECAM_MMCONF_BUS_NUMBER - 1
BLEN = CONFIG_ECAM_MMCONF_BUS_NUMBER
Return (CRES) /* note to change the Name buffer */ Return (CRES) /* note to change the Name buffer */
} /* end of Method(_SB.PCI0._CRS) */ } /* end of Method(_SB.PCI0._CRS) */