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AGESA vendorcode: Add ENABLE_MRC_CACHE option

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When selected, try to store and restore memory training
results from/to SPI flash. This change only pulls in
the required parts from vendorcode for the build.

Change-Id: I12880237be494c71e1d4836abd2d4b714ba87762
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21446
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Kyösti Mälkki
2017-09-01 19:23:35 +03:00
parent 6287a69530
commit 0e1ea279d0
2 changed files with 11 additions and 1 deletions
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4
src/vendorcode/amd/agesa/common/agesa-entry-cfg.h
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@ -24,7 +24,9 @@
#define AGESA_ENTRY_INIT_MID TRUE
#define AGESA_ENTRY_INIT_LATE TRUE
#define AGESA_ENTRY_INIT_S3SAVE IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
#define AGESA_ENTRY_INIT_S3SAVE \
(IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) || \
IS_ENABLED(CONFIG_ENABLE_MRC_CACHE))
#endif