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arch/x86: Drop romcc bootblock

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Change-Id: I79accbe1d5a554fea75fbd866995f385f718421a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37335
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Arthur Heymans
2019-11-28 16:09:28 +01:00
committed by Patrick Georgi
parent ba9b504ec5
commit 0e45b2875a
11 changed files with 0 additions and 367 deletions
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14
src/arch/x86/Kconfig
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@ -166,12 +166,6 @@ config BOOTBLOCK_DEBUG_SPINLOOP
Add a spin (JMP .) in bootblock_crt0.S during early bootblock to wait Add a spin (JMP .) in bootblock_crt0.S during early bootblock to wait
for a JTAG debugger to break into the execution sequence. for a JTAG debugger to break into the execution sequence.
config BOOTBLOCK_MAINBOARD_INIT
string
config BOOTBLOCK_NORTHBRIDGE_INIT
string
config BOOTBLOCK_RESETS config BOOTBLOCK_RESETS
string string
@ -184,9 +178,6 @@ config CMOS_DEFAULT_FILE
default "src/mainboard/$(MAINBOARDDIR)/cmos.default" default "src/mainboard/$(MAINBOARDDIR)/cmos.default"
depends on HAVE_CMOS_DEFAULT depends on HAVE_CMOS_DEFAULT
config BOOTBLOCK_SOUTHBRIDGE_INIT
string
config IOAPIC_INTERRUPTS_ON_FSB config IOAPIC_INTERRUPTS_ON_FSB
bool bool
default y if !IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS default y if !IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS
@ -256,11 +247,6 @@ config BOOTBLOCK_NORMAL
endchoice endchoice
config BOOTBLOCK_SOURCE
string
default "bootblock_simple.c" if BOOTBLOCK_SIMPLE
default "bootblock_normal.c" if BOOTBLOCK_NORMAL
config SKIP_MAX_REBOOT_CNT_CLEAR config SKIP_MAX_REBOOT_CNT_CLEAR
bool "Do not clear reboot count after successful boot" bool "Do not clear reboot count after successful boot"
depends on BOOTBLOCK_NORMAL depends on BOOTBLOCK_NORMAL

57
src/arch/x86/Makefile.inc
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@ -116,8 +116,6 @@ bootblock-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c
bootblock-y += id.S bootblock-y += id.S
$(call src-to-obj,bootblock,$(dir)/id.S): $(obj)/build.h $(call src-to-obj,bootblock,$(dir)/id.S): $(obj)/build.h
ifneq ($(CONFIG_ROMCC_BOOTBLOCK),y)
bootblock-y += bootblock_crt0.S bootblock-y += bootblock_crt0.S
ifeq ($(CONFIG_ARCH_BOOTBLOCK_X86_32),y) ifeq ($(CONFIG_ARCH_BOOTBLOCK_X86_32),y)
@ -128,59 +126,6 @@ endif
bootblock-$(CONFIG_ARCH_BOOTBLOCK_X86_32) += walkcbfs.S bootblock-$(CONFIG_ARCH_BOOTBLOCK_X86_32) += walkcbfs.S
else # ROMCC_BOOTBLOCK
# x86-specific linker flags
ifeq ($(CONFIG_ARCH_BOOTBLOCK_X86_32),y)
LDFLAGS_bootblock += -m elf_i386 --oformat elf32-i386
else
LDFLAGS_bootblock += -m elf_x86_64 --oformat elf64-x86-64
endif
# Add the assembly file that pulls in the rest of the dependencies in
# the right order. Make sure the auto generated bootblock.inc is a proper
# dependency. Make the same true for the linker sript.
bootblock-y += bootblock_romcc.S
bootblock-y += walkcbfs.S
$(call src-to-obj,bootblock,$(dir)/bootblock_romcc.S): $(objgenerated)/bootblock.inc
bootblock-y += bootblock.ld
$(call src-to-obj,bootblock,$(dir)/bootblock.ld): $(objgenerated)/bootblock.ld
bootblock_romccflags := -mcpu=i386 -O2 -D__BOOTBLOCK__
ifeq ($(CONFIG_SSE),y)
bootblock_romccflags := -mcpu=k7 -mno-mmx -msse -O2 -D__BOOTBLOCK__
endif
# This is a hack in case there are no per chipset linker files.
$(objgenerated)/empty: build-dirs
touch $@
$(objgenerated)/bootblock.ld: $$(filter-out $(call src-to-obj,bootblock,src/arch/x86/bootblock.ld), $$(filter %.ld,$$(bootblock-objs))) $(objgenerated)/empty
@printf " GEN $(subst $(obj)/,,$(@))\n"
cat $^ >> $@.tmp
mv $@.tmp $@
-include $(objgenerated)/bootblock.inc.d
$(objgenerated)/bootblock.inc: $(src)/arch/x86/$(subst ",,$(CONFIG_BOOTBLOCK_SOURCE)) $(objutil)/romcc/romcc $(OPTION_TABLE_H) $(KCONFIG_AUTOHEADER)
# The open quote in the subst messes with syntax highlighting. Fix it - ")
@printf " ROMCC $(subst $(obj)/,,$(@))\n"
$(CC_bootblock) -D__ROMCC__ -D__BOOTBLOCK__ $(CPPFLAGS_bootblock) -MM -MT$(objgenerated)/bootblock.inc \
$< > $(objgenerated)/bootblock.inc.d
$(CC_bootblock) -D__ROMCC__ -D__BOOTBLOCK__ $(CPPFLAGS_bootblock) -E \
$< -o $(objgenerated)/bootblock_romcc.c
$(ROMCC) -c -S $(bootblock_romccflags) -I. $(CPPFLAGS_bootblock) $< -o $@
# bootblock.ld is part of $(bootblock-objs)
$(objcbfs)/bootblock.debug: $$(bootblock-objs)
@printf " LINK $(subst $(obj)/,,$(@))\n"
$(LD_bootblock) $(LDFLAGS_bootblock) -o $@ -L$(obj) \
$(filter-out %.ld,$(bootblock-objs)) \
-T $(call src-to-obj,bootblock,src/arch/x86/bootblock.ld)
endif # ROMCC_BOOTBLOCK
endif # CONFIG_ARCH_BOOTBLOCK_X86_32 / CONFIG_ARCH_BOOTBLOCK_X86_64 endif # CONFIG_ARCH_BOOTBLOCK_X86_32 / CONFIG_ARCH_BOOTBLOCK_X86_64
############################################################################### ###############################################################################
@ -223,9 +168,7 @@ ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y)
romstage-$(CONFIG_HAVE_ACPI_RESUME) += acpi_s3.c romstage-$(CONFIG_HAVE_ACPI_RESUME) += acpi_s3.c
# gdt_init.S is included by entry32.inc when romstage is the first C # gdt_init.S is included by entry32.inc when romstage is the first C
# environment. # environment.
ifneq ($(CONFIG_ROMCC_BOOTBLOCK),y)
romstage-y += gdt_init.S romstage-y += gdt_init.S
endif
romstage-y += cbmem.c romstage-y += cbmem.c
romstage-$(CONFIG_IDT_IN_EVERY_STAGE) += exception.c romstage-$(CONFIG_IDT_IN_EVERY_STAGE) += exception.c
romstage-$(CONFIG_IDT_IN_EVERY_STAGE) += idt.S romstage-$(CONFIG_IDT_IN_EVERY_STAGE) += idt.S

23
src/arch/x86/bootblock.ld
View File

@ -1,23 +0,0 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <arch/x86/failover.ld>
#include <cpu/x86/16bit/entry16.ld>
#include <cpu/x86/16bit/reset16.ld>
#include <arch/x86/id.ld>
#if CONFIG(CPU_INTEL_FIRMWARE_INTERFACE_TABLE)
#include <cpu/intel/fit/fit.ld>
#endif
/* Include generated .ld files. */
#include <generated/bootblock.ld>

66
src/arch/x86/bootblock_normal.c
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@ -1,66 +0,0 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <smp/node.h>
#include <arch/bootblock_romcc.h>
#include <pc80/mc146818rtc.h>
#include <halt.h>
static const char *get_fallback(const char *stagelist)
{
while (*stagelist)
stagelist++;
return ++stagelist;
}
static void main(unsigned long bist)
{
u8 boot_mode;
const char *default_filenames =
"normal/romstage\0fallback/romstage";
if (boot_cpu()) {
bootblock_mainboard_init();
sanitize_cmos();
boot_mode = do_normal_boot();
} else {
/* Questionable single byte read from CMOS.
* Do not add any other CMOS access in the
* bootblock for AP CPUs.
*/
boot_mode = boot_use_normal(cmos_read(RTC_BOOT_BYTE));
}
char *normal_candidate = (char *)walkcbfs("coreboot-stages");
if (!normal_candidate)
normal_candidate = default_filenames;
unsigned long entry;
if (boot_mode) {
entry = findstage(normal_candidate);
if (entry)
call(entry, bist);
}
entry = findstage(get_fallback(normal_candidate));
if (entry)
call(entry, bist);
/* duh. we're stuck */
halt();
}

49
src/arch/x86/bootblock_romcc.S
View File

@ -1,49 +0,0 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/*
* This is the original bootblock used by coreboot on x86 systems. It contains
* a monolithic code flow, assembled from the following stages:
* - reset16.inc: the reset vector
* - entry16.inc: protected mode setup
* - entry32.inc: segment descriptor setup
* - timestamp.inc: store TSC in MMX registers
* - generated/bootblock.inc: ROMCC part of the bootblock
*
* This is used on platforms which select ROMCC_BOOTBLOCK, and it
* tries to do the absolute minimum before walking CBFS and jumping to romstage.
*
* This file assembles the bootblock program by the order of the includes. Thus,
* it's extremely important that one pays very careful attention to the order
* of the includes.
*/
#include <arch/x86/prologue.inc>
#include <cpu/x86/16bit/entry16.inc>
#include <cpu/x86/16bit/reset16.inc>
#include <cpu/x86/32bit/entry32.inc>
#include <arch/x86/timestamp.inc>
#if CONFIG(SSE)
#include <cpu/x86/sse_enable.inc>
#endif
/*
* This bootblock.inc file is generated by ROMCC. The above program flow
* falls through to this point. ROMCC assumes the last function it parsed
* is the main function and it places its instructions at the beginning of
* the generated file. Moreover, any library/common code needed in bootblock
* needs to come after bootblock.inc.
*/
#include <generated/bootblock.inc>

36
src/arch/x86/bootblock_simple.c
View File

@ -1,36 +0,0 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <smp/node.h>
#include <arch/bootblock_romcc.h>
#include <pc80/mc146818rtc.h>
#include <halt.h>
static void main(unsigned long bist)
{
if (boot_cpu()) {
bootblock_mainboard_init();
sanitize_cmos();
#if CONFIG(CMOS_POST)
cmos_post_init();
#endif
}
const char *target1 = "fallback/romstage";
unsigned long entry;
entry = findstage(target1);
if (entry)
call(entry, bist);
halt();
}

8
src/arch/x86/car.ld
View File

@ -36,11 +36,9 @@
/* Stack for CAR stages. Since it persists across all stages that /* Stack for CAR stages. Since it persists across all stages that
* use CAR it can be reused. The chipset/SoC is expected to provide * use CAR it can be reused. The chipset/SoC is expected to provide
* the stack size. */ * the stack size. */
#if !CONFIG(ROMCC_BOOTBLOCK)
_car_stack = .; _car_stack = .;
. += CONFIG_DCACHE_BSP_STACK_SIZE; . += CONFIG_DCACHE_BSP_STACK_SIZE;
_ecar_stack = .; _ecar_stack = .;
#endif
/* The pre-ram cbmem console as well as the timestamp region are fixed /* The pre-ram cbmem console as well as the timestamp region are fixed
* in size. Therefore place them above the car global section so that * in size. Therefore place them above the car global section so that
* multiple stages (romstage and verstage) have a consistent * multiple stages (romstage and verstage) have a consistent
@ -86,10 +84,6 @@
_ebss = .; _ebss = .;
_car_unallocated_start = .; _car_unallocated_start = .;
#if CONFIG(ROMCC_BOOTBLOCK)
_car_stack = .;
_ecar_stack = _car_region_end;
#endif
_car_region_end = . + CONFIG_DCACHE_RAM_SIZE - (. - _car_region_start); _car_region_end = . + CONFIG_DCACHE_RAM_SIZE - (. - _car_region_start);
} }
@ -108,6 +102,4 @@ _bogus = ASSERT((CONFIG_DCACHE_RAM_SIZE == 0) || (SIZEOF(.car.data) <= CONFIG_DC
#if CONFIG(PAGING_IN_CACHE_AS_RAM) #if CONFIG(PAGING_IN_CACHE_AS_RAM)
_bogus2 = ASSERT(_pagetables == ALIGN(_pagetables, 4096), "_pagetables aren't 4KiB aligned"); _bogus2 = ASSERT(_pagetables == ALIGN(_pagetables, 4096), "_pagetables aren't 4KiB aligned");
#endif #endif
#if !CONFIG(ROMCC_BOOTBLOCK)
_bogus3 = ASSERT(CONFIG_DCACHE_BSP_STACK_SIZE > 0x0, "BSP stack size not configured"); _bogus3 = ASSERT(CONFIG_DCACHE_BSP_STACK_SIZE > 0x0, "BSP stack size not configured");
#endif

66
src/arch/x86/failover.ld
View File

@ -1,66 +0,0 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
ENTRY(_start)
MEMORY {
rom : ORIGIN = CONFIG_X86_RESET_VECTOR - 0xfff0, LENGTH = 64K
}
TARGET(binary)
SECTIONS
{
/* Symbol ap_sipi_vector must be aligned to 4kB to start AP CPUs
* with Startup IPI message without RAM. Align .rom to next 4 byte
* boundary anyway, so no pad byte appears between _rom and _start.
*/
.bogus ROMLOC_MIN : {
. = CONFIG(SIPI_VECTOR_IN_ROM) ? ALIGN(4096) : ALIGN(4);
ROMLOC = .;
} >rom = 0xff
/* This section might be better named .setup */
.rom ROMLOC : {
_rom = .;
*(.rom.text);
*(.rom.data);
*(.rom.data.*);
*(.text);
*(.text.*);
*(.rodata);
*(.rodata.*);
_erom = .;
} >rom = 0xff
/* Allocation reserves extra 16 bytes here. Alignment requirements
* may cause the total size of a section to change when the start
* address gets applied.
*/
ROMLOC_MIN = 0xffffff00 - (_erom - _rom + 16) -
(CONFIG(SIPI_VECTOR_IN_ROM) ? 4096 : 0);
/* Post-check proper SIPI vector. */
_bogus = ASSERT(!CONFIG(SIPI_VECTOR_IN_ROM) || (ap_sipi_vector_in_rom == 0xff),
"Address mismatch on AP_SIPI_VECTOR");
/DISCARD/ : {
*(.comment)
*(.note)
*(.comment.*)
*(.note.*)
*(.eh_frame)
*(.iplt)
*(.rel.*)
*(.igot.*)
}
}

45
src/arch/x86/include/arch/bootblock_romcc.h
View File

@ -1,45 +0,0 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <cpu/x86/lapic/boot_cpu.c>
#ifdef CONFIG_BOOTBLOCK_RESETS
#include CONFIG_BOOTBLOCK_RESETS
#endif
#ifdef CONFIG_BOOTBLOCK_CPU_INIT
#include CONFIG_BOOTBLOCK_CPU_INIT
#endif
#ifdef CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT
#include CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT
#endif
#ifdef CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT
#include CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT
#endif
#ifdef CONFIG_BOOTBLOCK_MAINBOARD_INIT
#include CONFIG_BOOTBLOCK_MAINBOARD_INIT
#else
static void bootblock_mainboard_init(void)
{
#ifdef CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT
bootblock_northbridge_init();
#endif
#ifdef CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT
bootblock_southbridge_init();
#endif
#ifdef CONFIG_BOOTBLOCK_CPU_INIT
bootblock_cpu_init();
#endif
}
#endif

1
src/arch/x86/memlayout.ld
View File

@ -49,7 +49,6 @@ SECTIONS
#include EARLY_MEMLAYOUT #include EARLY_MEMLAYOUT
#elif ENV_BOOTBLOCK #elif ENV_BOOTBLOCK
/* arch/x86/bootblock.ld contains the logic for the ROMCC_BOOTBLOCK linking. */
BOOTBLOCK(CONFIG_X86_RESET_VECTOR - CONFIG_C_ENV_BOOTBLOCK_SIZE + 0x10, BOOTBLOCK(CONFIG_X86_RESET_VECTOR - CONFIG_C_ENV_BOOTBLOCK_SIZE + 0x10,
CONFIG_C_ENV_BOOTBLOCK_SIZE) CONFIG_C_ENV_BOOTBLOCK_SIZE)

2
src/lib/Makefile.inc
View File

@ -268,9 +268,7 @@ postcar-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
postcar-$(CONFIG_GENERIC_UDELAY) += timer.c postcar-$(CONFIG_GENERIC_UDELAY) += timer.c
# Use program.ld for all the platforms which use C fo the bootblock. # Use program.ld for all the platforms which use C fo the bootblock.
ifneq ($(CONFIG_ROMCC_BOOTBLOCK),y)
bootblock-y += program.ld bootblock-y += program.ld
endif
decompressor-y += program.ld decompressor-y += program.ld
postcar-y += program.ld postcar-y += program.ld