sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

mb/purism/librem_mini: Update smbios_slot_desc for M.2/WLAN

Browse Source 
Add strings for M.2 keying and number of PCIe lanes.

Change-Id: I2e13749b50263ee5c2388a419bc8d784af6bd880
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47251
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Matt DeVillier 2020-11-05 11:34:50 -06:00 committed by Patrick Georgi
parent e952392615
commit 0e4f37f7a7
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb
View File

@ -197,7 +197,7 @@ chip soc/intel/cannonlake
register "PcieRpLtrEnable[7]" = "1" register "PcieRpLtrEnable[7]" = "1"
# ClkSrcUsage must be set to free-run since SRCCLKREQ2 is NC # ClkSrcUsage must be set to free-run since SRCCLKREQ2 is NC
register "PcieClkSrcUsage[2]" = "0x80" register "PcieClkSrcUsage[2]" = "0x80"
smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230" "SlotDataBusWidth1X"
end end
device pci 1d.0 off end # PCI Express Port 9 device pci 1d.0 off end # PCI Express Port 9
device pci 1d.1 on # PCI Express Port 10 device pci 1d.1 on # PCI Express Port 10