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Improving BKDG implementation of P-states,

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CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode.

I didn't understand quite why it did that iwth F3xA0 (Power
Control Misc Register) so I moved Pll Lock time to rules in defaults.h
and reimplemented F3xA0 programming. A later patch will remove
a part I don't know what's mean to do.

Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6396 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Xavi Drudis Ferran
2011-02-28 00:18:43 +00:00
committed by Marc Jones
parent adb23a51f5
commit 0e5d3e16b4
5 changed files with 53 additions and 14 deletions
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8
src/northbridge/amd/amdfam10/Kconfig
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@@ -112,4 +112,12 @@ if DIMM_DDR3
endif
endif
config SVI_HIGH_FREQ
bool
default n
depends on NORTHBRIDGE_AMD_AMDFAM10
help
Select this for boards with a Voltage Regulator able to operate
at 3.4 MHz in SVI mode. Ignored unless the AMD CPU is rev C3.
source src/northbridge/amd/amdfam10/root_complex/Kconfig