soc/mediatek/mt8183: Add ddr geometry to support 6GB, 8GB DDR bootup
Currently the DRAM initialization code can only work on 4GB size and want to support larger memory sizes in future, so add geometry information to the DRAM calibration parameters. BUG=none BRANCH=kukui TEST=Boots correctly on Kukui Change-Id: I1fdf50b75c6a552c0a889f21e1a81ab4b9a305fa Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41949 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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committed by
Hung-Te Lin
parent
92fb91935b
commit
0e6cb83abb
@@ -5,6 +5,7 @@
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#include <delay.h>
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#include <delay.h>
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#include <soc/emi.h>
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#include <soc/emi.h>
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#include <soc/dramc_pi_api.h>
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#include <soc/dramc_pi_api.h>
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#include <soc/dramc_param.h>
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#include <soc/dramc_register.h>
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#include <soc/dramc_register.h>
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#include <soc/infracfg.h>
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#include <soc/infracfg.h>
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#include <string.h>
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#include <string.h>
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@@ -6,6 +6,7 @@
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#include <device/mmio.h>
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#include <device/mmio.h>
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#include <soc/emi.h>
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#include <soc/emi.h>
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#include <soc/dramc_register.h>
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#include <soc/dramc_register.h>
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#include <soc/dramc_param.h>
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#include <soc/dramc_pi_api.h>
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#include <soc/dramc_pi_api.h>
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#include <timer.h>
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#include <timer.h>
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@@ -3,14 +3,14 @@
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#ifndef SOC_MEDIATEK_MT8183_DRAMC_PARAM_H
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#ifndef SOC_MEDIATEK_MT8183_DRAMC_PARAM_H
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#define SOC_MEDIATEK_MT8183_DRAMC_PARAM_H
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#define SOC_MEDIATEK_MT8183_DRAMC_PARAM_H
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#include <soc/dramc_common_mt8183.h>
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#include <soc/emi.h>
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#include <stdint.h>
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#include <stdint.h>
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#include <sys/types.h>
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#include <sys/types.h>
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#include "emi.h"
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enum {
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enum {
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DRAMC_PARAM_HEADER_MAGIC = 0x44524d4b,
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DRAMC_PARAM_HEADER_MAGIC = 0x44524d4b,
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DRAMC_PARAM_HEADER_VERSION = 2,
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DRAMC_PARAM_HEADER_VERSION = 3,
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};
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};
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enum DRAMC_PARAM_STATUS_CODES {
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enum DRAMC_PARAM_STATUS_CODES {
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@@ -37,10 +37,16 @@ enum DRAMC_PARAM_FLAGS {
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DRAMC_FLAG_HAS_SAVED_DATA = 0x0001,
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DRAMC_FLAG_HAS_SAVED_DATA = 0x0001,
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};
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};
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enum DRAMC_PARAM_GEOMETRY_TYPE {
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DDR_TYPE_2CH_2RK_4GB_2_2,
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DDR_TYPE_2CH_2RK_6GB_3_3,
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DDR_TYPE_2CH_2RK_8GB_4_4,
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};
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struct dramc_param_header {
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struct dramc_param_header {
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u32 status; /* DRAMC_PARAM_STATUS_CODES */
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u32 status; /* DRAMC_PARAM_STATUS_CODES */
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u32 magic;
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u32 magic;
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u32 version;
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u32 version; /* DRAMC_PARAM_HEADER_VERSION */
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u32 size; /* size of whole dramc_param */
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u32 size; /* size of whole dramc_param */
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u16 config; /* DRAMC_PARAM_CONFIG */
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u16 config; /* DRAMC_PARAM_CONFIG */
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u16 flags; /* DRAMC_PARAM_FLAGS */
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u16 flags; /* DRAMC_PARAM_FLAGS */
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@@ -13,8 +13,9 @@ enum DRAMC_PARAM_SOURCE {
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};
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};
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struct sdram_params {
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struct sdram_params {
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u16 source; /* DRAMC_PARAM_SOURCE */
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u16 source; /* DRAMC_PARAM_SOURCE */
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u16 frequency;
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u16 frequency;
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u32 ddr_geometry; /* DRAMC_PARAM_GEOMETRY_TYPE */
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u8 wr_level[CHANNEL_MAX][RANK_MAX][DQS_NUMBER];
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u8 wr_level[CHANNEL_MAX][RANK_MAX][DQS_NUMBER];
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/* DUTY */
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/* DUTY */
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