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soc/intel: transition full control over PM Timer from FSP to coreboot

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Set `EnableTcoTimer=1` in order to keep FSP from
 1) enabling ACPI Timer emulation in uCode.
 2) disabling the PM ACPI Timer.

Both actions are now done in coreboot.

`EnableTcoTimer=1` makes FSP skip these steps in any possible case
including `SkipMpInit=0`, `SkipMpInit=1`, use of the MP PPI or FSP
Multiphase Init. This way full control is left to coreboot.

Change-Id: I8005daed732c031980ccc379375ff5b09df8dac1
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57933
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Lance Zhao
This commit is contained in:
Michael Niewöhner
2021-09-25 00:10:30 +02:00
parent 68bacc2109
commit 0e905801f8
7 changed files with 66 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

14
src/soc/intel/alderlake/fsp_params.c
View File

@@ -574,6 +574,19 @@ static void fill_fsps_8254_params(FSP_S_CONFIG *s_cfg,
s_cfg->Enable8254ClockGatingOnS3 = !use_8254;
}
static void fill_fsps_pm_timer_params(FSP_S_CONFIG *s_cfg,
const struct soc_intel_alderlake_config *config)
{
/*
* Legacy PM ACPI Timer (and TCO Timer)
* This *must* be 1 in any case to keep FSP from
* 1) enabling PM ACPI Timer emulation in uCode.
* 2) disabling the PM ACPI Timer.
* We handle both by ourself!
*/
s_cfg->EnableTcoTimer = 1;
}
static void fill_fsps_storage_params(FSP_S_CONFIG *s_cfg,
const struct soc_intel_alderlake_config *config)
{
@@ -742,6 +755,7 @@ static void soc_silicon_init_params(FSP_S_CONFIG *s_cfg,
fill_fsps_thc_params,
fill_fsps_tbt_params,
fill_fsps_8254_params,
fill_fsps_pm_timer_params,
fill_fsps_storage_params,
fill_fsps_pcie_params,
fill_fsps_misc_power_params,

9
src/soc/intel/cannonlake/fsp_params.c
View File

@@ -437,7 +437,14 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->Enable8254ClockGating = !use_8254;
params->Enable8254ClockGatingOnS3 = !use_8254;
params->EnableTcoTimer = CONFIG(USE_PM_ACPI_TIMER);
/*
* Legacy PM ACPI Timer (and TCO Timer)
* This *must* be 1 in any case to keep FSP from
* 1) enabling PM ACPI Timer emulation in uCode.
* 2) disabling the PM ACPI Timer.
* We handle both by ourself!
*/
params->EnableTcoTimer = 1;
/* USB */
for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) {

9
src/soc/intel/elkhartlake/fsp_params.c
View File

@@ -167,6 +167,15 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->Enable8254ClockGating = !use_8254;
params->Enable8254ClockGatingOnS3 = 1;
/*
* Legacy PM ACPI Timer (and TCO Timer)
* This *must* be 1 in any case to keep FSP from
* 1) enabling PM ACPI Timer emulation in uCode.
* 2) disabling the PM ACPI Timer.
* We handle both by ourself!
*/
params->EnableTcoTimer = 1;
/* PCH Master Gating Control */
params->PchPostMasterClockGating = 1;
params->PchPostMasterPowerGating = 1;

9
src/soc/intel/icelake/fsp_params.c
View File

@@ -98,6 +98,15 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->Enable8254ClockGating = !use_8254;
params->Enable8254ClockGatingOnS3 = !use_8254;
/*
* Legacy PM ACPI Timer (and TCO Timer)
* This *must* be 1 in any case to keep FSP from
* 1) enabling PM ACPI Timer emulation in uCode.
* 2) disabling the PM ACPI Timer.
* We handle both by ourself!
*/
params->EnableTcoTimer = 1;
/* S0ix */
params->PchPmSlpS0Enable = config->s0ix_enable;

9
src/soc/intel/jasperlake/fsp_params.c
View File

@@ -85,6 +85,15 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->Enable8254ClockGating = !use_8254;
params->Enable8254ClockGatingOnS3 = 1;
/*
* Legacy PM ACPI Timer (and TCO Timer)
* This *must* be 1 in any case to keep FSP from
* 1) enabling PM ACPI Timer emulation in uCode.
* 2) disabling the PM ACPI Timer.
* We handle both by ourself!
*/
params->EnableTcoTimer = 1;
/* disable Legacy PME */
memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci));

9
src/soc/intel/skylake/chip.c
View File

@@ -345,7 +345,14 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
bool use_8254 = get_uint_option("legacy_8254_timer", CONFIG(USE_LEGACY_8254_TIMER));
params->Early8254ClockGatingEnable = !use_8254;
params->EnableTcoTimer = CONFIG(USE_PM_ACPI_TIMER);
/*
* Legacy PM ACPI Timer (and TCO Timer)
* This *must* be 1 in any case to keep FSP from
* 1) enabling PM ACPI Timer emulation in uCode.
* 2) disabling the PM ACPI Timer.
* We handle both by ourself!
*/
params->EnableTcoTimer = 1;
memcpy(params->SerialIoDevMode, config->SerialIoDevMode,
sizeof(params->SerialIoDevMode));

9
src/soc/intel/tigerlake/fsp_params.c
View File

@@ -502,6 +502,15 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->Enable8254ClockGating = !use_8254;
params->Enable8254ClockGatingOnS3 = !use_8254;
/*
* Legacy PM ACPI Timer (and TCO Timer)
* This *must* be 1 in any case to keep FSP from
* 1) enabling PM ACPI Timer emulation in uCode.
* 2) disabling the PM ACPI Timer.
* We handle both by ourself!
*/
params->EnableTcoTimer = 1;
/* Enable Hybrid storage auto detection */
if (CONFIG(SOC_INTEL_CSE_LITE_SKU) && cse_is_hfs3_fw_sku_lite()
&& vboot_recovery_mode_enabled() && !cse_is_hfs1_com_normal()) {