soc/intel/cannonlake: Add back PM TIMER EMULATION

ACPI PM timer emulation will be added back as default FSP stops TCO count
for power saving, which will also stop ACPI PM timer within PCH. CPU PM TIMER
EMULATION will help UEFI payload pass, instead of endless loop wait for
ACPI PM timer counter to increase.

BUG=N/A
TEST=Build and boot up fine with whiskey lake rvp board into UEFI shell.

Change-Id: Ie069e815e6244c3f85fabf51e186311621d316fd
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/28937
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/intel/common/block/include/intelblocks/msr.h

@@ -36,6 +36,7 @@
 #define MSR_EMULATE_PM_TMR	0x121
 #define   EMULATE_DELAY_OFFSET_VALUE	20
 #define   EMULATE_PM_TMR_EN	(1 << 16)
+#define   EMULATE_DELAY_VALUE	0x13
 #define MSR_FEATURE_CONFIG	0x13c
 #define   FEATURE_CONFIG_RESERVED_MASK	0x3ULL
 #define   FEATURE_CONFIG_LOCK	(1 << 0)