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arch/x86: Flip option NO_CAR_GLOBAL_MIGRATION

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It is easier to track CAR_GLOBAL_MIGRATION which is
the approach to be deprecated with the next release.

This change enforces new policy; POSTCAR_STAGE=y is
not allowed together with CAR_GLOBAL_MIGRATION=y.

Change-Id: I0dbad6a14e68bf566ac0f151dc8ea259e5ae2250
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34804
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Kyösti Mälkki
2019-08-09 07:11:07 +03:00
parent 9fc12e0d4e
commit 0f5e01a962
33 changed files with 18 additions and 37 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
src/arch/x86/Kconfig
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@@ -222,8 +222,9 @@ config VERSTAGE_ADDR
# Use the post CAR infrastructure for tearing down cache-as-ram # Use the post CAR infrastructure for tearing down cache-as-ram
# from a program loaded in RAM and subsequently loading ramstage. # from a program loaded in RAM and subsequently loading ramstage.
config POSTCAR_STAGE config POSTCAR_STAGE
def_bool n def_bool y
select NO_CAR_GLOBAL_MIGRATION depends on ARCH_X86
depends on !CAR_GLOBAL_MIGRATION
config VERSTAGE_DEBUG_SPINLOOP config VERSTAGE_DEBUG_SPINLOOP
bool bool

6
src/arch/x86/car.ld
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@@ -76,7 +76,7 @@
* cbmem console. This is useful for clearing this area on a per-stage * cbmem console. This is useful for clearing this area on a per-stage
* basis when more than one stage uses cache-as-ram for CAR_GLOBALs. */ * basis when more than one stage uses cache-as-ram for CAR_GLOBALs. */
_car_global_start = .; _car_global_start = .;
#if CONFIG(NO_CAR_GLOBAL_MIGRATION) #if !CONFIG(CAR_GLOBAL_MIGRATION)
/* Allow global unitialized variables when CAR_GLOBALs are not used. */ /* Allow global unitialized variables when CAR_GLOBALs are not used. */
*(.bss) *(.bss)
*(.bss.*) *(.bss.*)
@@ -84,7 +84,7 @@
*(.sbss.*) *(.sbss.*)
#else #else
/* .car.global_data objects only around when /* .car.global_data objects only around when
* !CONFIG_NO_CAR_GLOBAL_MIGRATION is employed. */ * CONFIG_CAR_GLOBAL_MIGRATION is employed. */
*(.car.global_data); *(.car.global_data);
#endif #endif
. = ALIGN(ARCH_POINTER_ALIGN_SIZE); . = ALIGN(ARCH_POINTER_ALIGN_SIZE);
@@ -107,7 +107,7 @@
.illegal_globals . : { .illegal_globals . : {
*(EXCLUDE_FILE ("*/libagesa.*.a:" "*/romstage*/buildOpts.o" "*/romstage*/agesawrapper.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data) *(EXCLUDE_FILE ("*/libagesa.*.a:" "*/romstage*/buildOpts.o" "*/romstage*/agesawrapper.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data)
*(EXCLUDE_FILE ("*/libagesa.*.a:" "*/romstage*/buildOpts.o" "*/romstage*/agesawrapper.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data.*) *(EXCLUDE_FILE ("*/libagesa.*.a:" "*/romstage*/buildOpts.o" "*/romstage*/agesawrapper.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data.*)
#if !CONFIG(NO_CAR_GLOBAL_MIGRATION) #if CONFIG(CAR_GLOBAL_MIGRATION)
*(.bss) *(.bss)
*(.bss.*) *(.bss.*)
*(.sbss) *(.sbss)

8
src/arch/x86/include/arch/early_variables.h
View File

@@ -20,7 +20,7 @@
#include <commonlib/helpers.h> #include <commonlib/helpers.h>
#include <stdlib.h> #include <stdlib.h>
#if ENV_CACHE_AS_RAM && !CONFIG(NO_CAR_GLOBAL_MIGRATION) #if ENV_CACHE_AS_RAM && CONFIG(CAR_GLOBAL_MIGRATION)
asm(".section .car.global_data,\"w\",@nobits"); asm(".section .car.global_data,\"w\",@nobits");
asm(".previous"); asm(".previous");
#ifdef __clang__ #ifdef __clang__
@@ -83,8 +83,8 @@ static inline size_t car_object_offset(void *ptr)
/* /*
* We might end up here if: * We might end up here if:
* 1. ENV_CACHE_AS_RAM is not set for the stage or * 1. ENV_CACHE_AS_RAM is not set for the stage or
* 2. ENV_CACHE_AS_RAM is set for the stage but CONFIG_NO_CAR_GLOBAL_MIGRATION * 2. ENV_CACHE_AS_RAM is set for the stage but CONFIG_CAR_GLOBAL_MIGRATION
* is also set. In this case, there is no need to migrate CAR global * is not set. In this case, there is no need to migrate CAR global
* variables. But, since we might still be running out of CAR, car_active needs * variables. But, since we might still be running out of CAR, car_active needs
* to return 1 if ENV_CACHE_AS_RAM is set. * to return 1 if ENV_CACHE_AS_RAM is set.
*/ */
@@ -101,6 +101,6 @@ static inline int car_active(void) { return 0; }
#define car_get_var(var) (var) #define car_get_var(var) (var)
#define car_sync_var(var) (var) #define car_sync_var(var) (var)
#define car_set_var(var, val) (var) = (val) #define car_set_var(var, val) (var) = (val)
#endif /* ENV_CACHE_AS_RAM && !CONFIG(NO_CAR_GLOBAL_MIGRATION) */ #endif /* ENV_CACHE_AS_RAM && CONFIG(CAR_GLOBAL_MIGRATION) */
#endif /* ARCH_EARLY_VARIABLES_H */ #endif /* ARCH_EARLY_VARIABLES_H */

4
src/cpu/Kconfig
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@@ -10,12 +10,12 @@ config CACHE_AS_RAM
bool bool
default y default y
config NO_CAR_GLOBAL_MIGRATION config CAR_GLOBAL_MIGRATION
bool bool
default n default n
depends on CACHE_AS_RAM depends on CACHE_AS_RAM
help help
This option is selected if there is no need to migrate CAR globals. This option is selected if there is need to migrate CAR globals.
All stages which use CAR globals can directly access the variables All stages which use CAR globals can directly access the variables
from their linked addresses. from their linked addresses.

1
src/cpu/amd/agesa/Kconfig
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@@ -29,7 +29,6 @@ config CPU_AMD_AGESA
select UDELAY_LAPIC select UDELAY_LAPIC
select LAPIC_MONOTONIC_TIMER select LAPIC_MONOTONIC_TIMER
select SPI_FLASH if HAVE_ACPI_RESUME select SPI_FLASH if HAVE_ACPI_RESUME
select POSTCAR_STAGE
select SMM_ASEG select SMM_ASEG
if CPU_AMD_AGESA if CPU_AMD_AGESA

1
src/cpu/amd/family_10h-family_15h/Kconfig
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@@ -9,6 +9,7 @@ config CPU_AMD_MODEL_10XXX
select UDELAY_LAPIC select UDELAY_LAPIC
select SUPPORT_CPU_UCODE_IN_CBFS select SUPPORT_CPU_UCODE_IN_CBFS
select CPU_MICROCODE_MULTIPLE_FILES select CPU_MICROCODE_MULTIPLE_FILES
select CAR_GLOBAL_MIGRATION
select ACPI_HUGE_LOWMEM_BACKUP select ACPI_HUGE_LOWMEM_BACKUP
if CPU_AMD_MODEL_10XXX if CPU_AMD_MODEL_10XXX

2
src/cpu/amd/pi/Kconfig
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@@ -28,7 +28,7 @@ config CPU_AMD_PI
select UDELAY_LAPIC select UDELAY_LAPIC
select LAPIC_MONOTONIC_TIMER select LAPIC_MONOTONIC_TIMER
select SPI_FLASH if HAVE_ACPI_RESUME select SPI_FLASH if HAVE_ACPI_RESUME
select POSTCAR_STAGE if !BINARYPI_LEGACY_WRAPPER select CAR_GLOBAL_MIGRATION if BINARYPI_LEGACY_WRAPPER
select SMM_ASEG select SMM_ASEG
if CPU_AMD_PI if CPU_AMD_PI

1
src/cpu/via/nano/Kconfig
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@@ -30,6 +30,7 @@ config CPU_SPECIFIC_OPTIONS
select MMX select MMX
select SSE2 select SSE2
select SUPPORT_CPU_UCODE_IN_CBFS select SUPPORT_CPU_UCODE_IN_CBFS
select CAR_GLOBAL_MIGRATION
config DCACHE_RAM_BASE config DCACHE_RAM_BASE
hex hex

2
src/cpu/x86/Makefile.inc
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@@ -1,5 +1,5 @@
ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y) ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y)
ifneq ($(CONFIG_NO_CAR_GLOBAL_MIGRATION),y) ifeq ($(CONFIG_CAR_GLOBAL_MIGRATION),y)
romstage-$(CONFIG_CACHE_AS_RAM) += car.c romstage-$(CONFIG_CACHE_AS_RAM) += car.c
endif endif
endif endif

1
src/drivers/intel/fsp1_0/Kconfig
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@@ -16,6 +16,7 @@
config PLATFORM_USES_FSP1_0 config PLATFORM_USES_FSP1_0
bool bool
default n default n
select CAR_GLOBAL_MIGRATION
help help
Selected for Intel processors/platform combinations that use the Selected for Intel processors/platform combinations that use the
Intel Firmware Support Package (FSP) 1.0 for initialization. Intel Firmware Support Package (FSP) 1.0 for initialization.

1
src/drivers/intel/fsp1_1/Kconfig
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@@ -18,7 +18,6 @@ config PLATFORM_USES_FSP1_1
bool bool
select UEFI_2_4_BINDING select UEFI_2_4_BINDING
select INTEL_GMA_ADD_VBT if RUN_FSP_GOP select INTEL_GMA_ADD_VBT if RUN_FSP_GOP
select POSTCAR_STAGE
help help
Does the code require the Intel Firmware Support Package? Does the code require the Intel Firmware Support Package?

2
src/lib/imd_cbmem.c
View File

@@ -41,7 +41,7 @@
*/ */
#define CAN_USE_GLOBALS \ #define CAN_USE_GLOBALS \
(!CONFIG(ARCH_X86) || ENV_RAMSTAGE || ENV_POSTCAR || \ (!CONFIG(ARCH_X86) || ENV_RAMSTAGE || ENV_POSTCAR || \
CONFIG(NO_CAR_GLOBAL_MIGRATION)) !CONFIG(CAR_GLOBAL_MIGRATION))
static inline struct imd *cbmem_get_imd(void) static inline struct imd *cbmem_get_imd(void)
{ {

1
src/mainboard/emulation/qemu-i440fx/Kconfig
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@@ -12,7 +12,6 @@ config BOARD_SPECIFIC_OPTIONS
select BOARD_ROMSIZE_KB_256 select BOARD_ROMSIZE_KB_256
select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_HAS_NATIVE_VGA_INIT
select MAINBOARD_FORCE_NATIVE_VGA_INIT select MAINBOARD_FORCE_NATIVE_VGA_INIT
select POSTCAR_STAGE
config MAINBOARD_DIR config MAINBOARD_DIR
string string

1
src/mainboard/emulation/qemu-q35/Kconfig
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@@ -11,7 +11,6 @@ config BOARD_SPECIFIC_OPTIONS
select BOARD_ROMSIZE_KB_2048 select BOARD_ROMSIZE_KB_2048
select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_HAS_NATIVE_VGA_INIT
select MAINBOARD_FORCE_NATIVE_VGA_INIT select MAINBOARD_FORCE_NATIVE_VGA_INIT
select POSTCAR_STAGE
config MAINBOARD_DIR config MAINBOARD_DIR
string string

1
src/mainboard/intel/galileo/Kconfig
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@@ -25,7 +25,6 @@ config BOARD_SPECIFIC_OPTIONS
select MAINBOARD_HAS_TPM2 select MAINBOARD_HAS_TPM2
select PLATFORM_USES_FSP2_0 select PLATFORM_USES_FSP2_0
select UDK_2015_BINDING select UDK_2015_BINDING
select POSTCAR_STAGE
config MAINBOARD_DIR config MAINBOARD_DIR

1
src/northbridge/intel/e7505/Kconfig
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@@ -22,6 +22,5 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy
def_bool y def_bool y
select NO_MMCONF_SUPPORT select NO_MMCONF_SUPPORT
select HAVE_DEBUG_RAM_SETUP select HAVE_DEBUG_RAM_SETUP
select POSTCAR_STAGE
endif endif

1
src/northbridge/intel/gm45/Kconfig
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@@ -26,7 +26,6 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy
select INTEL_EDID select INTEL_EDID
select INTEL_GMA_ACPI select INTEL_GMA_ACPI
select INTEL_GMA_SSC_ALTERNATE_REF select INTEL_GMA_SSC_ALTERNATE_REF
select POSTCAR_STAGE
select PARALLEL_MP select PARALLEL_MP
config CBFS_SIZE config CBFS_SIZE

1
src/northbridge/intel/haswell/Kconfig
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@@ -19,7 +19,6 @@ config NORTHBRIDGE_INTEL_HASWELL
select CACHE_MRC_SETTINGS select CACHE_MRC_SETTINGS
select INTEL_DDI select INTEL_DDI
select INTEL_GMA_ACPI select INTEL_GMA_ACPI
select POSTCAR_STAGE
select C_ENVIRONMENT_BOOTBLOCK select C_ENVIRONMENT_BOOTBLOCK
select BOOTBLOCK_CONSOLE select BOOTBLOCK_CONSOLE

1
src/northbridge/intel/i440bx/Kconfig
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@@ -18,7 +18,6 @@ config NORTHBRIDGE_INTEL_I440BX
select NO_MMCONF_SUPPORT select NO_MMCONF_SUPPORT
select HAVE_DEBUG_RAM_SETUP select HAVE_DEBUG_RAM_SETUP
select UDELAY_IO select UDELAY_IO
select POSTCAR_STAGE
config SDRAMPWR_4DIMM config SDRAMPWR_4DIMM
bool bool

1
src/northbridge/intel/i945/Kconfig
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@@ -27,7 +27,6 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy
select INTEL_GMA_SSC_ALTERNATE_REF select INTEL_GMA_SSC_ALTERNATE_REF
select INTEL_EDID select INTEL_EDID
select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT
select POSTCAR_STAGE
select PARALLEL_MP select PARALLEL_MP
config NORTHBRIDGE_INTEL_SUBTYPE_I945GC config NORTHBRIDGE_INTEL_SUBTYPE_I945GC

1
src/northbridge/intel/nehalem/Kconfig
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@@ -20,7 +20,6 @@ config NORTHBRIDGE_INTEL_NEHALEM
select INTEL_EDID select INTEL_EDID
select INTEL_GMA_ACPI select INTEL_GMA_ACPI
select CACHE_MRC_SETTINGS select CACHE_MRC_SETTINGS
select POSTCAR_STAGE
select HAVE_DEBUG_RAM_SETUP select HAVE_DEBUG_RAM_SETUP
if NORTHBRIDGE_INTEL_NEHALEM if NORTHBRIDGE_INTEL_NEHALEM

1
src/northbridge/intel/pineview/Kconfig
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@@ -28,7 +28,6 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy
select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT
select INTEL_EDID if MAINBOARD_DO_NATIVE_VGA_INIT select INTEL_EDID if MAINBOARD_DO_NATIVE_VGA_INIT
select INTEL_GMA_ACPI select INTEL_GMA_ACPI
select POSTCAR_STAGE
select PARALLEL_MP select PARALLEL_MP
select C_ENVIRONMENT_BOOTBLOCK select C_ENVIRONMENT_BOOTBLOCK

1
src/northbridge/intel/sandybridge/Kconfig
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@@ -20,7 +20,6 @@ config NORTHBRIDGE_INTEL_SANDYBRIDGE
select CPU_INTEL_MODEL_206AX select CPU_INTEL_MODEL_206AX
select HAVE_DEBUG_RAM_SETUP select HAVE_DEBUG_RAM_SETUP
select INTEL_GMA_ACPI select INTEL_GMA_ACPI
select POSTCAR_STAGE
if NORTHBRIDGE_INTEL_SANDYBRIDGE if NORTHBRIDGE_INTEL_SANDYBRIDGE

1
src/northbridge/intel/x4x/Kconfig
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@@ -26,7 +26,6 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy
select VGA select VGA
select INTEL_GMA_ACPI select INTEL_GMA_ACPI
select CACHE_MRC_SETTINGS select CACHE_MRC_SETTINGS
select POSTCAR_STAGE
select PARALLEL_MP select PARALLEL_MP
config CBFS_SIZE config CBFS_SIZE

1
src/soc/amd/picasso/Kconfig
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@@ -56,7 +56,6 @@ config CPU_SPECIFIC_OPTIONS
select PARALLEL_MP select PARALLEL_MP
select PARALLEL_MP_AP_WORK select PARALLEL_MP_AP_WORK
select HAVE_SMI_HANDLER select HAVE_SMI_HANDLER
select POSTCAR_STAGE
select SSE2 select SSE2
select RTC select RTC

1
src/soc/amd/stoneyridge/Kconfig
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@@ -76,7 +76,6 @@ config CPU_SPECIFIC_OPTIONS
select PARALLEL_MP select PARALLEL_MP
select PARALLEL_MP_AP_WORK select PARALLEL_MP_AP_WORK
select HAVE_SMI_HANDLER select HAVE_SMI_HANDLER
select POSTCAR_STAGE
select SSE2 select SSE2
select RTC select RTC

1
src/soc/intel/apollolake/Kconfig
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@@ -57,7 +57,6 @@ config CPU_SPECIFIC_OPTIONS
select PCIEXP_CLK_PM select PCIEXP_CLK_PM
select PCIEXP_L1_SUB_STATE select PCIEXP_L1_SUB_STATE
select PCIEX_LENGTH_256MB select PCIEX_LENGTH_256MB
select POSTCAR_STAGE
select PMC_INVALID_READ_AFTER_WRITE select PMC_INVALID_READ_AFTER_WRITE
select PMC_GLOBAL_RESET_ENABLE_LOCK select PMC_GLOBAL_RESET_ENABLE_LOCK
select REG_SCRIPT select REG_SCRIPT

1
src/soc/intel/baytrail/Kconfig
View File

@@ -36,7 +36,6 @@ config CPU_SPECIFIC_OPTIONS
select HAVE_SPI_CONSOLE_SUPPORT select HAVE_SPI_CONSOLE_SUPPORT
select INTEL_GMA_ACPI select INTEL_GMA_ACPI
select INTEL_GMA_SWSMISCI select INTEL_GMA_SWSMISCI
select POSTCAR_STAGE
select CPU_INTEL_COMMON select CPU_INTEL_COMMON
select CPU_HAS_L2_ENABLE_MSR select CPU_HAS_L2_ENABLE_MSR

1
src/soc/intel/broadwell/Kconfig
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@@ -36,7 +36,6 @@ config CPU_SPECIFIC_OPTIONS
select HAVE_SPI_CONSOLE_SUPPORT select HAVE_SPI_CONSOLE_SUPPORT
select CPU_INTEL_COMMON select CPU_INTEL_COMMON
select INTEL_GMA_ACPI select INTEL_GMA_ACPI
select POSTCAR_STAGE
select HAVE_POWER_STATE_AFTER_FAILURE select HAVE_POWER_STATE_AFTER_FAILURE
select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE
select NO_FIXED_XIP_ROM_SIZE select NO_FIXED_XIP_ROM_SIZE

1
src/soc/intel/cannonlake/Kconfig
View File

@@ -76,7 +76,6 @@ config CPU_SPECIFIC_OPTIONS
select PARALLEL_MP select PARALLEL_MP
select PARALLEL_MP_AP_WORK select PARALLEL_MP_AP_WORK
select PLATFORM_USES_FSP2_0 select PLATFORM_USES_FSP2_0
select POSTCAR_STAGE
select REG_SCRIPT select REG_SCRIPT
select SMP select SMP
select SOC_AHCI_PORT_IMPLEMENTED_INVERT select SOC_AHCI_PORT_IMPLEMENTED_INVERT

1
src/soc/intel/denverton_ns/Kconfig
View File

@@ -32,7 +32,6 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON select SOC_INTEL_COMMON
select SOC_INTEL_COMMON_RESET select SOC_INTEL_COMMON_RESET
select PLATFORM_USES_FSP2_0 select PLATFORM_USES_FSP2_0
select POSTCAR_STAGE
select C_ENVIRONMENT_BOOTBLOCK select C_ENVIRONMENT_BOOTBLOCK
select IOAPIC select IOAPIC
select HAVE_SMI_HANDLER select HAVE_SMI_HANDLER

1
src/soc/intel/icelake/Kconfig
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@@ -32,7 +32,6 @@ config CPU_SPECIFIC_OPTIONS
select PARALLEL_MP_AP_WORK select PARALLEL_MP_AP_WORK
select MICROCODE_BLOB_UNDISCLOSED select MICROCODE_BLOB_UNDISCLOSED
select PLATFORM_USES_FSP2_1 select PLATFORM_USES_FSP2_1
select POSTCAR_STAGE
select REG_SCRIPT select REG_SCRIPT
select SMP select SMP
select SOC_AHCI_PORT_IMPLEMENTED_INVERT select SOC_AHCI_PORT_IMPLEMENTED_INVERT

1
src/soc/intel/skylake/Kconfig
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@@ -92,7 +92,6 @@ config USE_FSP2_0_DRIVER
select PLATFORM_USES_FSP2_0 select PLATFORM_USES_FSP2_0
select UDK_2015_BINDING select UDK_2015_BINDING
select INTEL_GMA_ADD_VBT if RUN_FSP_GOP select INTEL_GMA_ADD_VBT if RUN_FSP_GOP
select POSTCAR_STAGE
config USE_FSP1_1_DRIVER config USE_FSP1_1_DRIVER
def_bool y def_bool y