model_2065x: Use common i945-ivy TSEG SMM init.

Change-Id: I0302cbaeb45a55a4cfee94692eb7372f2b6b206d
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10468
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

src/northbridge/intel/nehalem/Makefile.inc

@@ -21,6 +21,7 @@ ifeq ($(CONFIG_NORTHBRIDGE_INTEL_NEHALEM),y)
 
 ramstage-y += ram_calc.c
 ramstage-y += northbridge.c
+ramstage-y += smi.c
 ramstage-y += gma.c
 
 ramstage-y += acpi.c

src/northbridge/intel/nehalem/nehalem.h

@@ -481,11 +481,6 @@ void init_iommu(void);
 
 #define LAC		0x87	/* Legacy Access Control */
 #define QPD0F1_SMRAM		0x4d	/* System Management RAM Control */
-#define  D_OPEN		(1 << 6)
-#define  D_CLS		(1 << 5)
-#define  D_LCK		(1 << 4)
-#define  G_SMRAME	(1 << 3)
-#define  C_BASE_SEG	((0 << 2) | (1 << 1) | (0 << 0))
 
 #define SKPAD		0xdc	/* Scratchpad Data */
 
@@ -583,12 +578,6 @@ void init_iommu(void);
 #ifndef __ASSEMBLER__
 static inline void barrier(void) { asm("" ::: "memory"); }
 
-struct ied_header {
-	char signature[10];
-	u32 size;
-	u8 reserved[34];
-} __attribute__ ((packed));
-
 #define PCI_DEVICE_ID_SB 0x0104
 #define PCI_DEVICE_ID_IB 0x0154
 

src/northbridge/intel/nehalem/northbridge.c

@@ -37,6 +37,7 @@
 #include <cbmem.h>
 #include "chip.h"
 #include "nehalem.h"
+#include <cpu/intel/smm/gen1/smi.h>
 
 static int bridge_revision_id = -1;
 
@@ -165,6 +166,18 @@ static void mc_read_resources(device_t dev)
 	add_fixed_resources(dev, 10);
 }
 
+void
+northbridge_get_tseg_base_and_size(u32 *tsegmb, u32 *tseg_size)
+{
+	device_t dev;
+	u32 bgsm;
+	dev = dev_find_slot(0, PCI_DEVFN(0, 0));
+
+	*tsegmb = pci_read_config32(dev, TSEG) & ~1;
+	bgsm = pci_read_config32(dev, D0F0_GTT_BASE);
+	*tseg_size = bgsm - *tsegmb;
+}
+
 static void mc_set_resources(device_t dev)
 {
 	/* And call the normal set_resources */

src/northbridge/intel/nehalem/smi.c

@@ -0,0 +1,14 @@
+#define __SIMPLE_DEVICE__
+
+#include <types.h>
+#include <string.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include "nehalem.h"
+
+#include <cpu/intel/smm/gen1/smi.h>
+
+void northbridge_write_smram(u8 smram)
+{
+	pcie_write_config8(PCI_DEV(QUICKPATH_BUS, 0, 1), QPD0F1_SMRAM, smram);
+}