libpayload arm64: update mmu translation table granule size, logic and macros
1. change mmu granule size from 64KB to 4KB 2. correct level 1 translation table creation logic 3. automatically calculate granule size related macros BRANCH=none BUG=none TEST=boot to kernel on oak board Change-Id: Ic62c7863dff53f566b82b68ff1d1ad9ec5d0698d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e5de7d942e42a8202fb879ce64b871864b1b9d38 Original-Change-Id: I78d7838921fa82a670e18ddc2de6d766dc7a2146 Original-Signed-off-by: Jimmy Huang <jimmy.huang@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/266010 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Commit-Queue: Yidi Lin <yidi.lin@mediatek.com> Reviewed-on: http://review.coreboot.org/10010 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
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Patrick Georgi
parent
dea4597bd4
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0fd3e79d0d
@@ -200,12 +200,24 @@ static uint64_t init_xlat_table(uint64_t base_addr,
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/*
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* L1 table lookup
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* If VA has bits more than 41, lookup starts at L1
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* If VA has bits more than L2 can resolve, lookup starts at L1
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* Assumption: we don't need L0 table in coreboot
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*/
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if (l1_index) {
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table = get_next_level_table(&table[l1_index]);
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if (!table)
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return 0;
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if (BITS_PER_VA > L1_ADDR_SHIFT) {
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if ((size >= L1_XLAT_SIZE) &&
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IS_ALIGNED(base_addr, (1UL << L1_ADDR_SHIFT))) {
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/* If block address is aligned and size is greater than
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* or equal to size addressed by each L1 entry, we can
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* directly store a block desc */
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desc = base_addr | BLOCK_DESC | attr;
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table[l1_index] = desc;
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/* L2 lookup is not required */
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return L1_XLAT_SIZE;
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} else {
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table = get_next_level_table(&table[l1_index]);
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if (!table)
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return 0;
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}
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}
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/*
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@@ -213,10 +225,11 @@ static uint64_t init_xlat_table(uint64_t base_addr,
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* If lookup was performed at L1, L2 table addr is obtained from L1 desc
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* else, lookup starts at ttbr address
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*/
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if (!l3_index && (size >= L2_XLAT_SIZE)) {
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if ((size >= L2_XLAT_SIZE) &&
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IS_ALIGNED(base_addr, (1UL << L2_ADDR_SHIFT))) {
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/*
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* If block address is aligned and size is greater than or equal
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* to 512MiB i.e. size addressed by each L2 entry, we can
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* to size addressed by each L2 entry, we can
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* directly store a block desc
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*/
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desc = base_addr | BLOCK_DESC | attr;
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@@ -369,7 +382,7 @@ void mmu_enable(void)
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/* Initialize TCR flags */
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raw_write_tcr_current(TCR_TOSZ | TCR_IRGN0_NM_WBWAC | TCR_ORGN0_NM_WBWAC |
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TCR_SH0_IS | TCR_TG0_64KB | TCR_PS_64GB |
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TCR_SH0_IS | TCR_TG0_4KB | TCR_PS_64GB |
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TCR_TBI_USED);
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/* Initialize TTBR */
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