From 0b4298c24288f65a6b315864bf5b44ef54cfb30b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sun, 29 Sep 2019 21:17:46 +0300 Subject: [PATCH 01/21] intel/pci_devs: Regroup PCI xx_DEVID entries MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I953e9a7746232b4c40deca55eb6cb3bd7af91496 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/35727 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/baytrail/include/soc/pci_devs.h | 69 +++++++-------- src/soc/intel/braswell/include/soc/pci_devs.h | 64 +++++++------- .../intel/denverton_ns/include/soc/pci_devs.h | 83 ++++++++++--------- .../intel/fsp_baytrail/include/soc/pci_devs.h | 76 ++++++++--------- .../fsp_broadwell_de/include/soc/pci_devs.h | 44 +++++----- src/southbridge/intel/fsp_rangeley/pci_devs.h | 39 ++++----- 6 files changed, 192 insertions(+), 183 deletions(-) diff --git a/src/soc/intel/baytrail/include/soc/pci_devs.h b/src/soc/intel/baytrail/include/soc/pci_devs.h index 4b344f8c64..71a0e53ce1 100644 --- a/src/soc/intel/baytrail/include/soc/pci_devs.h +++ b/src/soc/intel/baytrail/include/soc/pci_devs.h @@ -21,131 +21,132 @@ /* SoC transaction router */ #define SOC_DEV 0x0 #define SOC_FUNC 0 -# define SOC_DEVID 0x0f00 /* Graphics and Display */ #define GFX_DEV 0x2 #define GFX_FUNC 0 -# define GFX_DEVID 0x0f31 /* SDIO Port */ #define SDIO_DEV 0x11 #define SDIO_FUNC 0 -# define SDIO_DEVID 0x0f15 /* SD Port */ #define SD_DEV 0x12 #define SD_FUNC 0 -# define SD_DEVID 0x0f16 /* SATA */ #define SATA_DEV 0x13 #define SATA_FUNC 0 -#define IDE1_DEVID 0x0f20 -#define IDE2_DEVID 0x0f21 -#define AHCI1_DEVID 0x0f22 -#define AHCI2_DEVID 0x0f23 /* xHCI */ #define XHCI_DEV 0x14 #define XHCI_FUNC 0 -# define XHCI_DEVID 0x0f35 /* LPE Audio */ #define LPE_DEV 0x15 #define LPE_FUNC 0 -# define LPE_DEVID 0x0f28 /* MMC Port */ #define MMC_DEV 0x17 #define MMC_FUNC 0 -# define MMC_DEVID 0x0f50 /* Serial IO 1 */ #define SIO1_DEV 0x18 # define SIO_DMA1_DEV SIO1_DEV # define SIO_DMA1_FUNC 0 -# define SIO_DMA1_DEVID 0x0f40 # define I2C1_DEV SIO1_DEV # define I2C1_FUNC 1 -# define I2C1_DEVID 0x0f41 # define I2C2_DEV SIO1_DEV # define I2C2_FUNC 2 -# define I2C2_DEVID 0x0f42 # define I2C3_DEV SIO1_DEV # define I2C3_FUNC 3 -# define I2C3_DEVID 0x0f43 # define I2C4_DEV SIO1_DEV # define I2C4_FUNC 4 -# define I2C4_DEVID 0x0f44 # define I2C5_DEV SIO1_DEV # define I2C5_FUNC 5 -# define I2C5_DEVID 0x0f45 # define I2C6_DEV SIO1_DEV # define I2C6_FUNC 6 -# define I2C6_DEVID 0x0f46 # define I2C7_DEV SIO1_DEV # define I2C7_FUNC 7 -# define I2C7_DEVID 0x0f47 /* Trusted Execution Engine */ #define TXE_DEV 0x1a #define TXE_FUNC 0 -# define TXE_DEVID 0x0f18 /* HD Audio */ #define HDA_DEV 0x1b #define HDA_FUNC 0 -# define HDA_DEVID 0x0f04 /* PCIe Ports */ #define PCIE_DEV 0x1c # define PCIE_PORT1_DEV PCIE_DEV # define PCIE_PORT1_FUNC 0 -# define PCIE_PORT1_DEVID 0x0f48 # define PCIE_PORT2_DEV PCIE_DEV # define PCIE_PORT2_FUNC 1 -# define PCIE_PORT2_DEVID 0x0f4a # define PCIE_PORT3_DEV PCIE_DEV # define PCIE_PORT3_FUNC 2 -# define PCIE_PORT3_DEVID 0x0f4c # define PCIE_PORT4_DEV PCIE_DEV # define PCIE_PORT4_FUNC 3 -# define PCIE_PORT4_DEVID 0x0f4e /* EHCI */ #define EHCI_DEV 0x1d #define EHCI_FUNC 0 -# define EHCI_DEVID 0x0f34 /* Serial IO 2 */ #define SIO2_DEV 0x1e # define SIO_DMA2_DEV SIO2_DEV # define SIO_DMA2_FUNC 0 -# define SIO_DMA2_DEVID 0x0f06 # define PWM1_DEV SIO2_DEV # define PWM1_FUNC 1 -# define PWM1_DEVID 0x0f08 # define PWM2_DEV SIO2_DEV # define PWM2_FUNC 2 -# define PWM2_DEVID 0x0f09 # define HSUART1_DEV SIO2_DEV # define HSUART1_FUNC 3 -# define HSUART1_DEVID 0x0f0a # define HSUART2_DEV SIO2_DEV # define HSUART2_FUNC 4 -# define HSUART2_DEVID 0x0f0c # define SPI_DEV SIO2_DEV # define SPI_FUNC 5 -# define SPI_DEVID 0xf0e /* Platform Controller Unit */ #define PCU_DEV 0x1f # define LPC_DEV PCU_DEV # define LPC_FUNC 0 -# define LPC_DEVID 0x0f1c # define SMBUS_DEV PCU_DEV # define SMBUS_FUNC 3 -# define SMBUS_DEVID 0x0f12 + +#define SOC_DEVID 0x0f00 +#define GFX_DEVID 0x0f31 +#define SDIO_DEVID 0x0f15 +#define SD_DEVID 0x0f16 +#define IDE1_DEVID 0x0f20 +#define IDE2_DEVID 0x0f21 +#define AHCI1_DEVID 0x0f22 +#define AHCI2_DEVID 0x0f23 +#define XHCI_DEVID 0x0f35 +#define LPE_DEVID 0x0f28 +#define MMC_DEVID 0x0f50 +#define SIO_DMA1_DEVID 0x0f40 +#define I2C1_DEVID 0x0f41 +#define I2C2_DEVID 0x0f42 +#define I2C3_DEVID 0x0f43 +#define I2C4_DEVID 0x0f44 +#define I2C5_DEVID 0x0f45 +#define I2C6_DEVID 0x0f46 +#define I2C7_DEVID 0x0f47 +#define TXE_DEVID 0x0f18 +#define HDA_DEVID 0x0f04 +#define PCIE_PORT1_DEVID 0x0f48 +#define PCIE_PORT2_DEVID 0x0f4a +#define PCIE_PORT3_DEVID 0x0f4c +#define PCIE_PORT4_DEVID 0x0f4e +#define EHCI_DEVID 0x0f34 +#define SIO_DMA2_DEVID 0x0f06 +#define PWM1_DEVID 0x0f08 +#define PWM2_DEVID 0x0f09 +#define HSUART1_DEVID 0x0f0a +#define HSUART2_DEVID 0x0f0c +#define SPI_DEVID 0xf0e +#define LPC_DEVID 0x0f1c +#define SMBUS_DEVID 0x0f12 #endif /* _BAYTRAIL_PCI_DEVS_H_ */ diff --git a/src/soc/intel/braswell/include/soc/pci_devs.h b/src/soc/intel/braswell/include/soc/pci_devs.h index 8b06aff8f6..854b858e7f 100644 --- a/src/soc/intel/braswell/include/soc/pci_devs.h +++ b/src/soc/intel/braswell/include/soc/pci_devs.h @@ -23,99 +23,76 @@ /* SoC transaction router */ #define SOC_DEV 0x0 #define SOC_FUNC 0 -# define SOC_DEVID 0x2280 /* Graphics and Display */ #define GFX_DEV 0x2 #define GFX_FUNC 0 -# define GFX_DEVID 0x22b1 /* P-Unit DPTF */ #define PUNIT_DEV 0xB #define PUNIT_FUNC 0 -#define PUNIT_DEVID 0x22DC /* MMC Port */ #define MMC_DEV 0x10 #define MMC_FUNC 0 -# define MMC_DEVID 0x2294 /* SDIO Port */ #define SDIO_DEV 0x11 #define SDIO_FUNC 0 -# define SDIO_DEVID 0x2295 /* SD Port */ #define SD_DEV 0x12 #define SD_FUNC 0 -# define SD_DEVID 0x2296 /* SATA */ #define SATA_DEV 0x13 #define SATA_FUNC 0 -#define AHCI1_DEVID 0x22a3 /* xHCI */ #define XHCI_DEV 0x14 #define XHCI_FUNC 0 -#define XHCI_DEVID 0x22b5 /* LPE Audio */ #define LPE_DEV 0x15 #define LPE_FUNC 0 -# define LPE_DEVID 0x22a8 /* Serial IO 1 */ #define SIO1_DEV 0x18 # define SIO_DMA1_DEV SIO1_DEV # define SIO_DMA1_FUNC 0 -# define SIO_DMA1_DEVID 0x22c0 # define I2C1_DEV SIO1_DEV # define I2C1_FUNC 1 -# define I2C1_DEVID 0x22c1 # define I2C2_DEV SIO1_DEV # define I2C2_FUNC 2 -# define I2C2_DEVID 0x22c2 # define I2C3_DEV SIO1_DEV # define I2C3_FUNC 3 -# define I2C3_DEVID 0x22c3 # define I2C4_DEV SIO1_DEV # define I2C4_FUNC 4 -# define I2C4_DEVID 0x22c4 # define I2C5_DEV SIO1_DEV # define I2C5_FUNC 5 -# define I2C5_DEVID 0x22c5 # define I2C6_DEV SIO1_DEV # define I2C6_FUNC 6 -# define I2C6_DEVID 0x22c6 # define I2C7_DEV SIO1_DEV # define I2C7_FUNC 7 -# define I2C7_DEVID 0x22c7 /* Trusted Execution Engine */ #define TXE_DEV 0x1a #define TXE_FUNC 0 -# define TXE_DEVID 0x2298 /* HD Audio */ #define HDA_DEV 0x1b #define HDA_FUNC 0 -# define HDA_DEVID 0x2284 /* PCIe Ports */ #define PCIE_DEV 0x1c # define PCIE_PORT1_DEV PCIE_DEV # define PCIE_PORT1_FUNC 0 -# define PCIE_PORT1_DEVID 0x22c8 # define PCIE_PORT2_DEV PCIE_DEV # define PCIE_PORT2_FUNC 1 -# define PCIE_PORT2_DEVID 0x22ca # define PCIE_PORT3_DEV PCIE_DEV # define PCIE_PORT3_FUNC 2 -# define PCIE_PORT3_DEVID 0x22cc # define PCIE_PORT4_DEV PCIE_DEV # define PCIE_PORT4_FUNC 3 -# define PCIE_PORT4_DEVID 0x22ce /* Total number of ROOT PORTS */ #define MAX_ROOT_PORTS_BSW 4 @@ -123,34 +100,59 @@ #define SIO2_DEV 0x1e # define SIO_DMA2_DEV SIO2_DEV # define SIO_DMA2_FUNC 0 -# define SIO_DMA2_DEVID 0x2286 # define PWM1_DEV SIO2_DEV # define PWM1_FUNC 1 -# define PWM1_DEVID 0x2288 # define PWM2_DEV SIO2_DEV # define PWM2_FUNC 2 -# define PWM2_DEVID 0x2289 # define HSUART1_DEV SIO2_DEV # define HSUART1_FUNC 3 -# define HSUART1_DEVID 0x228a # define HSUART2_DEV SIO2_DEV # define HSUART2_FUNC 4 -# define HSUART2_DEVID 0x228c # define SPI_DEV SIO2_DEV # define SPI_FUNC 5 -# define SPI_DEVID 0x228e /* Platform Controller Unit */ #define PCU_DEV 0x1f # define LPC_DEV PCU_DEV # define LPC_FUNC 0 -# define LPC_DEVID 0x229c # define SMBUS_DEV PCU_DEV # define SMBUS_FUNC 3 -# define SMBUS_DEVID 0x0f12 /* PCH SCC Device Modes */ #define PCH_DISABLED 0 #define PCH_PCI_MODE 1 #define PCH_ACPI_MODE 2 + +#define SOC_DEVID 0x2280 +#define GFX_DEVID 0x22b1 +#define PUNIT_DEVID 0x22DC +#define MMC_DEVID 0x2294 +#define SDIO_DEVID 0x2295 +#define SD_DEVID 0x2296 +#define AHCI1_DEVID 0x22a3 +#define XHCI_DEVID 0x22b5 +#define LPE_DEVID 0x22a8 +#define SIO_DMA1_DEVID 0x22c0 +#define I2C1_DEVID 0x22c1 +#define I2C2_DEVID 0x22c2 +#define I2C3_DEVID 0x22c3 +#define I2C4_DEVID 0x22c4 +#define I2C5_DEVID 0x22c5 +#define I2C6_DEVID 0x22c6 +#define I2C7_DEVID 0x22c7 +#define TXE_DEVID 0x2298 +#define HDA_DEVID 0x2284 +#define PCIE_PORT1_DEVID 0x22c8 +#define PCIE_PORT2_DEVID 0x22ca +#define PCIE_PORT3_DEVID 0x22cc +#define PCIE_PORT4_DEVID 0x22ce +#define SIO_DMA2_DEVID 0x2286 +#define PWM1_DEVID 0x2288 +#define PWM2_DEVID 0x2289 +#define HSUART1_DEVID 0x228a +#define HSUART2_DEVID 0x228c +#define SPI_DEVID 0x228e +#define LPC_DEVID 0x229c +#define SMBUS_DEVID 0x0f12 + #endif /* _SOC_PCI_DEVS_H_ */ diff --git a/src/soc/intel/denverton_ns/include/soc/pci_devs.h b/src/soc/intel/denverton_ns/include/soc/pci_devs.h index a8a6283f10..faa4d927f5 100644 --- a/src/soc/intel/denverton_ns/include/soc/pci_devs.h +++ b/src/soc/intel/denverton_ns/include/soc/pci_devs.h @@ -34,157 +34,116 @@ /* SoC transaction router */ #define SA_DEV 0x0 #define SA_FUNC 0 -#define SA_DEVID 0x1980 -#define SA_DEVID_DNVAD 0x1995 #define SOC_DEV SA_DEV #define SOC_FUNC SA_FUNC -#define SOC_DEVID SA_DEVID /* RAS */ #define RAS_DEV 0x4 #define RAS_FUNC 0 -#define RAS_DEVID 0x19a1 /* Root Complex Event Collector */ #define RCEC_DEV 0x5 #define RCEC_FUNC 0 -#define RCEC_DEVID 0x19a2 /* Virtual Root Port 2 */ #define VRP2_DEV 0x6 #define VRP2_FUNC 0 -#define VRP2_DEVID 0x19a3 /* PCIe Root Ports */ #define PCIE_DEV 0x09 #define MAX_PCIE_PORT 0x8 #define PCIE_PORT1_DEV 0x09 #define PCIE_PORT1_FUNC 0 -#define PCIE_PORT1_DEVID 0x19a4 #define PCIE_PORT2_DEV 0x0a #define PCIE_PORT2_FUNC 0 -#define PCIE_PORT2_DEVID 0x19a5 #define PCIE_PORT3_DEV 0x0b #define PCIE_PORT3_FUNC 0 -#define PCIE_PORT3_DEVID 0x19a6 #define PCIE_PORT4_DEV 0x0c #define PCIE_PORT4_FUNC 0 -#define PCIE_PORT4_DEVID 0x19a7 #define PCIE_PORT5_DEV 0x0e #define PCIE_PORT5_FUNC 0 -#define PCIE_PORT5_DEVID 0x19a8 #define PCIE_PORT6_DEV 0x0f #define PCIE_PORT6_FUNC 0 -#define PCIE_PORT6_DEVID 0x19a9 #define PCIE_PORT7_DEV 0x10 #define PCIE_PORT7_FUNC 0 -#define PCIE_PORT7_DEVID 0x19aa #define PCIE_PORT8_DEV 0x11 #define PCIE_PORT8_FUNC 0 -#define PCIE_PORT8_DEVID 0x19ab /* SMBUS 2 */ #define SMBUS2_DEV 0x12 #define SMBUS2_FUNC 0 -#define SMBUS2_DEVID 0x19ac /* SATA */ #define SATA_DEV 0x13 #define SATA_FUNC 0 -#define AHCI_DEVID 0x19b2 #define SATA2_DEV 0x14 #define SATA2_FUNC 0 -#define AHCI2_DEVID 0x19c2 /* xHCI */ #define XHCI_DEV 0x15 #define XHCI_FUNC 0 -#define XHCI_DEVID 0x19d0 /* Virtual Root Port 0 */ #define VRP0_DEV 0x16 #define VRP0_FUNC 0 -#define VRP0_DEVID 0x19d1 /* Virtual Root Port 1 */ #define VRP1_DEV 0x17 #define VRP1_FUNC 0 -#define VRP1_DEVID 0x19d2 /* CSME */ #define ME_HECI_DEV 0x18 #define ME_HECI1_DEV ME_HECI_DEV #define ME_HECI1_FUNC 0 -#define ME_HECI1_DEVID 0x19d3 #define ME_HECI2_DEV ME_HECI_DEV #define ME_HECI2_FUNC 1 -#define ME_HECI2_DEVID 0x19d4 #define ME_IEDR_DEV ME_HECI_DEV #define ME_IEDR_FUNC 2 -#define ME_IEDR_DEVID 0x19ea #define ME_MEKT_DEV ME_HECI_DEV #define ME_MEKT_FUNC 3 -#define ME_MEKT_DEVID 0x19d5 #define ME_HECI3_DEV ME_HECI_DEV #define ME_HECI3_FUNC 4 -#define ME_HECI3_DEVID 0x19d6 /* HSUART */ #define HSUART_DEV 0x1a -#define HSUART_DEVID 0x19d8 #define HSUART1_DEV HSUART_DEV #define HSUART1_FUNC 0 -#define HSUART1_DEVID HSUART_DEVID #define HSUART2_DEV HSUART_DEV #define HSUART2_FUNC 1 -#define HSUART2_DEVID HSUART_DEVID #define HSUART3_DEV HSUART_DEV #define HSUART3_FUNC 2 -#define HSUART3_DEVID HSUART_DEVID /* IE */ #define IE_HECI_DEV 0x1b #define IE_HECI1_DEV IE_HECI_DEV #define IE_HECI1_FUNC 0 -#define IE_HECI1_DEVID 0x19e5 #define IE_HECI2_DEV IE_HECI_DEV #define IE_HECI2_FUNC 1 -#define IE_HECI2_DEVID 0x19e6 #define IE_IEDR_DEV IE_HECI_DEV #define IE_IEDR_FUNC 2 -#define IE_IEDR_DEVID 0x19e7 #define IE_MEKT_DEV IE_HECI_DEV #define IE_MEKT_FUNC 3 -#define IE_MEKT_DEVID 0x19e8 #define IE_HECI3_DEV IE_HECI_DEV #define IE_HECI3_FUNC 4 -#define IE_HECI3_DEVID 0x19e9 /* MMC Port */ #define MMC_DEV 0x1c #define MMC_FUNC 0 -#define MMC_DEVID 0x19db /* Platform Controller Unit */ #define PCU_DEV 0x1f #define LPC_DEV PCU_DEV #define LPC_FUNC 0 -#define LPC_DEVID 0x19dc #define P2SB_DEV PCU_DEV #define P2SB_FUNC 1 -#define P2SB_DEVID 0x19dd #define PMC_DEV PCU_DEV #define PMC_FUNC 2 -#define PMC_DEVID 0x19de #define SMBUS_DEV PCU_DEV #define SMBUS_FUNC 4 -#define SMBUS_DEVID 0x19df #define SPI_DEV PCU_DEV #define SPI_FUNC 5 -#define SPI_DEVID 0x19e0 #define NPK_DEV PCU_DEV #define NPK_FUNC 7 -#define NPK_DEVID 0x19e1 /* TODO - New added */ #define SA_DEV_SLOT_ROOT 0x00 @@ -199,4 +158,46 @@ #define PCH_DEV_LPC _PCH_DEV(LPC, 0) #define PCH_DEV_SPI _PCH_DEV(LPC, 5) +#define SA_DEVID 0x1980 +#define SA_DEVID_DNVAD 0x1995 +#define SOC_DEVID SA_DEVID +#define RAS_DEVID 0x19a1 +#define RCEC_DEVID 0x19a2 +#define VRP2_DEVID 0x19a3 +#define PCIE_PORT1_DEVID 0x19a4 +#define PCIE_PORT2_DEVID 0x19a5 +#define PCIE_PORT3_DEVID 0x19a6 +#define PCIE_PORT4_DEVID 0x19a7 +#define PCIE_PORT5_DEVID 0x19a8 +#define PCIE_PORT6_DEVID 0x19a9 +#define PCIE_PORT7_DEVID 0x19aa +#define PCIE_PORT8_DEVID 0x19ab +#define SMBUS2_DEVID 0x19ac +#define AHCI_DEVID 0x19b2 +#define AHCI2_DEVID 0x19c2 +#define XHCI_DEVID 0x19d0 +#define VRP0_DEVID 0x19d1 +#define VRP1_DEVID 0x19d2 +#define ME_HECI1_DEVID 0x19d3 +#define ME_HECI2_DEVID 0x19d4 +#define ME_IEDR_DEVID 0x19ea +#define ME_MEKT_DEVID 0x19d5 +#define ME_HECI3_DEVID 0x19d6 +#define HSUART_DEVID 0x19d8 +#define HSUART1_DEVID HSUART_DEVID +#define HSUART2_DEVID HSUART_DEVID +#define HSUART3_DEVID HSUART_DEVID +#define IE_HECI1_DEVID 0x19e5 +#define IE_HECI2_DEVID 0x19e6 +#define IE_IEDR_DEVID 0x19e7 +#define IE_MEKT_DEVID 0x19e8 +#define IE_HECI3_DEVID 0x19e9 +#define MMC_DEVID 0x19db +#define LPC_DEVID 0x19dc +#define P2SB_DEVID 0x19dd +#define PMC_DEVID 0x19de +#define SMBUS_DEVID 0x19df +#define SPI_DEVID 0x19e0 +#define NPK_DEVID 0x19e1 + #endif /* _DENVERTON_NS_PCI_DEVS_H_ */ diff --git a/src/soc/intel/fsp_baytrail/include/soc/pci_devs.h b/src/soc/intel/fsp_baytrail/include/soc/pci_devs.h index 5cca5ca8db..a6e37dcc96 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/pci_devs.h +++ b/src/soc/intel/fsp_baytrail/include/soc/pci_devs.h @@ -26,48 +26,38 @@ /* SoC transaction router */ #define SOC_DEV 0x0 #define SOC_FUNC 0 -# define SOC_DEVID 0x0f00 # define SOC_DEV_FUNC PCI_DEVFN(SOC_DEV,SOC_FUNC) /* Graphics and Display */ #define GFX_DEV 0x2 #define GFX_FUNC 0 -# define GFX_DEVID 0x0f31 # define GFX_DEV_FUNC PCI_DEVFN(GFX_DEV,GFX_FUNC) /* MIPI */ #define MIPI_DEV 0x3 #define MIPI_FUNC 0 -# define MIPI_DEVID 0x0f38 # define MIPI_DEV_FUNC PCI_DEVFN(MIPI_DEV,MIPI_FUNC) /* SDIO Port */ #define EMMC_DEV 0x10 #define EMMC_FUNC 0 -# define EMMC_DEVID 0x0f14 # define EMMC_DEV_FUNC PCI_DEVFN(EMMC_DEV,EMMC_FUNC) /* SDIO Port */ #define SDIO_DEV 0x11 #define SDIO_FUNC 0 -# define SDIO_DEVID 0x0f15 # define SDIO_DEV_FUNC PCI_DEVFN(SDIO_DEV,SDIO_FUNC) /* SD Port */ #define SD_DEV 0x12 #define SD_FUNC 0 -# define SD_DEVID 0x0f16 # define SD_DEV_FUNC PCI_DEVFN(SD_DEV,SD_FUNC) /* SATA */ #define SATA_DEV 0x13 #define SATA_FUNC 0 -# define IDE1_DEVID 0x0f20 -# define IDE2_DEVID 0x0f21 -# define AHCI1_DEVID 0x0f22 -# define AHCI2_DEVID 0x0f23 # define SATA_MA 0x84 # define SATA_MAP 0x90 # define SATA_PSC 0x92 @@ -84,7 +74,6 @@ /* xHCI */ #define XHCI_DEV 0x14 #define XHCI_FUNC 0 -# define XHCI_DEVID 0x0f35 # define XHCI_FUS_REG 0xE0 # define XHCI_FUNC_DISABLE (1 << 0) # define XHCI_USB2PR_REG 0xD0 @@ -93,47 +82,36 @@ /* LPE Audio */ #define LPE_DEV 0x15 #define LPE_FUNC 0 -# define LPE_DEVID 0x0f28 # define LPE_DEV_FUNC PCI_DEVFN(LPE_DEV,LPE_FUNC) /* OTG */ #define OTG_DEV 0x16 #define OTG_FUNC 0 -# define OTG_DEVID 0x0f37 # define OTG_DEV_FUNC PCI_DEVFN(LPE_DEV,LPE_FUNC) /* MMC Port */ #define MMC45_DEV 0x17 #define MMC45_FUNC 0 -# define MMC45_DEVID 0x0f50 # define MMC45_DEV_FUNC PCI_DEVFN(MMC45_DEV,MMC45_FUNC) /* Serial IO 1 */ #define SIO1_DEV 0x18 # define SIO_DMA1_DEV SIO1_DEV # define SIO_DMA1_FUNC 0 -# define SIO_DMA1_DEVID 0x0f40 # define I2C1_DEV SIO1_DEV # define I2C1_FUNC 1 -# define I2C1_DEVID 0x0f41 # define I2C2_DEV SIO1_DEV # define I2C2_FUNC 2 -# define I2C2_DEVID 0x0f42 # define I2C3_DEV SIO1_DEV # define I2C3_FUNC 3 -# define I2C3_DEVID 0x0f43 # define I2C4_DEV SIO1_DEV # define I2C4_FUNC 4 -# define I2C4_DEVID 0x0f44 # define I2C5_DEV SIO1_DEV # define I2C5_FUNC 5 -# define I2C5_DEVID 0x0f45 # define I2C6_DEV SIO1_DEV # define I2C6_FUNC 6 -# define I2C6_DEVID 0x0f46 # define I2C7_DEV SIO1_DEV # define I2C7_FUNC 7 -# define I2C7_DEVID 0x0f47 # define SIO_DMA1_DEV_FUNC PCI_DEVFN(SIO_DMA1_DEV,SIO_DMA1_FUNC) # define I2C1_DEV_FUNC PCI_DEVFN(I2C1_DEV,I2C1_FUNC) # define I2C2_DEV_FUNC PCI_DEVFN(I2C2_DEV,I2C2_FUNC) @@ -146,13 +124,11 @@ /* Trusted Execution Engine */ #define TXE_DEV 0x1a #define TXE_FUNC 0 -# define TXE_DEVID 0x0f18 # define TXE_DEV_FUNC PCI_DEVFN(TXE_DEV,TXE_FUNC) /* HD Audio */ #define HDA_DEV 0x1b #define HDA_FUNC 0 -# define HDA_DEVID 0x0f04 # define HDA_DEV_FUNC PCI_DEVFN(HDA_DEV,HDA_FUNC) # define HDA_AZUBAR 0x14 # define HDA_MMLA 0x64 @@ -165,16 +141,12 @@ #define PCIE_DEV 0x1c # define PCIE_PORT1_DEV PCIE_DEV # define PCIE_PORT1_FUNC 0 -# define PCIE_PORT1_DEVID 0x0f48 # define PCIE_PORT2_DEV PCIE_DEV # define PCIE_PORT2_FUNC 1 -# define PCIE_PORT2_DEVID 0x0f4a # define PCIE_PORT3_DEV PCIE_DEV # define PCIE_PORT3_FUNC 2 -# define PCIE_PORT3_DEVID 0x0f4c # define PCIE_PORT4_DEV PCIE_DEV # define PCIE_PORT4_FUNC 3 -# define PCIE_PORT4_DEVID 0x0f4e # define PCIE_PORT1_DEV_FUNC PCI_DEVFN(PCIE_DEV,PCIE_PORT1_FUNC) # define PCIE_PORT2_DEV_FUNC PCI_DEVFN(PCIE_DEV,PCIE_PORT2_FUNC) # define PCIE_PORT3_DEV_FUNC PCI_DEVFN(PCIE_DEV,PCIE_PORT3_FUNC) @@ -183,29 +155,22 @@ /* EHCI */ #define EHCI_DEV 0x1d #define EHCI_FUNC 0 -# define EHCI_DEVID 0x0f34 # define EHCI_DEV_FUNC PCI_DEVFN(EHCI_DEV,EHCI_FUNC) /* Serial IO 2 */ #define SIO2_DEV 0x1e # define SIO_DMA2_DEV SIO2_DEV # define SIO_DMA2_FUNC 0 -# define SIO_DMA2_DEVID 0x0f06 # define PWM1_DEV SIO2_DEV # define PWM1_FUNC 1 -# define PWM1_DEVID 0x0f08 # define PWM2_DEV SIO2_DEV # define PWM2_FUNC 2 -# define PWM2_DEVID 0x0f09 # define HSUART1_DEV SIO2_DEV # define HSUART1_FUNC 3 -# define HSUART1_DEVID 0x0f0a # define HSUART2_DEV SIO2_DEV # define HSUART2_FUNC 4 -# define HSUART2_DEVID 0x0f0c # define SPI_DEV SIO2_DEV # define SPI_FUNC 5 -# define SPI_DEVID 0xf0e # define SIO_DMA2_DEV_FUNC PCI_DEVFN(SIO_DMA2_DEV,SIO_DMA2_FUNC) # define PWM1_DEV_FUNC PCI_DEVFN(PWM1_DEV,PWM1_FUNC) # define PWM2_DEV_FUNC PCI_DEVFN(PWM2_DEV,PWM2_FUNC) @@ -218,10 +183,8 @@ #define PCU_DEV 0x1f # define LPC_DEV PCU_DEV # define LPC_FUNC 0 -# define LPC_DEVID 0x0f1c # define SMBUS_DEV PCU_DEV # define SMBUS_FUNC 3 -# define SMBUS_DEVID 0x0f12 # define LPC_DEV_FUNC PCI_DEVFN(LPC_DEV,LPC_FUNC) # define LPC_BDF PCI_DEV(0, LPC_DEV, LPC_FUNC) # define SMBUS_DEV_FUNC PCI_DEVFN(SMBUS_DEV,SMBUS_FUNC) @@ -234,4 +197,43 @@ #define START_ROMSTAGE_TIMESTAMP_LOCATION HDA_MMLA_BDFO #define BEFORE_RAMINIT_TIMESTAMP_LOCATION SATA_MA_BDFO + +#define SOC_DEVID 0x0f00 +#define GFX_DEVID 0x0f31 +#define MIPI_DEVID 0x0f38 +#define EMMC_DEVID 0x0f14 +#define SDIO_DEVID 0x0f15 +#define SD_DEVID 0x0f16 +#define IDE1_DEVID 0x0f20 +#define IDE2_DEVID 0x0f21 +#define AHCI1_DEVID 0x0f22 +#define AHCI2_DEVID 0x0f23 +#define XHCI_DEVID 0x0f35 +#define LPE_DEVID 0x0f28 +#define OTG_DEVID 0x0f37 +#define MMC45_DEVID 0x0f50 +#define SIO_DMA1_DEVID 0x0f40 +#define I2C1_DEVID 0x0f41 +#define I2C2_DEVID 0x0f42 +#define I2C3_DEVID 0x0f43 +#define I2C4_DEVID 0x0f44 +#define I2C5_DEVID 0x0f45 +#define I2C6_DEVID 0x0f46 +#define I2C7_DEVID 0x0f47 +#define TXE_DEVID 0x0f18 +#define HDA_DEVID 0x0f04 +#define PCIE_PORT1_DEVID 0x0f48 +#define PCIE_PORT2_DEVID 0x0f4a +#define PCIE_PORT3_DEVID 0x0f4c +#define PCIE_PORT4_DEVID 0x0f4e +#define EHCI_DEVID 0x0f34 +#define SIO_DMA2_DEVID 0x0f06 +#define PWM1_DEVID 0x0f08 +#define PWM2_DEVID 0x0f09 +#define HSUART1_DEVID 0x0f0a +#define HSUART2_DEVID 0x0f0c +#define SPI_DEVID 0xf0e +#define LPC_DEVID 0x0f1c +#define SMBUS_DEVID 0x0f12 + #endif /* _BAYTRAIL_PCI_DEVS_H_ */ diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/pci_devs.h b/src/soc/intel/fsp_broadwell_de/include/soc/pci_devs.h index ad8d80a71b..8de4d19982 100644 --- a/src/soc/intel/fsp_broadwell_de/include/soc/pci_devs.h +++ b/src/soc/intel/fsp_broadwell_de/include/soc/pci_devs.h @@ -24,8 +24,6 @@ #define SOC_DEV 0 #define SOC_FUNC 0 -#define SOC_DEVID 0x2F00 -#define SOC_DEVID_ES2 0x6F00 #define SOC_DEV_FUNC PCI_DEVFN(SOC_DEV, SOC_FUNC) /* DMI2/PCIe link to PCH */ @@ -53,24 +51,19 @@ #define VTD_DEV 5 #define VTD_FUNC 0 -#define VTD_DEVID 0x6f28 #define VTD_DEV_FUNC PCI_DEVFN(VTD_DEV, VTD_FUNC) #define VTD_PCI_DEV PCI_DEV(BUS0, VTD_DEV, VTD_FUNC) #define LPC_DEV 31 #define LPC_FUNC 0 -#define LPC_DEVID 0x8C42 -#define LPC_DEVID_ES2 0x8C54 #define LPC_DEV_FUNC PCI_DEVFN(LPC_DEV, LPC_FUNC) #define SATA_DEV 31 #define SATA_FUNC 2 -#define AHCI_DEVID 0x8C02 #define SATA_DEV_FUNC PCI_DEVFN(SATA_DEV, SATA_FUNC) #define SMBUS_DEV 31 #define SMBUS_FUNC 3 -#define SMBUS_DEVID 0x8C22 #define SMBUS_DEV_FUNC PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC) #define SATA2_DEV 31 @@ -79,17 +72,14 @@ #define EHCI1_DEV 29 #define EHCI1_FUNC 0 -#define EHCI1_DEVID 0x8C26 #define EHCI1_DEV_FUNC PCI_DEVFN(EHCI_DEV1, EHCI_FUNC1) #define EHCI2_DEV 26 #define EHCI2_FUNC 0 -#define EHCI2_DEVID 0x8C2D #define EHCI2_DEV_FUNC PCI_DEVFN(EHCI_DEV2, EHCI_FUNC2) #define XHCI_DEV 20 #define XHCI_FUNC 0 -#define XHCI_DEVID 0x8C31 #define XHCI_FUS_REG 0xE0 #define XHCI_FUNC_DISABLE (1 << 0) #define XHCI_USB2PR_REG 0xD0 @@ -97,45 +87,34 @@ #define GBE_DEV 25 #define GBE_FUNC 0 -#define GBE_DEVID 0x8C33 #define GBE_DEV_FUNC PCI_DEVFN(GBE_DEV, GBE_FUNC) #define ME_DEV 22 #define ME_FUNC 0 -#define ME_DEVID 0x8C3A #define ME_DEV_FUNC PCI_DEVFN(ME_DEV, ME_FUNC) #define HDA_DEV 27 #define HDA_FUNC 0 -#define HDA_DEVID 0x8C20 #define HDA_DEV_FUNC PCI_DEVFN(HDA_DEV, HDA_FUNC) /* Ports from PCH block with adjustable burification settings */ #define PCIE_DEV 28 #define PCIE_PORT1_DEV PCIE_DEV #define PCIE_PORT1_FUNC 0 -#define PCIE_PORT1_DEVID 0x8C10 #define PCIE_PORT2_DEV PCIE_DEV #define PCIE_PORT2_FUNC 1 -#define PCIE_PORT2_DEVID 0x8C12 #define PCIE_PORT3_DEV PCIE_DEV #define PCIE_PORT3_FUNC 2 -#define PCIE_PORT3_DEVID 0x8C14 #define PCIE_PORT4_DEV PCIE_DEV #define PCIE_PORT4_FUNC 3 -#define PCIE_PORT4_DEVID 0x8C16 #define PCIE_PORT5_DEV PCIE_DEV #define PCIE_PORT5_FUNC 4 -#define PCIE_PORT5_DEVID 0x8C18 #define PCIE_PORT6_DEV PCIE_DEV #define PCIE_PORT6_FUNC 5 -#define PCIE_PORT6_DEVID 0x8C1A #define PCIE_PORT7_DEV PCIE_DEV #define PCIE_PORT7_FUNC 6 -#define PCIE_PORT7_DEVID 0x8C1C #define PCIE_PORT8_DEV PCIE_DEV #define PCIE_PORT8_FUNC 7 -#define PCIE_PORT8_DEVID 0x8C1E #define PCIE_PORT1_DEV_FUNC PCI_DEVFN(PCIE_DEV, PCIE_PORT1_FUNC) #define PCIE_PORT2_DEV_FUNC PCI_DEVFN(PCIE_DEV, PCIE_PORT2_FUNC) #define PCIE_PORT3_DEV_FUNC PCI_DEVFN(PCIE_DEV, PCIE_PORT3_FUNC) @@ -161,4 +140,27 @@ #define UBOX_DEV 16 #define UBOX_FUNC 7 + +#define SOC_DEVID 0x2F00 +#define SOC_DEVID_ES2 0x6F00 +#define VTD_DEVID 0x6f28 +#define LPC_DEVID 0x8C42 +#define LPC_DEVID_ES2 0x8C54 +#define AHCI_DEVID 0x8C02 +#define SMBUS_DEVID 0x8C22 +#define EHCI1_DEVID 0x8C26 +#define EHCI2_DEVID 0x8C2D +#define XHCI_DEVID 0x8C31 +#define GBE_DEVID 0x8C33 +#define ME_DEVID 0x8C3A +#define HDA_DEVID 0x8C20 +#define PCIE_PORT1_DEVID 0x8C10 +#define PCIE_PORT2_DEVID 0x8C12 +#define PCIE_PORT3_DEVID 0x8C14 +#define PCIE_PORT4_DEVID 0x8C16 +#define PCIE_PORT5_DEVID 0x8C18 +#define PCIE_PORT6_DEVID 0x8C1A +#define PCIE_PORT7_DEVID 0x8C1C +#define PCIE_PORT8_DEVID 0x8C1E + #endif /* _SOC_PCI_DEVS_H_ */ diff --git a/src/southbridge/intel/fsp_rangeley/pci_devs.h b/src/southbridge/intel/fsp_rangeley/pci_devs.h index 29f9085a7b..89f3c5c230 100644 --- a/src/southbridge/intel/fsp_rangeley/pci_devs.h +++ b/src/southbridge/intel/fsp_rangeley/pci_devs.h @@ -26,87 +26,71 @@ /* Host Bridge */ #define SOC_DEV 0x0 #define SOC_FUNC 0 -# define SOC_DEVID 0x1f08 # define SOC_DEV_FUNC PCI_DEVFN(SOC_DEV,SOC_FUNC) /* PCIE Port 1 */ #define PCIE_PORT1_DEV 0x1 #define PCIE_PORT1_FUNC 0 -# define PCIE_PORT1_DEVID 0x1f10 # define PCIE_PORT1_DEV_FUNC PCI_DEVFN(PCIE_PORT1_DEV,PCIE_PORT1_FUNC) /* PCIE Port 2 */ #define PCIE_PORT2_DEV 0x2 #define PCIE_PORT2_FUNC 0 -# define PCIE_PORT2_DEVID 0x1f11 # define PCIE_PORT2_DEV_FUNC PCI_DEVFN(PCIE_PORT2_DEV,PCIE_PORT2_FUNC) /* PCIE Port 3 */ #define PCIE_PORT3_DEV 0x3 #define PCIE_PORT3_FUNC 0 -# define PCIE_PORT3_DEVID 0x1f12 # define PCIE_PORT3_DEV_FUNC PCI_DEVFN(PCIE_PORT3_DEV,PCIE_PORT3_FUNC) /* PCIE Port 4 */ #define PCIE_PORT4_DEV 0x4 #define PCIE_PORT4_FUNC 0 -# define PCIE_PORT4_DEVID 0x1f13 # define PCIE_PORT4_DEV_FUNC PCI_DEVFN(PCIE_PORT4_DEV,PCIE_PORT4_FUNC) /* Host Bridge, Fabric, and RAS Registers */ #define HOST_BRIDGE_DEV 0xe #define HOST_BRIDGE_FUNC 0 -# define HOST_BRIDGE_DEVID 0x1f14 # define HOST_BRIDGE_DEV_FUNC PCI_DEVFN(HOST_BRIDGE_DEV,HOST_BRIDGE_FUNC) /* Root Complex Event Collector (RCEC) */ #define RCEC_DEV 0xf #define RCEC_FUNC 0 -# define RCEC_DEVID 0x1f16 # define RCEC_DEV_FUNC PCI_DEVFN(RCEC_DEV,RCEC_FUNC) /* SMBus 2.0 1 */ #define SMBUS1_DEV 0x13 #define SMBUS1_FUNC 0 -# define SMBUS1_DEVID 0x1f15 # define SMBUS1_DEV_FUNC PCI_DEVFN(SMBUS1_DEV,SMBUS1_FUNC) /* Gigabit Ethernet (GbE) */ #define GBE_DEV 0x14 -#define GBE_DEVID 0x1f41 #define GBE1_DEV GBE_DEV #define GBE1_FUNC 0 -# define GBE1_DEVID GBE_DEVID # define GBE1_DEV_FUNC PCI_DEVFN(GBE1_DEV,GBE1_FUNC) #define GBE2_DEV GBE_DEV #define GBE2_FUNC 1 -# define GBE2_DEVID GBE_DEVID # define GBE2_DEV_FUNC PCI_DEVFN(GBE2_DEV,GBE2_FUNC) #define GBE3_DEV GBE_DEV #define GBE3_FUNC 2 -# define GBE3_DEVID GBE_DEVID # define GBE3_DEV_FUNC PCI_DEVFN(GBE3_DEV,GBE3_FUNC) #define GBE4_DEV GBE_DEV #define GBE4_FUNC 3 -# define GBE4_DEVID GBE_DEVID # define GBE4_DEV_FUNC PCI_DEVFN(GBE4_DEV,GBE4_FUNC) /* USB 2.0 */ #define USB2_DEV 0x16 #define USB2_FUNC 0 -# define USB2_DEVID 0x1f2c # define USB2_DEV_FUNC PCI_DEVFN(USB2_DEV,USB2_FUNC) /* SATA Gen 2 */ #define SATA2_DEV 0x17 #define SATA2_FUNC 0 -# define SATA2_DEVID 0x1f22 # define SATA2_DEV_FUNC PCI_DEVFN(SATA2_DEV,SATA2_FUNC) /* SATA Gen 3 */ #define SATA3_DEV 0x18 #define SATA3_FUNC 0 -# define SATA3_DEVID 0x1f32 # define SATA3_DEV_FUNC PCI_DEVFN(SATA3_DEV,SATA3_FUNC) /* Platform Control Unit (PCU) */ @@ -115,20 +99,37 @@ /* Low Pin Count (LPC/ISA) */ #define LPC_DEV PCU_DEV #define LPC_FUNC 0 -# define LPC_DEVID 0x1f38 # define LPC_DEV_FUNC PCI_DEVFN(LPC_DEV,LPC_FUNC) # define LPC_BDF PCI_DEV(BUS0, LPC_DEV, LPC_FUNC) /* SMBus 2.0 0 */ #define SMBUS0_DEV PCU_DEV #define SMBUS0_FUNC 3 -# define SMBUS0_DEVID 0x1f3c # define SMBUS0_DEV_FUNC PCI_DEVFN(SMBUS0_DEV,SMBUS0_FUNC) /* Intel QuickAssist Integrated Accelerator (IQIA) */ #define IQAT_DEV 0xb #define IQAT_FUNC 0 -# define IQAT_DEVID 0x1f18 # define IQAT_DEV_FUNC PCI_DEVFN(IQAT_DEV,IQAT_FUNC) +#define SOC_DEVID 0x1f08 +#define PCIE_PORT1_DEVID 0x1f10 +#define PCIE_PORT2_DEVID 0x1f11 +#define PCIE_PORT3_DEVID 0x1f12 +#define PCIE_PORT4_DEVID 0x1f13 +#define HOST_BRIDGE_DEVID 0x1f14 +#define RCEC_DEVID 0x1f16 +#define SMBUS1_DEVID 0x1f15 +#define GBE_DEVID 0x1f41 +#define GBE1_DEVID GBE_DEVID +#define GBE2_DEVID GBE_DEVID +#define GBE3_DEVID GBE_DEVID +#define GBE4_DEVID GBE_DEVID +#define USB2_DEVID 0x1f2c +#define SATA2_DEVID 0x1f22 +#define SATA3_DEVID 0x1f32 +#define LPC_DEVID 0x1f38 +#define SMBUS0_DEVID 0x1f3c +#define IQAT_DEVID 0x1f18 + #endif /* _RANGELEY_PCI_DEVS_H_ */ From 85b6c66c834502989bbbcb2a696452b72ce4f1aa Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Mon, 30 Sep 2019 22:40:53 +0300 Subject: [PATCH 02/21] intel/skylake: Refactor IRQ assignments MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When creating the IRQ routing, referenced device and function number are always of the same PCI device. Change-Id: Ifc4795245187f8d70650242a56e6ce771ef2167a Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/35735 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/soc/intel/skylake/include/soc/interrupt.h | 10 +- src/soc/intel/skylake/irq.c | 124 ++++++------------ 2 files changed, 46 insertions(+), 88 deletions(-) diff --git a/src/soc/intel/skylake/include/soc/interrupt.h b/src/soc/intel/skylake/include/soc/interrupt.h index 015ea76ec6..bc654981f1 100644 --- a/src/soc/intel/skylake/include/soc/interrupt.h +++ b/src/soc/intel/skylake/include/soc/interrupt.h @@ -31,11 +31,11 @@ #define PCH_PHRC 7 #define PCH_MAX_IRQ_CONFIG 8 -#define DEVICE_INT_CONFIG(dev, func, line, irqno) {\ - .Device = dev, \ - .Function = func, \ - .IntX = line, \ - .Irq = irqno } +#define DEVICE_INT_CONFIG(devfn, line, irqno) {\ + .Device = PCI_SLOT(devfn), \ + .Function = PCI_FUNC(devfn), \ + .IntX = (line), \ + .Irq = (irqno) } #define no_int 0 #define int_A 1 diff --git a/src/soc/intel/skylake/irq.c b/src/soc/intel/skylake/irq.c index ddaffda796..6e6d6555c2 100644 --- a/src/soc/intel/skylake/irq.c +++ b/src/soc/intel/skylake/irq.c @@ -28,194 +28,152 @@ static const SI_PCH_DEVICE_INTERRUPT_CONFIG devintconfig[] = { * cAVS(Audio, Voice, Speech), INTA is default, programmed in * PciCfgSpace 3Dh */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_LPC, - PCI_FUNC(PCH_DEVFN_HDA), int_A, cAVS_INTA_IRQ), + DEVICE_INT_CONFIG(PCH_DEVFN_HDA, int_A, cAVS_INTA_IRQ), /* * SMBus Controller, no default value, programmed in * PciCfgSpace 3Dh */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_LPC, - PCI_FUNC(PCH_DEVFN_SMBUS), int_A, SMBUS_INTA_IRQ), + DEVICE_INT_CONFIG(PCH_DEVFN_SMBUS, int_A, SMBUS_INTA_IRQ), /* GbE Controller, INTA is default, programmed in PciCfgSpace 3Dh */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_LPC, - PCI_FUNC(PCH_DEVFN_GBE), int_A, GbE_INTA_IRQ), + DEVICE_INT_CONFIG(PCH_DEVFN_GBE, int_A, GbE_INTA_IRQ), /* TraceHub, INTA is default, RO register */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_LPC, - PCI_FUNC(PCH_DEVFN_TRACEHUB), int_A, - TRACE_HUB_INTA_IRQ), + DEVICE_INT_CONFIG(PCH_DEVFN_TRACEHUB, int_A, TRACE_HUB_INTA_IRQ), /* * SerialIo: UART #0, INTA is default, * programmed in PCR[SERIALIO] + PCICFGCTRL[7] */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, - PCI_FUNC(PCH_DEVFN_UART0), int_A, LPSS_UART0_IRQ), + DEVICE_INT_CONFIG(PCH_DEVFN_UART0, int_A, LPSS_UART0_IRQ), /* * SerialIo: UART #1, INTA is default, * programmed in PCR[SERIALIO] + PCICFGCTRL[8] */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, - PCI_FUNC(PCH_DEVFN_UART1), int_B, LPSS_UART1_IRQ), + DEVICE_INT_CONFIG(PCH_DEVFN_UART1, int_B, LPSS_UART1_IRQ), /* * SerialIo: SPI #0, INTA is default, * programmed in PCR[SERIALIO] + PCICFGCTRL[10] */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, - PCI_FUNC(PCH_DEVFN_GSPI0), int_C, LPSS_SPI0_IRQ), + DEVICE_INT_CONFIG(PCH_DEVFN_GSPI0, int_C, LPSS_SPI0_IRQ), /* * SerialIo: SPI #1, INTA is default, * programmed in PCR[SERIALIO] + PCICFGCTRL[11] */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, - PCI_FUNC(PCH_DEVFN_GSPI1), int_D, LPSS_SPI1_IRQ), + DEVICE_INT_CONFIG(PCH_DEVFN_GSPI1, int_D, LPSS_SPI1_IRQ), /* SCS: eMMC (SKL PCH-LP Only) */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, - PCI_FUNC(PCH_DEVFN_EMMC), int_B, eMMC_IRQ), + DEVICE_INT_CONFIG(PCH_DEVFN_EMMC, int_B, eMMC_IRQ), /* SCS: SDIO (SKL PCH-LP Only) */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, - PCI_FUNC(PCH_DEVFN_SDIO), int_C, SDIO_IRQ), + DEVICE_INT_CONFIG(PCH_DEVFN_SDIO, int_C, SDIO_IRQ), /* SCS: SDCard (SKL PCH-LP Only) */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, - PCI_FUNC(PCH_DEVFN_SDCARD), int_D, SD_IRQ), + DEVICE_INT_CONFIG(PCH_DEVFN_SDCARD, int_D, SD_IRQ), /* PCI Express Port, INT is default, * programmed in PciCfgSpace + FCh */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE_1, - PCI_FUNC(PCH_DEVFN_PCIE9), int_A, PCIE_9_IRQ), - DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE_1, - PCI_FUNC(PCH_DEVFN_PCIE10), int_B, PCIE_10_IRQ), - DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE_1, - PCI_FUNC(PCH_DEVFN_PCIE11), int_C, PCIE_11_IRQ), - DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE_1, - PCI_FUNC(PCH_DEVFN_PCIE12), int_D, PCIE_12_IRQ), + DEVICE_INT_CONFIG(PCH_DEVFN_PCIE9, int_A, PCIE_9_IRQ), + DEVICE_INT_CONFIG(PCH_DEVFN_PCIE10, int_B, PCIE_10_IRQ), + DEVICE_INT_CONFIG(PCH_DEVFN_PCIE11, int_C, PCIE_11_IRQ), + DEVICE_INT_CONFIG(PCH_DEVFN_PCIE12, int_D, PCIE_12_IRQ), /* * PCI Express Port 1, INT is default, * programmed in PciCfgSpace + FCh */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, - PCI_FUNC(PCH_DEVFN_PCIE1), int_A, PCIE_1_IRQ), + DEVICE_INT_CONFIG(PCH_DEVFN_PCIE1, int_A, PCIE_1_IRQ), /* * PCI Express Port 2, INT is default, * programmed in PciCfgSpace + FCh */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, - PCI_FUNC(PCH_DEVFN_PCIE2), int_B, PCIE_2_IRQ), + DEVICE_INT_CONFIG(PCH_DEVFN_PCIE2, int_B, PCIE_2_IRQ), /* * PCI Express Port 3, INT is default, * programmed in PciCfgSpace + FCh */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, - PCI_FUNC(PCH_DEVFN_PCIE3), int_C, PCIE_3_IRQ), + DEVICE_INT_CONFIG(PCH_DEVFN_PCIE3, int_C, PCIE_3_IRQ), /* * PCI Express Port 4, INT is default, * programmed in PciCfgSpace + FCh */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, - PCI_FUNC(PCH_DEVFN_PCIE4), int_D, PCIE_4_IRQ), + DEVICE_INT_CONFIG(PCH_DEVFN_PCIE4, int_D, PCIE_4_IRQ), /* * PCI Express Port 5, INT is default, * programmed in PciCfgSpace + FCh */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, - PCI_FUNC(PCH_DEVFN_PCIE5), int_A, PCIE_5_IRQ), + DEVICE_INT_CONFIG(PCH_DEVFN_PCIE5, int_A, PCIE_5_IRQ), /* * PCI Express Port 6, INT is default, * programmed in PciCfgSpace + FCh */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, - PCI_FUNC(PCH_DEVFN_PCIE6), int_B, PCIE_6_IRQ), + DEVICE_INT_CONFIG(PCH_DEVFN_PCIE6, int_B, PCIE_6_IRQ), /* * PCI Express Port 7, INT is default, * programmed in PciCfgSpace + FCh */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, - PCI_FUNC(PCH_DEVFN_PCIE7), int_C, PCIE_7_IRQ), + DEVICE_INT_CONFIG(PCH_DEVFN_PCIE7, int_C, PCIE_7_IRQ), /* * PCI Express Port 8, INT is default, * programmed in PciCfgSpace + FCh */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, - PCI_FUNC(PCH_DEVFN_PCIE8), int_D, PCIE_8_IRQ), + DEVICE_INT_CONFIG(PCH_DEVFN_PCIE8, int_D, PCIE_8_IRQ), /* * SerialIo UART Controller #2, INTA is default, * programmed in PCR[SERIALIO] + PCICFGCTRL[9] */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO2, - PCI_FUNC(PCH_DEVFN_UART2), int_A, LPSS_UART2_IRQ), + DEVICE_INT_CONFIG(PCH_DEVFN_UART2, int_A, LPSS_UART2_IRQ), /* * SerialIo UART Controller #5, INTA is default, * programmed in PCR[SERIALIO] + PCICFGCTRL[6] */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO2, - PCI_FUNC(PCH_DEVFN_I2C5), int_B, LPSS_I2C5_IRQ), + DEVICE_INT_CONFIG(PCH_DEVFN_I2C5, int_B, LPSS_I2C5_IRQ), /* * SerialIo UART Controller #4, INTA is default, * programmed in PCR[SERIALIO] + PCICFGCTRL[5] */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO2, - PCI_FUNC(PCH_DEVFN_I2C4), int_C, LPSS_I2C4_IRQ), + DEVICE_INT_CONFIG(PCH_DEVFN_I2C4, int_C, LPSS_I2C4_IRQ), /* * SATA Controller, INTA is default, * programmed in PciCfgSpace + 3Dh */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_SATA, - PCI_FUNC(PCH_DEVFN_SATA), int_A, SATA_IRQ), + DEVICE_INT_CONFIG(PCH_DEVFN_SATA, int_A, SATA_IRQ), /* CSME: HECI #1 */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_CSE, - PCI_FUNC(PCH_DEVFN_CSE), int_A, HECI_1_IRQ), + DEVICE_INT_CONFIG(PCH_DEVFN_CSE, int_A, HECI_1_IRQ), /* CSME: HECI #2 */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_CSE, - PCI_FUNC(PCH_DEVFN_CSE_2), int_B, HECI_2_IRQ), + DEVICE_INT_CONFIG(PCH_DEVFN_CSE_2, int_B, HECI_2_IRQ), /* CSME: IDE-Redirection (IDE-R) */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_CSE, - PCI_FUNC(PCH_DEVFN_CSE_IDER), int_C, IDER_IRQ), + DEVICE_INT_CONFIG(PCH_DEVFN_CSE_IDER, int_C, IDER_IRQ), /* CSME: Keyboard and Text (KT) Redirection */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_CSE, - PCI_FUNC(PCH_DEVFN_CSE_KT), int_D, KT_IRQ), + DEVICE_INT_CONFIG(PCH_DEVFN_CSE_KT, int_D, KT_IRQ), /* CSME: HECI #3 */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_CSE, - PCI_FUNC(PCH_DEVFN_CSE_3), int_A, HECI_3_IRQ), + DEVICE_INT_CONFIG(PCH_DEVFN_CSE_3, int_A, HECI_3_IRQ), /* * SerialIo I2C Controller #0, INTA is default, * programmed in PCR[SERIALIO] + PCICFGCTRL[1] */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO1, - PCI_FUNC(PCH_DEVFN_I2C0), int_A, LPSS_I2C0_IRQ), + DEVICE_INT_CONFIG(PCH_DEVFN_I2C0, int_A, LPSS_I2C0_IRQ), /* * SerialIo I2C Controller #1, INTA is default, * programmed in PCR[SERIALIO] + PCICFGCTRL[2] */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO1, - PCI_FUNC(PCH_DEVFN_I2C1), int_B, LPSS_I2C1_IRQ), + DEVICE_INT_CONFIG(PCH_DEVFN_I2C1, int_B, LPSS_I2C1_IRQ), /* * SerialIo I2C Controller #2, INTA is default, * programmed in PCR[SERIALIO] + PCICFGCTRL[3] */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO1, - PCI_FUNC(PCH_DEVFN_I2C2), int_C, LPSS_I2C2_IRQ), + DEVICE_INT_CONFIG(PCH_DEVFN_I2C2, int_C, LPSS_I2C2_IRQ), /* * SerialIo I2C Controller #3, INTA is default, * programmed in PCR[SERIALIO] + PCICFGCTRL[4] */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO1, - PCI_FUNC(PCH_DEVFN_I2C3), int_D, LPSS_I2C3_IRQ), + DEVICE_INT_CONFIG(PCH_DEVFN_I2C3, int_D, LPSS_I2C3_IRQ), /* * USB 3.0 xHCI Controller, no default value, * programmed in PciCfgSpace 3Dh */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_XHCI, - PCI_FUNC(PCH_DEVFN_XHCI), int_A, XHCI_IRQ), + DEVICE_INT_CONFIG(PCH_DEVFN_XHCI, int_A, XHCI_IRQ), /* USB Device Controller (OTG) */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_XHCI, - PCI_FUNC(PCH_DEVFN_USBOTG), int_B, OTG_IRQ), + DEVICE_INT_CONFIG(PCH_DEVFN_USBOTG, int_B, OTG_IRQ), /* Thermal Subsystem */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_XHCI, - PCI_FUNC(PCH_DEVFN_THERMAL), int_C, THERMAL_IRQ), + DEVICE_INT_CONFIG(PCH_DEVFN_THERMAL, int_C, THERMAL_IRQ), /* Camera IO Host Controller */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_XHCI, - PCI_FUNC(PCH_DEVFN_CIO), int_A, CIO_INTA_IRQ), + DEVICE_INT_CONFIG(PCH_DEVFN_CIO, int_A, CIO_INTA_IRQ), /* Integrated Sensor Hub */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_ISH, - PCI_FUNC(PCH_DEVFN_ISH), int_A, ISH_IRQ) + DEVICE_INT_CONFIG(PCH_DEVFN_ISH, int_A, ISH_IRQ) }; void soc_irq_settings(FSP_SIL_UPD *params) From da33b75e7dfcd74dfa5b3d9bdd5869c546101ac3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Mon, 30 Sep 2019 12:58:33 +0300 Subject: [PATCH 03/21] intel/quark: Drop xx_DEV_FUNC MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Intel adopted xx_DEVFN_xx naming for macros expanding to PCI_DEVFN() starting with apollolake. The ones named xx_DEV_FUNC are being renamed, or dropped, if they were generally not used at all for a platform. Change-Id: Ice1062d10b793dcbeb5b2ce9e2788fd3b6b6250b Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/35728 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/quark/include/soc/pci_devs.h | 4 ---- 1 file changed, 4 deletions(-) diff --git a/src/soc/intel/quark/include/soc/pci_devs.h b/src/soc/intel/quark/include/soc/pci_devs.h index 1e17402868..a24f28f7ff 100644 --- a/src/soc/intel/quark/include/soc/pci_devs.h +++ b/src/soc/intel/quark/include/soc/pci_devs.h @@ -50,25 +50,21 @@ #define SIO2_DEV 0x15 #define I2CGPIO_DEV SIO2_DEV #define I2CGPIO_FUNC 2 -#define I2CGPIO_DEV_FUNC PCI_DEVFN(I2CGPIO_DEV, I2CGPIO_FUNC) #define I2CGPIO_BDF PCI_DEV(PCI_BUS_NUMBER_QNC, I2CGPIO_DEV, I2CGPIO_FUNC) /* PCIe Ports */ #define PCIE_DEV 0x17 #define PCIE_PORT0_DEV PCIE_DEV #define PCIE_PORT0_FUNC 0 -#define PCIE_PORT0_DEV_FUNC PCI_DEVFN(PCIE_DEV, PCIE_PORT0_FUNC) #define PCIE_PORT0_BDF PCI_DEV(PCI_BUS_NUMBER_QNC, PCIE_DEV, PCIE_PORT0_FUNC) #define PCIE_PORT1_DEV PCIE_DEV #define PCIE_PORT1_FUNC 1 -#define PCIE_PORT1_DEV_FUNC PCI_DEVFN(PCIE_DEV, PCIE_PORT1_FUNC) #define PCIE_PORT1_BDF PCI_DEV(PCI_BUS_NUMBER_QNC, PCIE_DEV, PCIE_PORT1_FUNC) /* Platform Controller Unit */ #define LPC_DEV PCI_DEVICE_NUMBER_QNC_LPC #define LPC_FUNC PCI_FUNCTION_NUMBER_QNC_LPC -#define LPC_DEV_FUNC PCI_DEVFN(LPC_DEV, LPC_FUNC) #define LPC_BDF PCI_DEV(PCI_BUS_NUMBER_QNC, LPC_DEV, LPC_FUNC) #endif /* _QUARK_PCI_DEVS_H_ */ From f47c32a12d778c6e4f8cd93cfe1f83d2ca2bb9be Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Sun, 29 Sep 2019 22:46:48 -0600 Subject: [PATCH 04/21] util/crossgcc: Add patch for __alloca missing on ubuntu 18.04 Bring this over from the HEADS repo. Signed-off-by: Martin Roth Change-Id: I36dc9860f4c4a2675fd3fa24fa3e534215ceb43e Reviewed-on: https://review.coreboot.org/c/coreboot/+/35724 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- util/crossgcc/patches/make-4.2.1_alloca.patch | 11 +++++++++++ 1 file changed, 11 insertions(+) create mode 100644 util/crossgcc/patches/make-4.2.1_alloca.patch diff --git a/util/crossgcc/patches/make-4.2.1_alloca.patch b/util/crossgcc/patches/make-4.2.1_alloca.patch new file mode 100644 index 0000000000..61a3581f4a --- /dev/null +++ b/util/crossgcc/patches/make-4.2.1_alloca.patch @@ -0,0 +1,11 @@ +--- clean/make-4.2/glob/glob.c 2013-10-20 17:14:38.000000000 +0000 ++++ make-4.2/glob/glob.c 2018-09-18 10:16:03.860886356 +0000 +@@ -208,7 +208,7 @@ + #endif /* __GNU_LIBRARY__ || __DJGPP__ */ + + +-#if !defined __alloca && !defined __GNU_LIBRARY__ ++#if !defined __alloca && defined __GNU_LIBRARY__ + + # ifdef __GNUC__ + # undef alloca From f5fa96f9c34d5cd9fc2dd0bbdf955b9fffb85a3d Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Sat, 21 Sep 2019 17:39:30 -0700 Subject: [PATCH 05/21] buildgcc: Run aclocal before configure Ubuntu 19.04 will fail looking for aclocal-1.15 if the scripts are not regenerated because 19.04 ships with 1.16. There are not enough eyes to roll when working with GNU autotools. Signed-off-by: Stefan Reinauer Signed-off-by: Martin Roth Change-Id: I4aa9f520499930ffc984ab0b0144c9c6b2e544a0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35522 Tested-by: build bot (Jenkins) --- util/crossgcc/buildgcc | 2 ++ 1 file changed, 2 insertions(+) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 9c10c7d56e..6c378ac7fd 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -893,9 +893,11 @@ build_LLVM() { } build_MAKE() { + ( cd ../${MAKE_DIR}/ && aclocal && autoconf ) CC="$(hostcc host)" CXX="$(hostcxx host)" CFLAGS="$HOSTCFLAGS" \ ../${MAKE_DIR}/configure --prefix="$TARGETDIR" --disable-nls \ || touch .failed + $MAKE -k clean # shellcheck disable=SC2086 $MAKE $JOBS || touch .failed $MAKE install DESTDIR=$DESTDIR || touch .failed From ce005dac6810e2964e7ff3a7552cad3e1791ae91 Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Fri, 1 Apr 2016 14:30:33 -0600 Subject: [PATCH 06/21] util/release: add gerrit stats script This tool downloads, caches and analyzes commits pushed to gerrit for a specified range of commits. Currently it only works over SSH. Data that is printed about the range of commits: CSV Data about each individual commit: - Commit ID - Commit Date - Author - Commiter - Submitter - Lines added - Lines removed - Title - Reviewers It then prints the analysis it did on the data: - Total Commits - Total lines added - Total lines removed - Total difference - Authors - Number of commits - Total Authors - Authors - Lines added - Authors - Lines removed - Reviewers - Number of patches reviewed - Submitters - Number of patches submitted The script relies on a number of perl modules which must be installed separately. Change-Id: I74896a97b5fe370c0b08562ac85d29435e438a31 Signed-off-by: Martin Roth Reviewed-on: https://review.coreboot.org/c/coreboot/+/14225 Reviewed-by: Stefan Reinauer Tested-by: Stefan Reinauer --- util/release/gerrit_stats.pl | 470 +++++++++++++++++++++++++++++++++++ 1 file changed, 470 insertions(+) create mode 100755 util/release/gerrit_stats.pl diff --git a/util/release/gerrit_stats.pl b/util/release/gerrit_stats.pl new file mode 100755 index 0000000000..acd56226d5 --- /dev/null +++ b/util/release/gerrit_stats.pl @@ -0,0 +1,470 @@ +#!/usr/bin/perl + +# +# This file is part of the coreboot project. +# +# Copyright (C) 2015 Google, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +package gerrit_stats; + +# To install any needed modules install the cpanm app, and use it to install the required modules: +# sudo cpan App::cpanminus +# sudo /usr/local/bin/cpanm JSON::Util Net::OpenSSH DateTime Devel::Size + +use strict; +use warnings; +use English qw( -no_match_vars ); +use File::Find; +use File::Path; +use Getopt::Long; +use Getopt::Std; +use JSON::Util; +use Net::OpenSSH; +use Data::Dumper qw(Dumper); +use DateTime; +use Devel::Size qw(size total_size); + +my $old_version; +my $new_version; +my $infodir="$ENV{'HOME'}/.commit_info/" . `git config -l | grep remote.origin.url | sed 's|.*@||' | sed 's|:.*||'`; +chomp($infodir); +my $URL_WITH_USER; +my $SKIP_GERRIT_CHECK; +my $print_commit_list = 1; + +#disable print buffering +$OUTPUT_AUTOFLUSH = 1; +binmode STDOUT, ":utf8"; + +Main(); + +#------------------------------------------------------------------------------- +# Main +#------------------------------------------------------------------------------- +sub Main { + check_arguments(); + + my %submitters = (); + my %authors = (); + my %owners = (); + my %reviewers = (); + my %author_added = (); + my %author_removed = (); + my $total_added = 0; + my $total_removed = 0; + my $number_of_commits = 0; + my $number_of_submitters = 0; + my $submit_epoch = ""; + my $first_submit_epoch = ""; + if (!$URL_WITH_USER) { + get_user() + } + + # make sure the versions exist + check_versions(); + + #fetch patches if needed. Get ids of first and last commits + my @commits = `git log --pretty=%h "$old_version..$new_version" 2>/dev/null`; + get_commits(@commits); + my $last_commit_id = $commits[0]; + my $first_commit_id = $commits[@commits - 1]; + chomp $last_commit_id; + chomp $first_commit_id; + + print "Statistics from commit $first_commit_id to commit $last_commit_id\n"; + print "Patch, Date, Owner, Author, Submitter, Inserted lines, Deleted lines, Subject, Reviewers\n"; + + #loop through all commits + for my $commit_id (@commits) { + $commit_id =~ s/^\s+|\s+$//g; + + my $submitter = ""; + my %patch_reviewers = (); + my $info; + my $owner; + my $author; + my $author_email; + my $inserted_lines = 0; + my $deleted_lines = 0; + my $subject; + + $number_of_commits++; + print "\"$commit_id\", "; + + #read the data file for the current commit + if (-f "$infodir/$commit_id" && -s "$infodir/$commit_id" > 20) { + open( my $HANDLE, "<", "$infodir/$commit_id" ) or die "Error: could not open file '$infodir/$commit_id'\n"; + $info = <$HANDLE>; + close $HANDLE; + + my $commit_info = JSON::Util->decode($info); + + #get the easy data + $owner = $commit_info->{'owner'}{'name'}; + if (! $owner) { + $owner = $commit_info->{'owner'}{'username'}; + } + if (! $owner) { + $owner = ""; + } + $author = $commit_info->{'currentPatchSet'}{'author'}{'name'}; + $author_email = $commit_info->{'currentPatchSet'}{'author'}{'email'}; + if (! $author) { + $author = $commit_info->{'currentPatchSet'}{'author'}{'username'}; + } + + $inserted_lines = $commit_info->{'currentPatchSet'}{'sizeInsertions'}; + $deleted_lines = $commit_info->{'currentPatchSet'}{'sizeDeletions'}; + $subject = $commit_info->{'subject'}; + + #get the patch's submitter + my $approvals = $commit_info->{'currentPatchSet'}{'approvals'}; + for my $approval (@$approvals) { + if ($approval->{'type'} eq "SUBM") { + $submit_epoch = $approval->{'grantedOn'}; + $submitter = $approval->{'by'}{'name'}; + } + } + + #get all the reviewers for all patch revisions + my $patchsets = $commit_info->{'patchSets'}; + for my $patch (@$patchsets) { + if (! $author) { + $author = $patch->{'author'}{'name'}; + } + my $approvals = $patch->{'approvals'}; + for my $approval (@$approvals) { + + if ( (! $submitter) && ($approval->{'type'} eq "SUBM")) { + $submit_epoch = $approval->{'grantedOn'}; + $submitter = $approval->{'by'}{'name'}; + } + + if ($approval->{'type'} eq "Code-Review") { + my $patch_reviewer = $approval->{'by'}{'name'}; + if ($patch_reviewer) { + if (exists $patch_reviewers{$patch_reviewer}) { + $patch_reviewers{$patch_reviewer}++; + } else { + $patch_reviewers{$patch_reviewer} = 1; + } + } + } + } + } + + } else { + # get the info from git + my $logline = `git log --pretty="%ct@@@%s@@@%an@@@%aE@@@%cn" $commit_id^..$commit_id --`; + $logline =~ m/^(.*)@@@(.*)@@@(.*)@@@(.*)@@@(.*)\n/; + ($submit_epoch, $subject, $author, $author_email, $submitter) = ($1, $2, $3, $4, $5); + $owner = $author; + $logline = `git log --pretty= --shortstat $commit_id^..$commit_id --`; + if ($logline =~ m/\s+(\d+)\s+insertion/) { + $inserted_lines = $1; + } + if ($logline =~ m/\s+(\d+)\s+deletion/) { + $deleted_lines = $1 * -1; + } + my @loglines = `git log $commit_id^..$commit_id -- | grep '\\sReviewed-by:'`; + for my $line (@loglines){ + if ($line =~ m/.*:\s+(.*)\sfrom_epoch(epoch => $submit_epoch); + $dt->set_time_zone( 'Europe/Paris' ); + my $submit_time = $dt->strftime('%Y/%m/%d %H:%M:%S'); + if (!$first_submit_epoch) { + $first_submit_epoch = $submit_epoch; + } + + #create the list of reviewers to print + my $reviewerlist = ""; + foreach my $reviewer (keys %patch_reviewers) { + if ($reviewerlist eq "") { + $reviewerlist = $reviewer; + } else { + $reviewerlist .= ", $reviewer"; + } + + if (exists $reviewers{$reviewer}) { + $reviewers{$reviewer}++; + } else { + $reviewers{$reviewer} = 1; + } + } + if (! $reviewerlist) { + $reviewerlist = "-" + } + + if ($print_commit_list) { + print "$submit_time, $owner, $author, $submitter, $inserted_lines, $deleted_lines, \"$subject\", \"$reviewerlist\"\n"; + } else { + print "$number_of_commits\n"; + } + $total_added += $inserted_lines; + $total_removed += $deleted_lines; + if (exists $owners{$owner}) { + $owners{$owner}++; + } else { + $owners{$owner} = 1; + } + + if (exists $authors{$author}{"num"}) { + $authors{$author}{"num"}++; + $author_added{$author} += $inserted_lines; + $author_removed{$author} += $deleted_lines; + $authors{$author}{"earliest_commit"}=$submit_time; + } else { + $authors{$author}{"num"} = 1; + $authors{$author}{"latest_commit"}=$submit_time; + $authors{$author}{"earliest_commit"}=$submit_time; + $author_added{$author} = $inserted_lines; + $author_removed{$author} = $deleted_lines; + } + if (! exists $authors{$author}{email} && $author_email) { + $authors{$author}{email} = "$author_email"; + } + } + my $Days = ($first_submit_epoch - $submit_epoch) / 86400; + if (($first_submit_epoch - $submit_epoch) % 86400) { + $Days += 1; + } + + print "- Total Commits: $number_of_commits\n"; + printf "- Average Commits per day: %.2f\n", $number_of_commits / $Days; + print "- Total lines added: $total_added\n"; + print "- Total lines removed: $total_removed\n"; + print "- Total difference: " . ($total_added + $total_removed) . "\n\n"; + + print "=== Authors - Number of commits ===\n"; + my $number_of_authors = 0; + foreach my $author (sort { $authors{$b}{num} <=> $authors{$a}{num} } (keys %authors) ) { + if (! exists $authors{$author}{"email"}) { + $authors{$author}{"email"} = "-"; + } + printf "%-25s %5d %-40s (%2.2f%%) {%s / %s}\n",$author, $authors{$author}{"num"}, $authors{$author}{"email"}, $authors{$author}{"num"} / $number_of_commits * 100, $authors{$author}{"latest_commit"}, $authors{$author}{"earliest_commit"}; + $number_of_authors++; + } + print "Total Authors: $number_of_authors\n\n"; + + print "=== Authors - Lines added ===\n"; + foreach my $author (sort { $author_added{$b} <=> $author_added{$a} } (keys %author_added) ) { + if ($author_added{$author}) { + printf "%-25s %5d (%2.3f%%)\n",$author, $author_added{$author}, $author_added{$author} / $total_added * 100; + } + } + print "\n"; + + print "=== Authors - Lines removed ===\n"; + foreach my $author (sort { $author_removed{$a} <=> $author_removed{$b} } (keys %author_removed) ) { + if ($author_removed{$author}) { + printf "%-25s %5d (%2.3f%%)\n",$author,$author_removed{$author} * -1, $author_removed{$author} / $total_removed * 100; + } + } + print "\n"; + + print "=== Reviewers - Number of patches reviewed ===\n"; + my $number_of_reviewers = 0; + foreach my $reviewer (sort { $reviewers{$b} <=> $reviewers{$a} } (keys %reviewers) ) { + printf "%-25s %5d (%2.3f%%)\n",$reviewer, $reviewers{$reviewer}, $reviewers{$reviewer} / $number_of_commits * 100; + $number_of_reviewers++; + } + print "Total Reviewers: $number_of_reviewers\n\n"; + + print "=== Submitters - Number of patches submitted ===\n"; + foreach my $submitter (sort { $submitters{$b} <=> $submitters{$a} } (keys %submitters) ) { + printf "%-25s %5d (%2.3f%%)\n",$submitter, $submitters{$submitter}, $submitters{$submitter} / $number_of_commits * 100; + } + print "Total Submitters: $number_of_submitters\n\n"; + + print "Commits, Ave, Added, Removed, Diff, Authors, Reviewers, Submitters\n"; + printf "$number_of_commits, %.2f, $total_added, $total_removed, " . ($total_added + $total_removed) . ", $number_of_authors, $number_of_reviewers, $number_of_submitters\n", $number_of_commits / $Days; +} + +#------------------------------------------------------------------------------- +#------------------------------------------------------------------------------- +sub check_versions { + `git cat-file -e $old_version^{commit} 2>/dev/null`; + if (${^CHILD_ERROR_NATIVE}){ + print "Error: Old version ($old_version) does not exist.\n"; + exit 1; + } + + `git cat-file -e $new_version^{commit} 2>/dev/null`; + if (${^CHILD_ERROR_NATIVE}){ + print "Error: New version ($new_version) does not exist.\n"; + exit 1; + } +} + +#------------------------------------------------------------------------------- +#------------------------------------------------------------------------------- +sub get_user { + my $url=`git config -l | grep remote.origin.url`; + + if ($url =~ /.*url=ssh:\/\/(\w+@[a-zA-Z][a-zA-Z0-9\.]+:\d+)/) + { + $URL_WITH_USER = $1; + } else { + print "Error: Could not get a ssh url with a username from gitconfig.\n"; + print " use the -u option to set a url.\n"; + exit 1; + } +} + +#------------------------------------------------------------------------------- +#------------------------------------------------------------------------------- +sub get_commits { + my @commits = @_; + my $submit_time = ""; + if (defined $SKIP_GERRIT_CHECK) { + return; + } + my $ssh = Net::OpenSSH->new("$URL_WITH_USER", ); + $ssh->error and die "Couldn't establish SSH connection to $URL_WITH_USER:". $ssh->error; + + print "Using URL: ssh://$URL_WITH_USER\n"; + + if (! -d $infodir) { + mkpath($infodir) + } + + for my $commit_id (@commits) { + $commit_id =~ s/^\s+|\s+$//g; + $submit_time = ""; + my $gerrit_review; + + # Quit if we've reeached the last coreboot commit supporting these queries + if ($commit_id =~ /^7309709/) { + last; + } + + if (-f "$infodir/$commit_id") { + $gerrit_review = 1; + } else { + $gerrit_review = `git log $commit_id^..$commit_id | grep '\\sReviewed-on:\\s'`; + } + + if ($gerrit_review && $commit_id && (! -f "$infodir/$commit_id") ) { + print "Downloading $commit_id"; + my @info = $ssh->capture("gerrit query --format=JSON --comments --files --current-patch-set --all-approvals --submit-records --dependencies commit:$commit_id"); + $ssh->error and die "remote ls command failed: " . $ssh->error; + + my $commit_info = JSON::Util->decode($info[0]); + my $rowcount = $commit_info->{'rowCount'}; + if (defined $rowcount && ($rowcount eq "0")) { + print " - no gerrit commit for that id.\n"; + open( my $HANDLE, ">", "$infodir/$commit_id" ) or die "Error: could not open file '$infodir/$commit_id'\n"; + print $HANDLE "No gerrit commit"; + close $HANDLE; + next; + } + my $approvals = $commit_info->{'currentPatchSet'}{'approvals'}; + + for my $approval (@$approvals) { + if ($approval->{'type'} eq "SUBM") { + $submit_time = $approval->{'grantedOn'} + } + } + my $dt=""; + if ($submit_time) { + $dt = DateTime->from_epoch(epoch => $submit_time); + } else { + print " - no submit time for that id.\n"; + open( my $HANDLE, ">", "$infodir/$commit_id" ) or die "Error: could not open file '$infodir/$commit_id'\n"; + print $HANDLE "No submit time"; + close $HANDLE; + + next; + } + + open( my $HANDLE, ">", "$infodir/$commit_id" ) or die "Error: could not open file '$infodir/$commit_id'\n"; + print $HANDLE $info[0]; + close $HANDLE; + + $dt->set_time_zone( 'Europe/Paris' ); + print " - submit time: " . $dt->strftime('%Y/%m/%d %H:%M:%S') . "\n"; + } elsif ($commit_id && (! -f "$infodir/$commit_id")) { + print "No gerrit commit for $commit_id\n"; + open( my $HANDLE, ">", "$infodir/$commit_id" ) or die "Error: could not open file '$infodir/$commit_id'\n"; + print $HANDLE "No gerrit commit"; + close $HANDLE; + } + } + print "\n"; +} + +#------------------------------------------------------------------------------- +# check_arguments parse the command line arguments +#------------------------------------------------------------------------------- +sub check_arguments { + my $show_usage = 0; + GetOptions( + 'help|?' => sub { usage() }, + 'url|u=s' => \$URL_WITH_USER, + 'skip|s' => \$SKIP_GERRIT_CHECK, + ); + # strip ssh:// from url if passed in. + if (defined $URL_WITH_USER) { + $URL_WITH_USER =~ s|ssh://||; + } + if (@ARGV) { + ($old_version, $new_version) = @ARGV; + } else { + usage(); + } +} + +#------------------------------------------------------------------------------- +# usage - Print the arguments for the user +#------------------------------------------------------------------------------- +sub usage { + print "gerrit_stats [Old version] [New version]\n"; + print "Old version should be a tag (4.1), a branch (origin/4.1), or a commit id\n"; + print "New version can be 'HEAD' a branch (origin/master) a tag (4.2), or a commit id\n"; + print " Options:\n"; + print " u | url [url] url with username.\n"; + print "Example: \"$0 -u Gaumless\@review.coreboot.org:29418 origin/4.1 4.2\"\n"; + exit(0); +} + +1; From d46bc604137f29905c4cb9f681803c93f77a8aa3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Mon, 30 Sep 2019 13:08:44 +0300 Subject: [PATCH 07/21] intel/fsp_baytrail: Drop some PCI scratchpad register definitions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit These were unused and somewhat cryptic, assumed purpose was to store pre-CBMEM timestamps in various PCI config space locations. Change-Id: I074294446501d49a9bd3c823a2a794c33f443168 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/35731 Reviewed-by: Aaron Durbin Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- .../intel/fsp_baytrail/include/soc/pci_devs.h | 25 ------------------- 1 file changed, 25 deletions(-) diff --git a/src/soc/intel/fsp_baytrail/include/soc/pci_devs.h b/src/soc/intel/fsp_baytrail/include/soc/pci_devs.h index a6e37dcc96..a920194a8a 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/pci_devs.h +++ b/src/soc/intel/fsp_baytrail/include/soc/pci_devs.h @@ -58,18 +58,8 @@ /* SATA */ #define SATA_DEV 0x13 #define SATA_FUNC 0 -# define SATA_MA 0x84 -# define SATA_MAP 0x90 -# define SATA_PSC 0x92 -# define SATA_SP 0xD0 -# define SATA_BIST1 0xE4 -# define SATA_BIST2 0xE8 # define SATA_DEV_FUNC PCI_DEVFN(SATA_DEV,SATA_FUNC) -#define SATA_MA_BDFO PCI_DEV(BUS0, SATA_DEV, SATA_FUNC), SATA_MA -#define SATA_SP_BDFO PCI_DEV(BUS0, SATA_DEV, SATA_FUNC), SATA_SP -#define SATA_BIST1_BDFO PCI_DEV(BUS0, SATA_DEV, SATA_FUNC), SATA_BIST1 -#define SATA_BIST2_BDFO PCI_DEV(BUS0, SATA_DEV, SATA_FUNC), SATA_BIST2 /* xHCI */ #define XHCI_DEV 0x14 @@ -130,12 +120,6 @@ #define HDA_DEV 0x1b #define HDA_FUNC 0 # define HDA_DEV_FUNC PCI_DEVFN(HDA_DEV,HDA_FUNC) -# define HDA_AZUBAR 0x14 -# define HDA_MMLA 0x64 -# define HDA_MMUA 0x68 -#define HDA_AZUBAR_BDFO PCI_DEV(BUS0, HDA_DEV, HDA_FUNC), HDA_AZUBAR -#define HDA_MMLA_BDFO PCI_DEV(BUS0, HDA_DEV, HDA_FUNC), HDA_MMLA -#define HDA_MMUA_BDFO PCI_DEV(BUS0, HDA_DEV, HDA_FUNC), HDA_MMUA /* PCIe Ports */ #define PCIE_DEV 0x1c @@ -189,15 +173,6 @@ # define LPC_BDF PCI_DEV(0, LPC_DEV, LPC_FUNC) # define SMBUS_DEV_FUNC PCI_DEVFN(SMBUS_DEV,SMBUS_FUNC) -#define INITIAL_TIMESTAMP_LOCATION HDA_MMUA_BDFO -#define BEFORE_CAR_TIMESTAMP_LOCATION SATA_BIST1_BDFO -#define ASM_BEFORE_CAR_TSC_LOC (0x80 << 24 | SATA_DEV_FUNC << 8 | SATA_BIST1) -#define AFTER_CAR_TIMESTAMP_LOCATION SATA_BIST2_BDFO -#define ASM_AFTER_CAR_TSC_LOC (0x80 << 24 | SATA_DEV_FUNC << 8 | SATA_BIST2) -#define START_ROMSTAGE_TIMESTAMP_LOCATION HDA_MMLA_BDFO -#define BEFORE_RAMINIT_TIMESTAMP_LOCATION SATA_MA_BDFO - - #define SOC_DEVID 0x0f00 #define GFX_DEVID 0x0f31 #define MIPI_DEVID 0x0f38 From 193eefb2e878f2c7032f4c6d100aee9d2d745279 Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Thu, 26 Sep 2019 16:11:12 +0000 Subject: [PATCH 08/21] Update vboot submodule to upstream master Updating from commit id e6700f4c: 2019-08-13 04:36:52 +0000 - (vboot: update vboot2 functions to use new vb2_error_t) to commit id b2c8984d: 2019-10-01 06:01:59 +0000 - (vboot: fix compile error with MOCK_TPM) This brings in 71 new commits. Change-Id: Id7cefa3ad5b30c955d18e469494fec32f6f58a48 Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/35315 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- 3rdparty/vboot | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/3rdparty/vboot b/3rdparty/vboot index e6700f4c70..b2c8984d37 160000 --- a/3rdparty/vboot +++ b/3rdparty/vboot @@ -1 +1 @@ -Subproject commit e6700f4c70fe72850ae4f3f5df19c9281ebcefc8 +Subproject commit b2c8984d37e378b2faad170d4ec9b378c0c2b145 From 4685e53fe6d1fc5ff2984635e46dfe4df3fddf4c Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Thu, 26 Sep 2019 16:11:08 +0000 Subject: [PATCH 09/21] Update opensbi submodule to upstream master Updating from commit id ce228ee: 2019-07-02 11:11:08 +0530 - (include: Bump-up version to 0.4) to commit id e561c63: 2019-10-02 17:03:58 +0530 - (lib: Fix coldboot race condition observed on emulators/simulators) This brings in 44 new commits. Change-Id: Ide6e3c2bb98e79750b40a9b8ca9f2f1d2c123628 Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/35314 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- 3rdparty/opensbi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/3rdparty/opensbi b/3rdparty/opensbi index ce228ee091..e561c63036 160000 --- a/3rdparty/opensbi +++ b/3rdparty/opensbi @@ -1 +1 @@ -Subproject commit ce228ee0919deb9957192d723eecc8aaae2697c6 +Subproject commit e561c6303639ed510183da25d3d54555a53371c9 From 22f009901dd0874909d66122ac2ad37d53d8d366 Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Thu, 26 Sep 2019 16:11:02 +0000 Subject: [PATCH 10/21] Update chromeec submodule to upstream master Updating from commit id 860fe2962: 2018-12-29 05:45:29 -0800 - (mt_scp/ipi: Support host command.) to commit id a1afae4e0: 2019-10-02 11:47:45 +0000 - (juniper: initial setup) This brings in 1723 new commits. Change-Id: Ieb4f00b21a4354bb634c3427c73260123b54ac2a Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/35624 Tested-by: build bot (Jenkins) Reviewed-by: Jacob Garber Reviewed-by: Stefan Reinauer --- 3rdparty/chromeec | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/3rdparty/chromeec b/3rdparty/chromeec index 860fe2962d..a1afae4e00 160000 --- a/3rdparty/chromeec +++ b/3rdparty/chromeec @@ -1 +1 @@ -Subproject commit 860fe2962d40ee901369d1dc67f4aa7a7a42ba4d +Subproject commit a1afae4e002a3eccd7835ac898259b0690e9e61a From 0b20b83b7da32fc96f41ca7fe92c920d36a05b05 Mon Sep 17 00:00:00 2001 From: Frans Hendriks Date: Tue, 1 Oct 2019 13:41:04 +0200 Subject: [PATCH 11/21] mb/facebook/fbg1701: Add mainboard_read_pcb_version() PCB version is determined using inb() in actual code. Create function mainboard_read_pcb_version to read pcb version. BUG=N/A TEST=Boot and verified on Facebook FBG-1701 Change-Id: I7c16627f468d84ca4ad2aab8bf9fb555f50dc23c Signed-off-by: Frans Hendriks Reviewed-on: https://review.coreboot.org/c/coreboot/+/35741 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/mainboard/facebook/fbg1701/mainboard.c | 10 ++++++++++ src/mainboard/facebook/fbg1701/mainboard.h | 1 + src/mainboard/facebook/fbg1701/ramstage.c | 6 +----- 3 files changed, 12 insertions(+), 5 deletions(-) diff --git a/src/mainboard/facebook/fbg1701/mainboard.c b/src/mainboard/facebook/fbg1701/mainboard.c index 8524b24000..a8cb34c744 100644 --- a/src/mainboard/facebook/fbg1701/mainboard.c +++ b/src/mainboard/facebook/fbg1701/mainboard.c @@ -16,7 +16,10 @@ * GNU General Public License for more details. */ +#include #include +#include "mainboard.h" +#include "onboard.h" /* * Declare the resources we are using @@ -36,6 +39,13 @@ static void mainboard_reserve_resources(struct device *dev) res->flags = IORESOURCE_IRQ | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } +/* Read PCB version */ +unsigned int mainboard_read_pcb_version(void) +{ + return ((inb(CPLD_PCB_VERSION_PORT) & CPLD_PCB_VERSION_MASK) >> + CPLD_PCB_VERSION_BIT); +} + /* * mainboard_enable is executed as first thing after * enumerate_buses(). diff --git a/src/mainboard/facebook/fbg1701/mainboard.h b/src/mainboard/facebook/fbg1701/mainboard.h index e161da0396..3cace548b3 100644 --- a/src/mainboard/facebook/fbg1701/mainboard.h +++ b/src/mainboard/facebook/fbg1701/mainboard.h @@ -16,6 +16,7 @@ #ifndef MAINBOARD_H #define MAINBOARD_H +unsigned int mainboard_read_pcb_version(void); void *load_logo(size_t *logo_size); #endif diff --git a/src/mainboard/facebook/fbg1701/ramstage.c b/src/mainboard/facebook/fbg1701/ramstage.c index 5c78bccac5..c5fb79881a 100644 --- a/src/mainboard/facebook/fbg1701/ramstage.c +++ b/src/mainboard/facebook/fbg1701/ramstage.c @@ -324,15 +324,11 @@ static const struct edp_data b101uan08_table[] = { static void mainboard_configure_edp_bridge(void) { - u8 cpld_version; const struct edp_data *edptable; unsigned int loops; int status; - cpld_version = (inb(CPLD_PCB_VERSION_PORT) & CPLD_PCB_VERSION_MASK) >> - CPLD_PCB_VERSION_BIT; - printk(BIOS_DEBUG, "CPLD version: %x\n", cpld_version); - if (cpld_version < 7) + if (mainboard_read_pcb_version() < 7) edptable = b101uan01_table; else edptable = b101uan08_table; From f26a1985bf2d5bea1b345cd306443e0ebb77e27a Mon Sep 17 00:00:00 2001 From: Frans Hendriks Date: Wed, 2 Oct 2019 10:16:26 +0200 Subject: [PATCH 12/21] soc/intel/braswell/chip.h: Add IGD_MEMSIZE_xxMB Add defines to have some more readable code for devcietree.cb. BUG=N/A TEST=4K HDMI monitor and LCD working fine on Facebook FBG-1701 Change-Id: Ifc1a7657a528d1fc570dd16df66b078e37e014cb Signed-off-by: Frans Hendriks Reviewed-on: https://review.coreboot.org/c/coreboot/+/35751 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph --- src/soc/intel/braswell/chip.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/soc/intel/braswell/chip.h b/src/soc/intel/braswell/chip.h index 747b941f55..9f790dc140 100644 --- a/src/soc/intel/braswell/chip.h +++ b/src/soc/intel/braswell/chip.h @@ -32,6 +32,11 @@ #define SVID_CONFIG3 3 #define SVID_PMIC_CONFIG 8 +#define IGD_MEMSIZE_32MB 0x01 +#define IGD_MEMSIZE_64MB 0x02 +#define IGD_MEMSIZE_96MB 0x03 +#define IGD_MEMSIZE_128MB 0x04 + enum lpe_clk_src { LPE_CLK_SRC_XTAL, LPE_CLK_SRC_PLL, From be816858871d74cdff4e3744c18f6dedcf7c5ec4 Mon Sep 17 00:00:00 2001 From: Frans Hendriks Date: Wed, 2 Oct 2019 10:23:55 +0200 Subject: [PATCH 13/21] mb/facebook/fbg1701/devicetree.cb: Use 64MB framebuffer size Connected 4K monitor is not configured at max resolution. The framebuffer size is too small. Increase the framebuffer size to 64MB. This is sufficient for max configuration of 1 HDMI monitor combined with internal LCD panel. BUG=N/A TEST=4K HDMI monitor and LCD working fine on Facebook FBG-1701 Change-Id: I25d2cd696830fc5bda84ea2b87538f526373998e Signed-off-by: Frans Hendriks Reviewed-on: https://review.coreboot.org/c/coreboot/+/35064 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph --- src/mainboard/facebook/fbg1701/devicetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/facebook/fbg1701/devicetree.cb b/src/mainboard/facebook/fbg1701/devicetree.cb index 3c82a034b4..70e950c65e 100644 --- a/src/mainboard/facebook/fbg1701/devicetree.cb +++ b/src/mainboard/facebook/fbg1701/devicetree.cb @@ -9,7 +9,7 @@ chip soc/intel/braswell register "PcdMrcInitMmioSize" = "0x0800" register "PcdMrcInitSpdAddr1" = "0xa0" register "PcdMrcInitSpdAddr2" = "0xa2" - register "PcdIgdDvmt50PreAlloc" = "1" + register "PcdIgdDvmt50PreAlloc" = "IGD_MEMSIZE_64MB" register "PcdApertureSize" = "2" register "PcdGttSize" = "1" register "PcdDvfsEnable" = "0" From c49869b4249b89e21c2d106645029801cb01aaea Mon Sep 17 00:00:00 2001 From: Petr Cvek Date: Tue, 1 Oct 2019 04:01:21 +0200 Subject: [PATCH 14/21] sb/intel/i82801gx: Use symbolic name for register, code rework An original code had a wrong register address 0x27 for AHCI BAR. The value was aligned incidentally by the code specific of the pci_read_config32 function to the correct address 0x24. All 0x24 values in sata.c were changed to the symbolic name PCI_BASE_ADDRESS_5 and the code was optimized. An equivalent code was tested on a real hardware. Signed-off-by: Petr Cvek Change-Id: I33509befe86ff6e333c559c87a0f45886d737df9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35737 Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- src/southbridge/intel/i82801gx/sata.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/src/southbridge/intel/i82801gx/sata.c b/src/southbridge/intel/i82801gx/sata.c index 24dbf7cf27..47c35ba7c6 100644 --- a/src/southbridge/intel/i82801gx/sata.c +++ b/src/southbridge/intel/i82801gx/sata.c @@ -94,7 +94,6 @@ static void sata_init(struct device *dev) { u32 reg32; u16 reg16; - u32 *ahci_bar; u8 ports; /* Get the chip configuration */ @@ -117,7 +116,7 @@ static void sata_init(struct device *dev) case SATA_MODE_IDE_LEGACY_COMBINED: printk(BIOS_DEBUG, "SATA controller in combined mode.\n"); /* No AHCI: clear AHCI base */ - pci_write_config32(dev, 0x24, 0x00000000); + pci_write_config32(dev, PCI_BASE_ADDRESS_5, 0x00000000); /* And without AHCI BAR no memory decoding */ reg16 = pci_read_config16(dev, PCI_COMMAND); reg16 &= ~PCI_COMMAND_MEMORY; @@ -155,8 +154,11 @@ static void sata_init(struct device *dev) /* Interrupt Pin is set by D31IP.PIP */ pci_write_config8(dev, INTR_LN, 0x0a); - ahci_bar = (u32 *)(pci_read_config32(dev, 0x27) & ~0x3ff); - ahci_bar[3] = config->sata_ports_implemented; + struct resource *ahci_res = find_resource(dev, PCI_BASE_ADDRESS_5); + if (ahci_res != NULL) + /* write AHCI GHC_PI register */ + write32(res2mmio(ahci_res, 0xc, 0), + config->sata_ports_implemented); break; default: case SATA_MODE_IDE_PLAIN: @@ -165,7 +167,7 @@ static void sata_init(struct device *dev) pci_write_config8(dev, SATA_MAP, 0x00); /* No AHCI: clear AHCI base */ - pci_write_config32(dev, 0x24, 0x00000000); + pci_write_config32(dev, PCI_BASE_ADDRESS_5, 0x00000000); /* And without AHCI BAR no memory decoding */ reg16 = pci_read_config16(dev, PCI_COMMAND); From 006eb9d8c8550ce0e8d01d37cceb88e7c1e12a5e Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Wed, 2 Oct 2019 07:45:45 -0400 Subject: [PATCH 15/21] libpayload: refactor fetching cbmem pointers There's a recurring pattern of reading cbtable entries that point into cbmem entries. Move that pattern into its own function. Coccinelle patch used for this: @@ identifier T, T2; expression TARGET; @@ -struct cb_cbmem_tab *const T2 = (struct cb_cbmem_tab *)T; -TARGET = phys_to_virt(T2->cbmem_tab); +TARGET = get_cbmem_ptr(T); Change-Id: I7bd4a7ad8baeeaebf0fa7d4b4de6dbc719bc781f Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/35756 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Furquan Shaikh Reviewed-by: Stefan Reinauer --- payloads/libpayload/arch/x86/coreboot.c | 3 +-- payloads/libpayload/include/coreboot_tables.h | 2 ++ payloads/libpayload/libc/coreboot.c | 24 +++++++++---------- 3 files changed, 15 insertions(+), 14 deletions(-) diff --git a/payloads/libpayload/arch/x86/coreboot.c b/payloads/libpayload/arch/x86/coreboot.c index 3a9eb1a7be..07adee8917 100644 --- a/payloads/libpayload/arch/x86/coreboot.c +++ b/payloads/libpayload/arch/x86/coreboot.c @@ -50,8 +50,7 @@ static void cb_parse_x86_rom_var_mtrr(void *ptr, struct sysinfo_t *info) static void cb_parse_mrc_cache(void *ptr, struct sysinfo_t *info) { - struct cb_cbmem_tab *const cbmem = (struct cb_cbmem_tab *)ptr; - info->mrc_cache = phys_to_virt(cbmem->cbmem_tab); + info->mrc_cache = get_cbmem_ptr(ptr); } int cb_parse_arch_specific(struct cb_record *rec, struct sysinfo_t *info) diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h index c24d6acfd6..188f4268c3 100644 --- a/payloads/libpayload/include/coreboot_tables.h +++ b/payloads/libpayload/include/coreboot_tables.h @@ -395,4 +395,6 @@ static inline const char *cb_mb_part_string(const struct cb_mainboard *cbm) (void *)(((u8 *) (_rec)) + sizeof(*(_rec)) \ + (sizeof((_rec)->map[0]) * (_idx))) +/* Helper functions */ +void *get_cbmem_ptr(unsigned char *ptr); #endif diff --git a/payloads/libpayload/libc/coreboot.c b/payloads/libpayload/libc/coreboot.c index e14b144ee4..2ff2090c19 100644 --- a/payloads/libpayload/libc/coreboot.c +++ b/payloads/libpayload/libc/coreboot.c @@ -42,6 +42,12 @@ /* === Parsing code === */ /* This is the generic parsing code. */ +void *get_cbmem_ptr(unsigned char *ptr) +{ + struct cb_cbmem_tab *const cbmem = (struct cb_cbmem_tab *)ptr; + return phys_to_virt(cbmem->cbmem_tab); +} + static void cb_parse_memory(void *ptr, struct sysinfo_t *info) { struct cb_memory *mem = ptr; @@ -128,20 +134,17 @@ static void cb_parse_mac_addresses(unsigned char *ptr, static void cb_parse_tstamp(unsigned char *ptr, struct sysinfo_t *info) { - struct cb_cbmem_tab *const cbmem = (struct cb_cbmem_tab *)ptr; - info->tstamp_table = phys_to_virt(cbmem->cbmem_tab); + info->tstamp_table = get_cbmem_ptr(ptr); } static void cb_parse_cbmem_cons(unsigned char *ptr, struct sysinfo_t *info) { - struct cb_cbmem_tab *const cbmem = (struct cb_cbmem_tab *)ptr; - info->cbmem_cons = phys_to_virt(cbmem->cbmem_tab); + info->cbmem_cons = get_cbmem_ptr(ptr); } static void cb_parse_acpi_gnvs(unsigned char *ptr, struct sysinfo_t *info) { - struct cb_cbmem_tab *const cbmem = (struct cb_cbmem_tab *)ptr; - info->acpi_gnvs = phys_to_virt(cbmem->cbmem_tab); + info->acpi_gnvs = get_cbmem_ptr(ptr); } static void cb_parse_board_id(unsigned char *ptr, struct sysinfo_t *info) @@ -193,8 +196,7 @@ static void cb_parse_string(unsigned char *ptr, char **info) static void cb_parse_wifi_calibration(void *ptr, struct sysinfo_t *info) { - struct cb_cbmem_tab *const cbmem = (struct cb_cbmem_tab *)ptr; - info->wifi_calibration = phys_to_virt(cbmem->cbmem_tab); + info->wifi_calibration = get_cbmem_ptr(ptr); } static void cb_parse_ramoops(void *ptr, struct sysinfo_t *info) @@ -235,14 +237,12 @@ static void cb_parse_boot_media_params(unsigned char *ptr, static void cb_parse_vpd(void *ptr, struct sysinfo_t *info) { - struct cb_cbmem_tab *const cbmem = (struct cb_cbmem_tab *)ptr; - info->chromeos_vpd = phys_to_virt(cbmem->cbmem_tab); + info->chromeos_vpd = get_cbmem_ptr(ptr); } static void cb_parse_fmap_cache(void *ptr, struct sysinfo_t *info) { - struct cb_cbmem_tab *const cbmem = (struct cb_cbmem_tab *)ptr; - info->fmap_cache = phys_to_virt(cbmem->cbmem_tab); + info->fmap_cache = get_cbmem_ptr(ptr); } #if CONFIG(LP_TIMER_RDTSC) From c7ddc999fc076bf6871e3b5e641c07f17b0b1746 Mon Sep 17 00:00:00 2001 From: Mathew King Date: Thu, 8 Aug 2019 14:59:25 -0600 Subject: [PATCH 16/21] ifdtool: Add validate option to ifdtool Add an option to ifdtool which validates that the flash regions defined in the descriptor match the coresponding areas in the FMAP. BUG=chromium:992215 TEST=Ran 'ifdtool -t' with a good bios image and verify no issues run 'ifdtool -t' with a bad bios image and verify expected issues Signed-off-by: Mathew King Change-Id: Idebf105dee1b8f829d54bd65c82867af7aa4aded Reviewed-on: https://review.coreboot.org/c/coreboot/+/34802 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- .../binary_extraction.md} | 0 Documentation/ifdtool/index.md | 5 ++ Documentation/ifdtool/layout.md | 66 +++++++++++++++ Documentation/index.md | 1 - Documentation/util.md | 2 +- util/ifdtool/Makefile | 11 ++- util/ifdtool/ifdtool.c | 80 ++++++++++++++++--- util/ifdtool/ifdtool.h | 1 + 8 files changed, 150 insertions(+), 16 deletions(-) rename Documentation/{Binary_Extraction.md => ifdtool/binary_extraction.md} (100%) create mode 100644 Documentation/ifdtool/index.md create mode 100644 Documentation/ifdtool/layout.md diff --git a/Documentation/Binary_Extraction.md b/Documentation/ifdtool/binary_extraction.md similarity index 100% rename from Documentation/Binary_Extraction.md rename to Documentation/ifdtool/binary_extraction.md diff --git a/Documentation/ifdtool/index.md b/Documentation/ifdtool/index.md new file mode 100644 index 0000000000..e6e6057a74 --- /dev/null +++ b/Documentation/ifdtool/index.md @@ -0,0 +1,5 @@ + +Contents: + +* [Intel IFD Binary Extraction](binary_extraction.md) +* [IFD Layout](layout.md) \ No newline at end of file diff --git a/Documentation/ifdtool/layout.md b/Documentation/ifdtool/layout.md new file mode 100644 index 0000000000..950db6f7ff --- /dev/null +++ b/Documentation/ifdtool/layout.md @@ -0,0 +1,66 @@ +# IFD Layout + +A coreboot image for an Intel SoC contains two separate definitions of the +layout of the flash. The Intel Flash Descriptor (IFD) which defines offsets and +sizes of various regions of flash and the [coreboot FMAP](../lib/flashmap.md). + +The FMAP should define all of the of the regions defined by the IFD to ensure +that those regions are accounted for by coreboot and will not be accidentally +modified. + +## IFD mapping + +The names of the IFD regions in the FMAP should follow the convention of +starting with the prefix `SI_` which stands for `silicon initialization` as a +way to categorize anything required by the SoC but not provided by coreboot. + +|IFD Region index|IFD Region name|FMAP Name|Notes| +|---|---|---|---| +|0|Flash Descriptor|SI_DESC|Always the top 4KB of flash| +|1|BIOS|SI_BIOS|This is the region that contains coreboot| +|2|Intel ME|SI_ME|| +|3|Gigabit Ethernet|SI_GBE|| +|4|Platform Data|SI_PDR|| +|8|EC Firmware|SI_EC|Most Chrome OS devices do not use this region; EC firmware is stored BIOS region of flash| + +## Validation + +The ifdtool can be used to manipulate a firmware image with a IFD. This tool +will not take into account the FMAP while modifying the image which can lead to +unexpected and hard to debug issues with the firmware image. For example if the +ME region is defined at 6 MB in the IFD but the FMAP only allocates 4 MB for the +ME, then when the ME is added by the ifdtool 6 MB will be written which could +overwrite 2 MB of the BIOS. + +In order to validate that the FMAP and the IFD are compatible the ifdtool +provides --validate (-t) option. `ifdtool -t` will read both the IFD and the +FMAP in the image and for every non empty region in the IFD if that region is +defined in the FMAP but the offset or size is different then the tool will +return an error. + +Example: + +```console +foo@bar:~$ ifdtool -t bad_image.bin +Region mismatch between bios and SI_BIOS + Descriptor region bios: + offset: 0x00400000 + length: 0x01c00000 + FMAP area SI_BIOS: + offset: 0x00800000 + length: 0x01800000 +Region mismatch between me and SI_ME + Descriptor region me: + offset: 0x00103000 + length: 0x002f9000 + FMAP area SI_ME: + offset: 0x00103000 + length: 0x006f9000 +Region mismatch between pd and SI_PDR + Descriptor region pd: + offset: 0x003fc000 + length: 0x00004000 + FMAP area SI_PDR: + offset: 0x007fc000 + length: 0x00004000 +``` \ No newline at end of file diff --git a/Documentation/index.md b/Documentation/index.md index b880c1c4d5..39c8d11f9a 100644 --- a/Documentation/index.md +++ b/Documentation/index.md @@ -169,7 +169,6 @@ Contents: * [coreboot at conferences](community/conferences.md) * [Payloads](payloads.md) * [Distributions](distributions.md) -* [Intel IFD Binary Extraction](Binary_Extraction.md) * [Dealing with Untrusted Input in SMM](technotes/2017-02-dealing-with-untrusted-input-in-smm.md) * [GPIO toggling in ACPI AML](acpi/gpio.md) * [Adding devices to a device tree](acpi/devicetree.md) diff --git a/Documentation/util.md b/Documentation/util.md index f8fabc1ec3..3a09b00101 100644 --- a/Documentation/util.md +++ b/Documentation/util.md @@ -47,7 +47,7 @@ Controller (EC). `C` * __genprof__ - Format function tracing logs `Bash` `C` * __gitconfig__ - Initialize git repository submodules install git hooks `Bash` -* __ifdtool__ - Extract and dump Intel Firmware Descriptor information +* [__ifdtool__](ifdtool/index.md) - Extract and dump Intel Firmware Descriptor information `C` * __intelmetool__ - Dump interesting things about Management Engine even if hidden `C` diff --git a/util/ifdtool/Makefile b/util/ifdtool/Makefile index cc52b1ed4a..a4f0af6217 100644 --- a/util/ifdtool/Makefile +++ b/util/ifdtool/Makefile @@ -18,10 +18,16 @@ PROGRAM = ifdtool CC = gcc INSTALL = /usr/bin/env install PREFIX = /usr/local -CFLAGS = -O2 -g -Wall -Wextra -Wmissing-prototypes -Werror -I../../src/commonlib/include +CFLAGS = -O2 -g -Wall -Wextra -Wmissing-prototypes -Werror +CFLAGS += -I../../src/commonlib/include +CFLAGS += -I../cbfstool/flashmap +CFLAGS += -include ../../src/commonlib/include/commonlib/compiler.h LDFLAGS = OBJS = ifdtool.o +OBJS += fmap.o +OBJS += kv_pair.o +OBJS += valstr.o all: dep $(PROGRAM) @@ -38,6 +44,9 @@ dep: %.o: %.c $(CC) $(CFLAGS) -c -o $@ $< +%.o: ../cbfstool/flashmap/%.c + $(CC) $(CFLAGS) -c -o $@ $< + install: $(PROGRAM) mkdir -p $(DESTDIR)$(PREFIX)/bin $(INSTALL) $(PROGRAM) $(DESTDIR)$(PREFIX)/bin diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c index 83caa693ab..0e83c760d8 100644 --- a/util/ifdtool/ifdtool.c +++ b/util/ifdtool/ifdtool.c @@ -22,6 +22,7 @@ #include #include #include +#include #include "ifdtool.h" #ifndef O_BINARY @@ -46,15 +47,15 @@ static int selected_chip = 0; static int platform = -1; static const struct region_name region_names[MAX_REGIONS] = { - { "Flash Descriptor", "fd", "flashregion_0_flashdescriptor.bin" }, - { "BIOS", "bios", "flashregion_1_bios.bin" }, - { "Intel ME", "me", "flashregion_2_intel_me.bin" }, - { "GbE", "gbe", "flashregion_3_gbe.bin" }, - { "Platform Data", "pd", "flashregion_4_platform_data.bin" }, - { "Reserved", "res1", "flashregion_5_reserved.bin" }, - { "Reserved", "res2", "flashregion_6_reserved.bin" }, - { "Reserved", "res3", "flashregion_7_reserved.bin" }, - { "EC", "ec", "flashregion_8_ec.bin" }, + { "Flash Descriptor", "fd", "flashregion_0_flashdescriptor.bin", "SI_DESC" }, + { "BIOS", "bios", "flashregion_1_bios.bin", "SI_BIOS" }, + { "Intel ME", "me", "flashregion_2_intel_me.bin", "SI_ME" }, + { "GbE", "gbe", "flashregion_3_gbe.bin", "SI_GBE" }, + { "Platform Data", "pd", "flashregion_4_platform_data.bin", "SI_PDR" }, + { "Reserved", "res1", "flashregion_5_reserved.bin", NULL }, + { "Reserved", "res2", "flashregion_6_reserved.bin", NULL }, + { "Reserved", "res3", "flashregion_7_reserved.bin", NULL }, + { "EC", "ec", "flashregion_8_ec.bin", "SI_EC" }, }; /* port from flashrom */ @@ -804,6 +805,51 @@ static void write_regions(char *image, int size) } } +static void validate_layout(char *image, int size) +{ + uint i, errors = 0; + struct fmap *fmap; + long int fmap_loc = fmap_find((uint8_t *)image, size); + const frba_t *frba = find_frba(image, size); + + if (fmap_loc < 0 || !frba) + exit(EXIT_FAILURE); + + fmap = (struct fmap *)(image + fmap_loc); + + for (i = 0; i < max_regions; i++) { + if (region_names[i].fmapname == NULL) + continue; + + region_t region = get_region(frba, i); + + if (region.size == 0) + continue; + + const struct fmap_area *area = + fmap_find_area(fmap, region_names[i].fmapname); + + if (!area) + continue; + + if ((uint)region.base != area->offset || + (uint)region.size != area->size) { + printf("Region mismatch between %s and %s\n", + region_names[i].terse, area->name); + printf(" Descriptor region %s:\n", region_names[i].terse); + printf(" offset: 0x%08x\n", region.base); + printf(" length: 0x%08x\n", region.size); + printf(" FMAP area %s:\n", area->name); + printf(" offset: 0x%08x\n", area->offset); + printf(" length: 0x%08x\n", area->size); + errors++; + } + } + + if (errors > 0) + exit(EXIT_FAILURE); +} + static void write_image(const char *filename, char *image, int size) { char new_filename[FILENAME_MAX]; // allow long file names @@ -1359,6 +1405,7 @@ static void print_usage(const char *name) printf("\n" " -d | --dump: dump intel firmware descriptor\n" " -f | --layout dump regions into a flashrom layout file\n" + " -t | --validate Validate that the firmware descriptor layout matches the fmap layout\n" " -x | --extract: extract intel fd modules\n" " -i | --inject : inject file into region \n" " -n | --newlayout update regions using a flashrom layout file\n" @@ -1388,7 +1435,7 @@ int main(int argc, char *argv[]) { int opt, option_index = 0; int mode_dump = 0, mode_extract = 0, mode_inject = 0, mode_spifreq = 0; - int mode_em100 = 0, mode_locked = 0, mode_unlocked = 0; + int mode_em100 = 0, mode_locked = 0, mode_unlocked = 0, mode_validate = 0; int mode_layout = 0, mode_newlayout = 0, mode_density = 0; int mode_altmedisable = 0, altmedisable = 0; char *region_type_string = NULL, *region_fname = NULL; @@ -1413,10 +1460,11 @@ int main(int argc, char *argv[]) {"version", 0, NULL, 'v'}, {"help", 0, NULL, 'h'}, {"platform", 0, NULL, 'p'}, + {"validate", 0, NULL, 't'}, {0, 0, 0, 0} }; - while ((opt = getopt_long(argc, argv, "df:D:C:M:xi:n:s:p:eluvh?", + while ((opt = getopt_long(argc, argv, "df:D:C:M:xi:n:s:p:eluvth?", long_options, &option_index)) != EOF) { switch (opt) { case 'd': @@ -1593,6 +1641,9 @@ int main(int argc, char *argv[]) } fprintf(stderr, "Platform is: %s\n", optarg); break; + case 't': + mode_validate = 1; + break; case 'v': print_version(); exit(EXIT_SUCCESS); @@ -1608,7 +1659,7 @@ int main(int argc, char *argv[]) if ((mode_dump + mode_layout + mode_extract + mode_inject + mode_newlayout + (mode_spifreq | mode_em100 | mode_unlocked | - mode_locked) + mode_altmedisable) > 1) { + mode_locked) + mode_altmedisable + mode_layout) > 1) { fprintf(stderr, "You may not specify more than one mode.\n\n"); print_usage(argv[0]); exit(EXIT_FAILURE); @@ -1616,7 +1667,7 @@ int main(int argc, char *argv[]) if ((mode_dump + mode_layout + mode_extract + mode_inject + mode_newlayout + mode_spifreq + mode_em100 + mode_locked + - mode_unlocked + mode_density + mode_altmedisable) == 0) { + mode_unlocked + mode_density + mode_altmedisable + mode_validate) == 0) { fprintf(stderr, "You need to specify a mode.\n\n"); print_usage(argv[0]); exit(EXIT_FAILURE); @@ -1667,6 +1718,9 @@ int main(int argc, char *argv[]) if (mode_extract) write_regions(image, size); + if (mode_validate) + validate_layout(image, size); + if (mode_inject) inject_region(filename, image, size, region_type, region_fname); diff --git a/util/ifdtool/ifdtool.h b/util/ifdtool/ifdtool.h index f3b9a53e06..195a09cce4 100644 --- a/util/ifdtool/ifdtool.h +++ b/util/ifdtool/ifdtool.h @@ -165,4 +165,5 @@ struct region_name { const char *pretty; const char *terse; const char *filename; + const char *fmapname; }; From d8b150f0d578a5182ce11698906776c0d1d448e9 Mon Sep 17 00:00:00 2001 From: Mathew King Date: Fri, 9 Aug 2019 10:55:37 -0600 Subject: [PATCH 17/21] southbridge/intel: Add config option to validate firmware descriptor Add new config option to validate the Intel firmware descriptor against the fmap layout. This will prevent a firmware descriptor from being used that could corrupt regions of the bootimage in certian circumstances. BUG=chromium:992215 TEST=Build firmware image with mismached decriptor and fmp Without VALIDATE_INTEL_DESCRIPTOR set firmware builds With VALIDATE_INTEL_DESCRIPTOR set error is shown with mismached regions Change-Id: I9e8bb20485e96026cd594cf4e9d6b11b2bf20e1f Signed-off-by: Mathew King Reviewed-on: https://review.coreboot.org/c/coreboot/+/34816 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/southbridge/intel/common/Kconfig | 9 +++++++++ src/southbridge/intel/common/firmware/Makefile.inc | 5 +++++ 2 files changed, 14 insertions(+) diff --git a/src/southbridge/intel/common/Kconfig b/src/southbridge/intel/common/Kconfig index dfd89755ec..31039b68b4 100644 --- a/src/southbridge/intel/common/Kconfig +++ b/src/southbridge/intel/common/Kconfig @@ -55,6 +55,15 @@ config INTEL_DESCRIPTOR_MODE_REQUIRED This config states descriptor mode is *required* for the platform to function properly, or to function at all. +config VALIDATE_INTEL_DESCRIPTOR + depends on INTEL_DESCRIPTOR_MODE_CAPABLE + bool "Validate Intel firmware descriptor" + default n + help + This config enables validating the Intel firmware descriptor against the + fmap layout. If the firmware descriptor layout does not match the fmap + then the bootimage cannot be built. + config INTEL_CHIPSET_LOCKDOWN depends on HAVE_INTEL_CHIPSET_LOCKDOWN && HAVE_SMI_HANDLER && !CHROMEOS #ChromeOS's payload seems to handle finalization on its on. diff --git a/src/southbridge/intel/common/firmware/Makefile.inc b/src/southbridge/intel/common/firmware/Makefile.inc index e7060361bd..5f3212f487 100644 --- a/src/southbridge/intel/common/firmware/Makefile.inc +++ b/src/southbridge/intel/common/firmware/Makefile.inc @@ -45,6 +45,11 @@ add_intel_firmware: $(obj)/coreboot.pre $(IFDTOOL) printf " DD Adding Intel Firmware Descriptor\n" dd if=$(IFD_BIN_PATH) \ of=$(obj)/coreboot.pre conv=notrunc >/dev/null 2>&1 +ifeq ($(CONFIG_VALIDATE_INTEL_DESCRIPTOR),y) + $(objutil)/ifdtool/ifdtool \ + $(IFDTOOL_USE_CHIPSET) \ + -t $(obj)/coreboot.pre +endif ifeq ($(CONFIG_HAVE_ME_BIN),y) printf " IFDTOOL me.bin -> coreboot.pre\n" $(objutil)/ifdtool/ifdtool \ From dcf86e0cffde76aee45372849b710c2aac5fffa8 Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Thu, 29 Aug 2019 12:32:53 -0600 Subject: [PATCH 18/21] mb/[google/intel]/*: Specify Chrome EC bus - LPC or ESPI Previously all boards using eSPI for the Chrome EC just called it LPC as the code for the chrome EC is the same between the two busses. I'm adding a new Kconfig symbol to specify eSPI, so switch the boards that actually use eSPI to that symbol and add the LPC symbol to all the others. The EC_GOOGLE_CHROMEEC_LPC symbol will no longer default to enabled for x86 platforms, so one symbol or the other needs to be specified for each platform. BUG=b:140055300 TEST=Build tested only. Change-Id: Icf242ca2b7d8b1470feda4e44b47a2cdc20680f2 Signed-off-by: Martin Roth Reviewed-on: https://review.coreboot.org/c/coreboot/+/35153 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/mainboard/google/auron/Kconfig | 1 + src/mainboard/google/cyan/Kconfig | 1 + src/mainboard/google/dragonegg/Kconfig | 2 +- src/mainboard/google/eve/Kconfig | 2 +- src/mainboard/google/hatch/Kconfig | 2 +- src/mainboard/google/link/Kconfig | 1 + src/mainboard/google/octopus/Kconfig | 2 +- src/mainboard/google/poppy/Kconfig | 2 +- src/mainboard/google/rambi/Kconfig | 1 + src/mainboard/google/slippy/Kconfig | 1 + src/mainboard/intel/glkrvp/Kconfig | 2 +- src/mainboard/intel/strago/Kconfig | 1 + 12 files changed, 12 insertions(+), 6 deletions(-) diff --git a/src/mainboard/google/auron/Kconfig b/src/mainboard/google/auron/Kconfig index 171418e4fa..13348a348f 100644 --- a/src/mainboard/google/auron/Kconfig +++ b/src/mainboard/google/auron/Kconfig @@ -4,6 +4,7 @@ config BOARD_GOOGLE_BASEBOARD_AURON select SOC_INTEL_BROADWELL select BOARD_ROMSIZE_KB_8192 select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_LPC select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME diff --git a/src/mainboard/google/cyan/Kconfig b/src/mainboard/google/cyan/Kconfig index 6f830b208e..647d4e9026 100644 --- a/src/mainboard/google/cyan/Kconfig +++ b/src/mainboard/google/cyan/Kconfig @@ -3,6 +3,7 @@ config BOARD_GOOGLE_BASEBOARD_CYAN select BOARD_ROMSIZE_KB_8192 select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_BOARDID + select EC_GOOGLE_CHROMEEC_LPC select EC_GOOGLE_CHROMEEC_MEC select EC_GOOGLE_CHROMEEC_ACPI_MEMMAP select ENABLE_BUILTIN_COM1 diff --git a/src/mainboard/google/dragonegg/Kconfig b/src/mainboard/google/dragonegg/Kconfig index dc6146c18b..1891cbe0ac 100644 --- a/src/mainboard/google/dragonegg/Kconfig +++ b/src/mainboard/google/dragonegg/Kconfig @@ -5,7 +5,7 @@ config BOARD_GOOGLE_BASEBOARD_DRAGONEGG select DRIVERS_I2C_HID select DRIVERS_SPI_ACPI select EC_GOOGLE_CHROMEEC - select EC_GOOGLE_CHROMEEC_LPC + select EC_GOOGLE_CHROMEEC_ESPI select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select INTEL_LPSS_UART_FOR_CONSOLE diff --git a/src/mainboard/google/eve/Kconfig b/src/mainboard/google/eve/Kconfig index e646f23d26..c768ecc3a4 100644 --- a/src/mainboard/google/eve/Kconfig +++ b/src/mainboard/google/eve/Kconfig @@ -11,7 +11,7 @@ config BOARD_SPECIFIC_OPTIONS select DRIVERS_USB_ACPI select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_BOARDID - select EC_GOOGLE_CHROMEEC_LPC + select EC_GOOGLE_CHROMEEC_ESPI select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select INTEL_GMA_HAVE_VBT diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 8bb0207e19..004cc28633 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -11,7 +11,7 @@ config BOARD_GOOGLE_BASEBOARD_HATCH select DRIVERS_USB_ACPI select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_BOARDID - select EC_GOOGLE_CHROMEEC_LPC + select EC_GOOGLE_CHROMEEC_ESPI select GOOGLE_SMBIOS_MAINBOARD_VERSION select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES diff --git a/src/mainboard/google/link/Kconfig b/src/mainboard/google/link/Kconfig index b7421900dc..12c5ffeb38 100644 --- a/src/mainboard/google/link/Kconfig +++ b/src/mainboard/google/link/Kconfig @@ -7,6 +7,7 @@ config BOARD_SPECIFIC_OPTIONS select SOUTHBRIDGE_INTEL_C216 select BOARD_ROMSIZE_KB_8192 select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_LPC select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME diff --git a/src/mainboard/google/octopus/Kconfig b/src/mainboard/google/octopus/Kconfig index 81204188b1..c13d7f8ade 100644 --- a/src/mainboard/google/octopus/Kconfig +++ b/src/mainboard/google/octopus/Kconfig @@ -12,7 +12,7 @@ config BOARD_GOOGLE_BASEBOARD_OCTOPUS select DRIVERS_USB_ACPI select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_BOARDID - select EC_GOOGLE_CHROMEEC_LPC + select EC_GOOGLE_CHROMEEC_ESPI select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select INTEL_LPSS_UART_FOR_CONSOLE diff --git a/src/mainboard/google/poppy/Kconfig b/src/mainboard/google/poppy/Kconfig index 91de9a8c71..07e3990b47 100644 --- a/src/mainboard/google/poppy/Kconfig +++ b/src/mainboard/google/poppy/Kconfig @@ -7,7 +7,7 @@ config BOARD_GOOGLE_BASEBOARD_POPPY select DRIVERS_I2C_HID select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_BOARDID - select EC_GOOGLE_CHROMEEC_LPC + select EC_GOOGLE_CHROMEEC_ESPI select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select INTEL_GMA_HAVE_VBT if BOARD_GOOGLE_NAMI diff --git a/src/mainboard/google/rambi/Kconfig b/src/mainboard/google/rambi/Kconfig index 63e0d5676c..83bcc1a2ee 100644 --- a/src/mainboard/google/rambi/Kconfig +++ b/src/mainboard/google/rambi/Kconfig @@ -3,6 +3,7 @@ config BOARD_GOOGLE_BASEBOARD_RAMBI def_bool n select SOC_INTEL_BAYTRAIL select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_LPC select ENABLE_BUILTIN_COM1 select BOARD_ROMSIZE_KB_8192 select HAVE_ACPI_TABLES diff --git a/src/mainboard/google/slippy/Kconfig b/src/mainboard/google/slippy/Kconfig index 68b92bb3f3..13dbe19577 100644 --- a/src/mainboard/google/slippy/Kconfig +++ b/src/mainboard/google/slippy/Kconfig @@ -7,6 +7,7 @@ config BOARD_GOOGLE_BASEBOARD_SLIPPY select INTEL_LYNXPOINT_LP select BOARD_ROMSIZE_KB_8192 select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_LPC select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME diff --git a/src/mainboard/intel/glkrvp/Kconfig b/src/mainboard/intel/glkrvp/Kconfig index f10a9f0fa4..3380762736 100644 --- a/src/mainboard/intel/glkrvp/Kconfig +++ b/src/mainboard/intel/glkrvp/Kconfig @@ -30,7 +30,7 @@ choice config GLK_CHROME_EC bool "Chrome EC" select EC_GOOGLE_CHROMEEC - select EC_GOOGLE_CHROMEEC_LPC + select EC_GOOGLE_CHROMEEC_ESPI config GLK_INTEL_EC bool "Intel EC" diff --git a/src/mainboard/intel/strago/Kconfig b/src/mainboard/intel/strago/Kconfig index 1f6a73d474..5a49e8cc0a 100644 --- a/src/mainboard/intel/strago/Kconfig +++ b/src/mainboard/intel/strago/Kconfig @@ -5,6 +5,7 @@ config BOARD_SPECIFIC_OPTIONS select BOARD_ROMSIZE_KB_8192 select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_BOARDID + select EC_GOOGLE_CHROMEEC_LPC select EC_GOOGLE_CHROMEEC_MEC select EC_GOOGLE_CHROMEEC_ACPI_MEMMAP select ENABLE_BUILTIN_COM1 From 30d3c9ed48dc7e03a412b36b600b54b32f0c4162 Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Thu, 29 Aug 2019 13:09:06 -0600 Subject: [PATCH 19/21] ec/google/chromec: Default EC_GOOGLE_CHROMEEC_LPC to disabled Don't set a default bus type for the Chrome EC on x86. The platform must select the bus, typically LPC or ESPI. BUG=b:140055300 TEST=Build tested only Change-Id: I736cb9e43292a1b228cd083ca81a8e5db383e878 Signed-off-by: Martin Roth Reviewed-on: https://review.coreboot.org/c/coreboot/+/35154 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Furquan Shaikh --- src/ec/google/chromeec/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/ec/google/chromeec/Kconfig b/src/ec/google/chromeec/Kconfig index 2242653ccc..2eb3b95c7d 100644 --- a/src/ec/google/chromeec/Kconfig +++ b/src/ec/google/chromeec/Kconfig @@ -60,7 +60,7 @@ config EC_GOOGLE_CHROMEEC_ESPI config EC_GOOGLE_CHROMEEC_LPC depends on EC_GOOGLE_CHROMEEC && ARCH_X86 # Needs Plug-and-play. - def_bool y + def_bool n help Google Chrome EC via LPC bus. From 5a2bbcaa93109ba19b631489e366a71df4608f4e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Thu, 3 Oct 2019 16:54:04 +0300 Subject: [PATCH 20/21] cpu/intel/: Fix regression with smmrelocate MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fix regression with commit d53fd70 intel/smm/gen1: Use smm_subregion(). The bitmask on SMRR register parameter was inverted for selected models. Change-Id: Ia572ca3bdd4da371985691b5d249f998382fbe48 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/35780 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans Reviewed-by: Patrick Georgi Reviewed-by: Bill XIE Reviewed-by: Nico Huber --- src/cpu/intel/smm/gen1/smmrelocate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c index 4ecd7db78e..3eb869ae1f 100644 --- a/src/cpu/intel/smm/gen1/smmrelocate.c +++ b/src/cpu/intel/smm/gen1/smmrelocate.c @@ -121,7 +121,7 @@ static void fill_in_relocation_params(struct smm_relocation_params *params) /* On model_6fx and model_1067x bits [0:11] on smrr_base are reserved */ if (cpu_has_alternative_smrr()) - params->smrr_base.lo &= ~rmask; + params->smrr_base.lo &= rmask; smm_subregion(SMM_SUBREGION_CHIPSET, ¶ms->ied_base, ¶ms->ied_size); } From 8be1fdf26f28136040386bdbb666949aa5ed44fc Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Thu, 26 Sep 2019 16:10:55 +0000 Subject: [PATCH 21/21] Update arm-trusted-firmware submodule to upstream master Updating from commit id 42cdeb93: 2019-09-13 12:09:21 +0000 - (Merge "stm32mp1: manage CONSOLE_FLAG_TRANSLATE_CRLF and cleanup driver" into integration) to commit id ace23683: 2019-09-27 09:54:27 +0000 - (Merge changes from topic "ld/stm32-authentication" into integration) This brings in 83 new commits. Change-Id: I273b5014db76d307d8735d78a8fdd5db3d07146c Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/35625 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer Reviewed-by: Julius Werner --- 3rdparty/arm-trusted-firmware | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/3rdparty/arm-trusted-firmware b/3rdparty/arm-trusted-firmware index 42cdeb9308..ace23683be 160000 --- a/3rdparty/arm-trusted-firmware +++ b/3rdparty/arm-trusted-firmware @@ -1 +1 @@ -Subproject commit 42cdeb93080f2b54a75be14e4f5ee776872f3f0f +Subproject commit ace23683beb81354d6edbc61c087ab8c384d0631