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mb/google/volteer: Migrate volteer to use SPD files under spd/

Browse Source 
SPD files are being moved from the soc and mainboard directories to a
centralised spd/ directory. This change migrates all volteer variants to
use this new location. The contents of the new SPDs are identical, only
their file paths have changed.

The variant Makefile.inc and dram_id.generated.txt files were generated
using the part_id_gen tool. E.g. for voema:

util/spd_tools/bin/part_id_gen \
  TGL \
  lp4x \
  src/mainboard/google/volteer/variants/voema/memory \
  src/mainboard/google/volteer/variants/voema/memory/mem_parts_used.txt

BUG=b:191776301
TEST=Check that each variant's coreboot.rom is the same with and without
this change. Built using:
abuild -p none -t google/volteer -a -x --timeless

Change-Id: Ibd4f42fd421bfa58354b532fe7a67ee59dac5e1d
Signed-off-by: Reka Norman <rekanorman@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57695
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Reka Norman
2021-09-15 16:33:51 +10:00
committed by Patrick Georgi
parent 2d501aa0fd
commit 102a71c0d2
57 changed files with 226 additions and 648 deletions
Download Patch File Download Diff File Expand all files Collapse all files

32
src/soc/intel/tigerlake/spd/ddr4-spd-1.hex
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32
src/soc/intel/tigerlake/spd/ddr4-spd-2.hex
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32
src/soc/intel/tigerlake/spd/ddr4-spd-3.hex
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32
src/soc/intel/tigerlake/spd/ddr4-spd-4.hex
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32
src/soc/intel/tigerlake/spd/ddr4-spd-5.hex
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src/soc/intel/tigerlake/spd/ddr4-spd-6.hex
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32
src/soc/intel/tigerlake/spd/ddr4-spd-7.hex
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@@ -1,32 +0,0 @@
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32
src/soc/intel/tigerlake/spd/ddr4-spd-8.hex
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@@ -1,32 +0,0 @@
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32
src/soc/intel/tigerlake/spd/ddr4-spd-9.hex
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@@ -1,32 +0,0 @@
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32
src/soc/intel/tigerlake/spd/ddr4-spd-empty.hex
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@@ -1,32 +0,0 @@
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19
src/soc/intel/tigerlake/spd/ddr4_spd_manifest.generated.txt
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@@ -1,19 +0,0 @@
H5AN8G6NDJR-XNC,ddr4-spd-1.hex
MT40A512M16TB-062E:J,ddr4-spd-1.hex
H5ANAG6NCMR-XNC,ddr4-spd-2.hex
HMA851S6CJR6N-VK,ddr4-spd-3.hex
K4A8G165WC-BCTD,ddr4-spd-3.hex
H5AN8G6NCJR-VKC,ddr4-spd-3.hex
MT40A1G16KNR-075:E,ddr4-spd-4.hex
K4AAG165WB-MCTD,ddr4-spd-5.hex
H5ANAG6NCMR-VKC,ddr4-spd-6.hex
K4A8G165WC-BCWE,ddr4-spd-1.hex
MT40A1G16KD-062E:E,ddr4-spd-7.hex
K4AAG165WA-BCWE,ddr4-spd-7.hex
H5AN8G6NCJR-XNC,ddr4-spd-1.hex
K4AAG165WA-BCTD,ddr4-spd-8.hex
H5ANAG6NDMR-XNC,ddr4-spd-2.hex
H5ANAG6NCJR-XNC,ddr4-spd-9.hex
K4AAG165WB-BCWE,ddr4-spd-9.hex
MT40A1G16RC-062E:B,ddr4-spd-9.hex
MT40A512M16TB-062E:R,ddr4-spd-1.hex

32
src/soc/intel/tigerlake/spd/lp4x-spd-1.hex
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@@ -1,32 +0,0 @@
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32
src/soc/intel/tigerlake/spd/lp4x-spd-2.hex
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@@ -1,32 +0,0 @@
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

32
src/soc/intel/tigerlake/spd/lp4x-spd-3.hex
View File

@@ -1,32 +0,0 @@
23 11 11 0E 15 21 B4 08 00 00 00 00 0A 01 00 00
00 00 04 FF 92 54 05 00 87 00 90 A8 90 C0 08 60
04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

32
src/soc/intel/tigerlake/spd/lp4x-spd-4.hex
View File

@@ -1,32 +0,0 @@
23 11 11 0E 16 29 94 08 00 00 00 00 02 01 00 00
00 00 04 FF 92 54 05 00 87 00 90 A8 90 E0 0B F0
05 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

32
src/soc/intel/tigerlake/spd/lp4x-spd-5.hex
View File

@@ -1,32 +0,0 @@
23 11 11 0E 14 19 94 08 00 00 00 00 02 01 00 00
00 00 05 0A 80 54 01 00 89 00 90 A8 90 A0 05 D0
02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

19
src/soc/intel/tigerlake/spd/lp4x_spd_manifest.generated.txt
View File

@@ -1,19 +0,0 @@
H9HCNNNBKMMLXR-NEE,lp4x-spd-1.hex
H9HCNNNFAMMLXR-NEE,lp4x-spd-2.hex
K4U6E3S4AA-MGCL,lp4x-spd-1.hex
K4UBE3D4AA-MGCL,lp4x-spd-3.hex
MT53E1G32D2NP-046 WT:A,lp4x-spd-4.hex
H9HKNNNCRMBVAR-NEH,lp4x-spd-1.hex
MT53E1G64D4SQ-046 WT:A,lp4x-spd-4.hex
MT53E512M32D2NP-046 WT:F,lp4x-spd-1.hex
NT6AP256T32AV-J2,lp4x-spd-5.hex
K4U6E3S4AA-MGCR,lp4x-spd-1.hex
MT53E512M32D2NP-046 WT:E,lp4x-spd-1.hex
H9HCNNNCPMMLXR-NEE,lp4x-spd-3.hex
K4UBE3D4AA-MGCR,lp4x-spd-3.hex
MT53E512M64D4NW-046 WT:E,lp4x-spd-1.hex
MT53E1G64D8NW-046 WT:E,lp4x-spd-3.hex
H9HCNNNCRMBLPR-NEE,lp4x-spd-1.hex
H9HCNNNFBMBLPR-NEE,lp4x-spd-3.hex
MT53D1G64D4NW-046 WT:A,lp4x-spd-4.hex
MT53D512M64D4NW-046 WT:F,lp4x-spd-1.hex

32
src/soc/intel/tigerlake/spd/placeholder.spd.hex
View File

@@ -1,32 +0,0 @@
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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