AMD: Set the mask of MTRR according to CONFIG_CPU_ADDR_BITS

The high bits of mtrr mask are MBZ (Must be zero). Writing 1 to these
bits will cause exception. So be carefull when spread this change.

The supermicro/h8scm needs more work. Currently it is set as it was.
We need to check if the F10 and F15 have different value.

Change-Id: I2dd8bf07ecee2fe4d1721cec6b21623556e68947
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1661
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>

src/cpu/amd/agesa/family12/Kconfig

@@ -23,7 +23,7 @@ config CPU_AMD_AGESA_FAMILY12
 
 config CPU_ADDR_BITS
 	int
-	default 36
+	default 48
 	depends on CPU_AMD_AGESA_FAMILY12
 
 config CPU_SOCKET_TYPE

src/cpu/amd/agesa/family15/Kconfig

@@ -21,6 +21,11 @@ config CPU_AMD_AGESA_FAMILY15
 	bool
 	select PCI_IO_CFG_EXT
 
+config CPU_ADDR_BITS
+	int
+	default 48
+	depends on CPU_AMD_AGESA_FAMILY15
+
 if CPU_AMD_AGESA_FAMILY15
 
 config CPU_AMD_SOCKET_G34

src/cpu/amd/agesa/family15tn/Kconfig

@@ -23,7 +23,7 @@ config CPU_AMD_AGESA_FAMILY15_TN
 
 config CPU_ADDR_BITS
 	int
-	default 36
+	default 48
 	depends on CPU_AMD_AGESA_FAMILY15_TN
 
 config CPU_SOCKET_TYPE