soc/intel/xeon_sp: Make gsi_bases platform independent

This commit makes gsi_bases platform independent. It introduces two new
Kconfigs which set if there are IIO APICs on other devices than the PCH
or not, and where they do start.

Change-Id: I40db4a8fd90572757687f35bbd8eebd7229fc75a
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65531
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/intel/xeon_sp/acpi.c

@@ -98,16 +98,16 @@ static void print_madt_ioapic(int socket, int stack,
 const struct madt_ioapic_info *soc_get_ioapic_info(size_t *entries)
 {
 	int cur_index;
+	int gsi_per_iiostack = 0;
+
 	const IIO_UDS *hob = get_iio_uds();
 
-	/* With XEON-SP FSP, PCH IOAPIC is allocated with first 120 GSIs. */
+	uint8_t gsi_bases[CONFIG(XEON_SP_HAVE_IIO_IOAPIC) * 8 + 1] = { 0 };
-#if (CONFIG(SOC_INTEL_COOPERLAKE_SP))
-	const int gsi_bases[] = { 0, 0x78, 0x80, 0x88, 0x90, 0x98, 0xA0, 0xA8, 0xB0 };
-#endif
 
-#if (CONFIG(SOC_INTEL_SKYLAKE_SP))
+	for (uint8_t i = 1; i < sizeof(gsi_bases); i++) {
-	const int gsi_bases[] = { 0, 0x18, 0x20, 0x28, 0x30, 0x48, 0x50, 0x58, 0x60 };
+		int gsi_base = CONFIG_XEON_SP_PCH_IOAPIC_GSI_BASES;
-#endif
+		gsi_bases[i] = gsi_base + (i * gsi_per_iiostack);
+	}
 
 	static struct madt_ioapic_info madt_tbl[ARRAY_SIZE(gsi_bases)];
 
@@ -119,6 +119,11 @@ const struct madt_ioapic_info *soc_get_ioapic_info(size_t *entries)
 			  madt_tbl[cur_index].addr, madt_tbl[cur_index].gsi_base);
 	++cur_index;
 
+	if (!CONFIG(XEON_SP_HAVE_IIO_IOAPIC)) {
+		*entries = cur_index;
+		return madt_tbl;
+	}
+
 	for (int socket = 0; socket < hob->PlatformData.numofIIO; ++socket) {
 		for (int stack = 0; stack < MAX_IIO_STACK; ++stack) {
 			const STACK_RES *ri =

src/soc/intel/xeon_sp/cpx/Kconfig

@@ -108,6 +108,14 @@ config DIMM_MAX
 config DIMM_SPD_SIZE
 	default 512
 
+config XEON_SP_HAVE_IIO_IOAPIC
+	bool
+	default y
+
+config XEON_SP_PCH_IOAPIC_GSI_BASES
+	hex
+	default 0x78
+
 if INTEL_TXT
 
 config INTEL_TXT_SINIT_SIZE

src/soc/intel/xeon_sp/skx/Kconfig

@@ -59,4 +59,12 @@ config IFD_CHIPSET
 	string
 	default "lbg"
 
+config XEON_SP_HAVE_IIO_IOAPIC
+	bool
+	default y
+
+config XEON_SP_PCH_IOAPIC_GSI_BASES
+	hex
+	default 0x18
+
 endif