src/cpu: drop CPU_X86_CACHE_HELPER and x86_enable_cache wrapper function

Selecting CPU_X86_CACHE_HELPER only added the x86_enable_cache wrapper
function around enable_cache which additionally wrote a POST code to
port 0x80 and printed a message to the console. This function was only
called during multi-processor initialization in ramstage via the init
function pointer in the CPU's device operations struct and was run on
all cores, so the message on the console was printed once per CPU core.

This patch replaces all x86_enable_cache calls by calls to enable_cache
and removes the wrapper function and the Kconfig symbol
CPU_X86_CACHE_HELPER which was used to only add this when the
corresponding CPUs used the x86_enable_cache wrapper function.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Suggested-by: Angel Pons <th3fanbus@gmail.com>
Change-Id: I5866b6bf014821ff9e3a48052a5eaf69319b003a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58579
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/cpu/amd/agesa/family14/Kconfig

@@ -3,7 +3,6 @@
 config CPU_AMD_AGESA_FAMILY14
 	bool
 	select X86_AMD_FIXED_MTRRS
-	select CPU_X86_CACHE_HELPER
 
 if CPU_AMD_AGESA_FAMILY14
 

src/cpu/amd/agesa/family14/model_14_init.c

@@ -54,7 +54,7 @@ static void model_14_init(struct device *dev)
 		restore_mtrr();
 
 	x86_mtrr_check();
-	x86_enable_cache();
+	enable_cache();
 
 	/* zero the machine check error status registers */
 	mca_clear_status();

src/cpu/amd/agesa/family15tn/Kconfig

@@ -4,7 +4,6 @@ config CPU_AMD_AGESA_FAMILY15_TN
 	bool
 	select IDS_OPTIONS_HOOKED_UP
 	select X86_AMD_FIXED_MTRRS
-	select CPU_X86_CACHE_HELPER
 
 if CPU_AMD_AGESA_FAMILY15_TN
 

src/cpu/amd/agesa/family15tn/model_15_init.c

@@ -25,7 +25,7 @@ static void model_15_init(struct device *dev)
 	u32 siblings;
 #endif
 
-	//x86_enable_cache();
+	//enable_cache();
 	//amd_setup_mtrrs();
 	//x86_mtrr_check();
 	disable_cache();
@@ -53,7 +53,7 @@ static void model_15_init(struct device *dev)
 		restore_mtrr();
 
 	x86_mtrr_check();
-	x86_enable_cache();
+	enable_cache();
 
 	/* zero the machine check error status registers */
 	mca_clear_status();

src/cpu/amd/agesa/family16kb/Kconfig

@@ -3,7 +3,6 @@
 config CPU_AMD_AGESA_FAMILY16_KB
 	bool
 	select X86_AMD_FIXED_MTRRS
-	select CPU_X86_CACHE_HELPER
 
 if CPU_AMD_AGESA_FAMILY16_KB
 

src/cpu/amd/agesa/family16kb/model_16_init.c

@@ -23,7 +23,7 @@ static void model_16_init(struct device *dev)
 	u32 siblings;
 #endif
 
-	//x86_enable_cache();
+	//enable_cache();
 	//amd_setup_mtrrs();
 	//x86_mtrr_check();
 	disable_cache();
@@ -51,7 +51,7 @@ static void model_16_init(struct device *dev)
 		restore_mtrr();
 
 	x86_mtrr_check();
-	x86_enable_cache();
+	enable_cache();
 
 	/* zero the machine check error status registers */
 	mca_clear_status();

src/cpu/intel/model_65x/Kconfig

@@ -2,4 +2,3 @@ config CPU_INTEL_MODEL_65X
 	bool
 	select ARCH_X86
 	select SUPPORT_CPU_UCODE_IN_CBFS
-	select CPU_X86_CACHE_HELPER

src/cpu/intel/model_65x/model_65x_init.c

@@ -16,7 +16,7 @@ static void model_65x_init(struct device *dev)
 	p6_configure_l2_cache();
 
 	/* Turn on caching if we haven't already */
-	x86_enable_cache();
+	enable_cache();
 	x86_setup_mtrrs();
 	x86_mtrr_check();
 

src/cpu/intel/model_67x/Kconfig

@@ -2,4 +2,3 @@ config CPU_INTEL_MODEL_67X
 	bool
 	select ARCH_X86
 	select SUPPORT_CPU_UCODE_IN_CBFS
-	select CPU_X86_CACHE_HELPER

src/cpu/intel/model_67x/model_67x_init.c

@@ -17,7 +17,7 @@ static void model_67x_init(struct device *cpu)
 	p6_configure_l2_cache();
 
 	/* Turn on caching if we haven't already */
-	x86_enable_cache();
+	enable_cache();
 
 	/* Setup MTRRs */
 	x86_setup_mtrrs();

src/cpu/intel/model_68x/Kconfig

@@ -4,4 +4,3 @@ config CPU_INTEL_MODEL_68X
 	bool
 	select ARCH_X86
 	select SUPPORT_CPU_UCODE_IN_CBFS
-	select CPU_X86_CACHE_HELPER

src/cpu/intel/model_68x/model_68x_init.c

@@ -14,7 +14,7 @@ static void model_68x_init(struct device *cpu)
 	char processor_name[49];
 
 	/* Turn on caching if we haven't already */
-	x86_enable_cache();
+	enable_cache();
 
 	/* Update the microcode */
 	intel_update_microcode_from_cbfs();

src/cpu/intel/model_6bx/Kconfig

@@ -2,4 +2,3 @@ config CPU_INTEL_MODEL_6BX
 	bool
 	select ARCH_X86
 	select SUPPORT_CPU_UCODE_IN_CBFS
-	select CPU_X86_CACHE_HELPER

src/cpu/intel/model_6bx/model_6bx_init.c

@@ -14,7 +14,7 @@ static void model_6bx_init(struct device *cpu)
 	char processor_name[49];
 
 	/* Turn on caching if we haven't already */
-	x86_enable_cache();
+	enable_cache();
 
 	/* Update the microcode */
 	intel_update_microcode_from_cbfs();

src/cpu/intel/model_6ex/Kconfig

@@ -9,4 +9,3 @@ config CPU_INTEL_MODEL_6EX
 	select SUPPORT_CPU_UCODE_IN_CBFS
 	select CPU_INTEL_COMMON
 	select CPU_INTEL_COMMON_TIMEBASE
-	select CPU_X86_CACHE_HELPER

src/cpu/intel/model_6ex/model_6ex_init.c

@@ -97,7 +97,7 @@ static void model_6ex_init(struct device *cpu)
 	char processor_name[49];
 
 	/* Turn on caching if we haven't already */
-	x86_enable_cache();
+	enable_cache();
 
 	/* Print processor name */
 	fill_processor_name(processor_name);

src/cpu/intel/model_6fx/Kconfig

@@ -10,4 +10,3 @@ config CPU_INTEL_MODEL_6FX
 	select CPU_INTEL_COMMON
 	select CPU_INTEL_COMMON_TIMEBASE
 	select SETUP_XIP_CACHE
-	select CPU_X86_CACHE_HELPER

src/cpu/intel/model_6fx/model_6fx_init.c

@@ -111,7 +111,7 @@ static void model_6fx_init(struct device *cpu)
 	char processor_name[49];
 
 	/* Turn on caching if we haven't already */
-	x86_enable_cache();
+	enable_cache();
 
 	/* Print processor name */
 	fill_processor_name(processor_name);

src/cpu/intel/model_6xx/Kconfig

@@ -2,4 +2,3 @@ config CPU_INTEL_MODEL_6XX
 	bool
 	select ARCH_X86
 	select SUPPORT_CPU_UCODE_IN_CBFS
-	select CPU_X86_CACHE_HELPER

src/cpu/intel/model_6xx/model_6xx_init.c

@@ -10,7 +10,7 @@
 static void model_6xx_init(struct device *dev)
 {
 	/* Turn on caching if we haven't already */
-	x86_enable_cache();
+	enable_cache();
 	x86_setup_mtrrs();
 	x86_mtrr_check();
 

src/cpu/intel/model_f2x/Kconfig

@@ -4,4 +4,3 @@ config CPU_INTEL_MODEL_F2X
 	select SUPPORT_CPU_UCODE_IN_CBFS
 	select SMM_ASEG
 	select CPU_INTEL_COMMON
-	select CPU_X86_CACHE_HELPER

src/cpu/intel/model_f2x/model_f2x_init.c

@@ -12,7 +12,7 @@
 static void model_f2x_init(struct device *cpu)
 {
 	/* Turn on caching if we haven't already */
-	x86_enable_cache();
+	enable_cache();
 
 	if (!intel_ht_sibling()) {
 		/* MTRRs are shared between threads */

src/cpu/intel/model_f3x/Kconfig

@@ -3,4 +3,3 @@ config CPU_INTEL_MODEL_F3X
 	select ARCH_X86
 	select SUPPORT_CPU_UCODE_IN_CBFS
 	select CPU_INTEL_COMMON
-	select CPU_X86_CACHE_HELPER

src/cpu/intel/model_f3x/model_f3x_init.c

@@ -12,7 +12,7 @@
 static void model_f3x_init(struct device *cpu)
 {
 	/* Turn on caching if we haven't already */
-	x86_enable_cache();
+	enable_cache();
 
 	if (!CONFIG(PARALLEL_MP) && !intel_ht_sibling()) {
 		/* MTRRs are shared between threads */

src/cpu/intel/model_f4x/Kconfig

@@ -2,4 +2,3 @@ config CPU_INTEL_MODEL_F4X
 	bool
 	select ARCH_X86
 	select SUPPORT_CPU_UCODE_IN_CBFS
-	select CPU_X86_CACHE_HELPER

src/cpu/intel/model_f4x/model_f4x_init.c

@@ -8,7 +8,7 @@
 static void model_f4x_init(struct device *cpu)
 {
 	/* Turn on caching if we haven't already */
-	x86_enable_cache();
+	enable_cache();
 
 	/* Enable the local CPU APICs */
 	setup_lapic();

src/cpu/x86/Kconfig

@@ -1,9 +1,3 @@
-config CPU_X86_CACHE_HELPER
-	bool
-	default n
-	help
-	  Add the x86_enable_cache ramstage helper function to the build.
-
 config PARALLEL_MP
 	def_bool y
 	depends on !LEGACY_SMP_INIT

src/cpu/x86/Makefile.inc

@@ -1,4 +1,3 @@
-subdirs-$(CONFIG_CPU_X86_CACHE_HELPER) += cache
 subdirs-y += lapic
 subdirs-y += mtrr
 subdirs-y += pae

src/cpu/x86/cache/Makefile.inc

@@ -1 +0,0 @@
-ramstage-y += cache.c

src/cpu/x86/cache/cache.c

@@ -1,11 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <console/console.h>
-#include <cpu/x86/cache.h>
-
-void x86_enable_cache(void)
-{
-	post_code(POST_ENABLING_CACHE);
-	printk(BIOS_INFO, "Enabling cache\n");
-	enable_cache();
-}

src/include/cpu/x86/cache.h

@@ -56,7 +56,5 @@ static __always_inline void disable_cache(void)
 	wbinvd();
 }
 
-void x86_enable_cache(void);
-
 #endif /* !__ASSEMBLER__ */
 #endif /* CPU_X86_CACHE */