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Re-declare CACHE_ROM_SIZE as aligned ROM_SIZE for MTRR

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This change allows Kconfig options ROM_SIZE and CBFS_SIZE to be
set with values that are not power of 2. The region programmed
as WB cacheable will include all of ROM_SIZE.

Side-effects to consider:

Memory region below flash may be tagged WRPROT cacheable. As an
example, with ROM_SIZE of 12 MB, CACHE_ROM_SIZE would be 16 MB.
Since this can overlap CAR, we add an explicit test and fail
on compile should this happen. To work around this problem, one
needs to use CACHE_ROM_SIZE_OVERRIDE in the mainboard Kconfig and
define a smaller region for WB cache.

With this change flash regions outside CBFS are also tagged WRPROT
cacheable. This covers IFD and ME and sections ChromeOS may use.

Change-Id: I5e577900ff7e91606bef6d80033caaed721ce4bf
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4625
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
This commit is contained in:
Kyösti Mälkki
2014-01-06 11:06:26 +02:00
parent 5e73be2a7a
commit 107f72e674
27 changed files with 103 additions and 57 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
src/cpu/intel/car/cache_as_ram_ht.inc
View File

@ -392,7 +392,7 @@ no_msr_11e:
movl $(~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid), %eax
wrmsr
#if CONFIG_CACHE_ROM_SIZE
#if CACHE_ROM_SIZE
/* Enable caching and Speculative Reads for Flash ROM device. */
movl $MTRRphysBase_MSR(1), %ecx
movl $(CACHE_ROM_BASE | MTRR_TYPE_WRPROT), %eax
@ -400,7 +400,7 @@ no_msr_11e:
wrmsr
movl $MTRRphysMask_MSR(1), %ecx
rdmsr
movl $(~(CONFIG_CACHE_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
movl $(~(CACHE_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
wrmsr
#endif

4
src/cpu/intel/fsp_model_206ax/cache_as_ram.inc
View File

@ -173,7 +173,7 @@ _clear_mtrrs_:
movl $CPU_PHYSMASK_HI, %edx // 36bit address space
wrmsr
#if CONFIG_CACHE_ROM_SIZE
#if CACHE_ROM_SIZE
/* Enable Caching and speculative Reads for the
* complete ROM now that we actually have RAM.
*/
@ -182,7 +182,7 @@ _clear_mtrrs_:
xorl %edx, %edx
wrmsr
movl $MTRRphysMask_MSR(1), %ecx
movl $(~(CONFIG_CACHE_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
movl $(~(CACHE_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
movl $CPU_PHYSMASK_HI, %edx
wrmsr
#endif

4
src/cpu/intel/haswell/romstage.c
View File

@ -124,9 +124,9 @@ static void *setup_romstage_stack_after_car(void)
/* Cache the ROM as WP just below 4GiB. */
slot = stack_push(slot, mtrr_mask_upper); /* upper mask */
slot = stack_push(slot, ~(CONFIG_ROM_SIZE - 1) | MTRRphysMaskValid);
slot = stack_push(slot, ~(CACHE_ROM_SIZE - 1) | MTRRphysMaskValid);
slot = stack_push(slot, 0); /* upper base */
slot = stack_push(slot, ~(CONFIG_ROM_SIZE - 1) | MTRR_TYPE_WRPROT);
slot = stack_push(slot, ~(CACHE_ROM_SIZE - 1) | MTRR_TYPE_WRPROT);
num_mtrrs++;
/* Cache RAM as WB from 0 -> CONFIG_RAMTOP. */

4
src/cpu/intel/model_2065x/cache_as_ram.inc
View File

@ -238,7 +238,7 @@ before_romstage:
movl $CPU_PHYSMASK_HI, %edx // 36bit address space
wrmsr
#if CONFIG_CACHE_ROM_SIZE
#if CACHE_ROM_SIZE
/* Enable Caching and speculative Reads for the
* complete ROM now that we actually have RAM.
*/
@ -247,7 +247,7 @@ before_romstage:
xorl %edx, %edx
wrmsr
movl $MTRRphysMask_MSR(1), %ecx
movl $(~(CONFIG_CACHE_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
movl $(~(CACHE_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
movl $CPU_PHYSMASK_HI, %edx
wrmsr
#endif

4
src/cpu/intel/model_206ax/cache_as_ram.inc
View File

@ -250,7 +250,7 @@ before_romstage:
movl $CPU_PHYSMASK_HI, %edx // 36bit address space
wrmsr
#if CONFIG_CACHE_ROM_SIZE
#if CACHE_ROM_SIZE
/* Enable Caching and speculative Reads for the
* complete ROM now that we actually have RAM.
*/
@ -259,7 +259,7 @@ before_romstage:
xorl %edx, %edx
wrmsr
movl $MTRRphysMask_MSR(1), %ecx
movl $(~(CONFIG_CACHE_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
movl $(~(CACHE_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
movl $CPU_PHYSMASK_HI, %edx
wrmsr
#endif

4
src/cpu/intel/model_6ex/cache_as_ram.inc
View File

@ -186,14 +186,14 @@ clear_mtrrs:
movl $CPU_PHYSMASK_HI, %edx
wrmsr
#if CONFIG_CACHE_ROM_SIZE
#if CACHE_ROM_SIZE
/* Enable caching and Speculative Reads for Flash ROM device. */
movl $MTRRphysBase_MSR(1), %ecx
movl $(CACHE_ROM_BASE | MTRR_TYPE_WRPROT), %eax
xorl %edx, %edx
wrmsr
movl $MTRRphysMask_MSR(1), %ecx
movl $(~(CONFIG_CACHE_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
movl $(~(CACHE_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
movl $CPU_PHYSMASK_HI, %edx
wrmsr
#endif