thin out romcc epilogue and have it call copy_and_run as

all the others do. Make sure copy_and_run is called with
the right calling convention. Fix up 2 license headers.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5386 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

src/arch/i386/include/arch/acpi.h

@@ -407,7 +407,6 @@ extern u8 acpi_slp_type;
 void suspend_resume(void);
 void *acpi_find_wakeup_vector(void);
 void *acpi_get_wakeup_rsdp(void);
-void acpi_jmp_to_realm_wakeup(u32 linear_addr) __attribute__((regparm(0)));
 void acpi_jump_to_wakeup(void *wakeup_addr);
 
 int acpi_get_sleep_type(void);

src/arch/i386/init/crt0_prologue.inc

@@ -3,8 +3,7 @@
  *
  * This file is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
+ * published by the Free Software Foundation; version 2 of the License.
- * the License, or (at your option) any later version.
  */
 
 

src/arch/i386/init/crt0_romcc_epilogue.inc

@@ -1,124 +1,27 @@
-/* -*- asm -*-
- * $ $
- *
- */
-
 /* 
- * Copyright (C) 1996-2002 Markus Franz Xaver Johannes Oberhumer
+ * Copyright 2002 Eric Biederman
  *
  * This file is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
+ * published by the Free Software Foundation; version 2 of the License.
- * the License, or (at your option) any later version.
- *
- * Originally this code was part of ucl the data compression library
- * for upx the ``Ultimate Packer of eXecutables''.
- *
- * - Converted to gas assembly, and refitted to work with etherboot.
- *   Eric Biederman 20 Aug 2002
- * - Merged the nrv2b decompressor into crt0.base of coreboot
- *   Eric Biederman 26 Sept 2002
  */
 
-
-#ifndef CONSOLE_DEBUG_TX_STRING
-	/* uses:	 esp, ebx, ax, dx */
-# define __CRT_CONSOLE_TX_STRING(string) \
-	mov	string, %ebx	; \
-	CALLSP(crt_console_tx_string)
-
-# if defined(CONFIG_TTYS0_BASE) && (ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG)
-#  define CONSOLE_DEBUG_TX_STRING(string)        __CRT_CONSOLE_TX_STRING(string)
-# else
-#  define CONSOLE_DEBUG_TX_STRING(string)
-# endif
-#endif
-
 	/* clear boot_complete flag */
 	xorl	%ebp, %ebp
 __main:
-	CONSOLE_DEBUG_TX_STRING($str_copying_to_ram)
+	post_code(0x11)
-
-	/*
-	 *	Copy data into RAM and clear the BSS. Since these segments
-	 *	isn\'t really that big we just copy/clear using bytes, not
-	 *	double words.
-	 */
-	post_code(0x11)		/* post 11 */
-
 	cld			/* clear direction flag */
 	
-	/* copy coreboot from it's initial load location to 
-	 * the location it is compiled to run at.
-	 * Normally this is copying from FLASH ROM to RAM.
-	 */
 	movl	%ebp, %esi
+
 	/* FIXME: look for a proper place for the stack */
 	movl	$0x4000000, %esp
 	movl	%esp, %ebp
 	pushl %esi
-	pushl $str_coreboot_ram_name
+	call copy_and_run
-	call cbfs_and_run_core
 
 .Lhlt:	
-	post_code(0xee)	/* post fe */
+	post_code(0xee)
 	hlt
 	jmp	.Lhlt
 
-#ifdef __CRT_CONSOLE_TX_STRING
-	/* Uses esp, ebx, ax, dx  */
-crt_console_tx_string:
-	mov	(%ebx), %al
-	inc	%ebx
-	cmp	$0, %al
-	jne	9f
-	RETSP
-9:
-/* Base Address */
-#ifndef CONFIG_TTYS0_BASE
-#define CONFIG_TTYS0_BASE	0x3f8
-#endif
-/* Data */
-#define TTYS0_RBR (CONFIG_TTYS0_BASE+0x00)
-
-/* Control */
-#define TTYS0_TBR TTYS0_RBR
-#define TTYS0_IER (CONFIG_TTYS0_BASE+0x01)
-#define TTYS0_IIR (CONFIG_TTYS0_BASE+0x02)
-#define TTYS0_FCR TTYS0_IIR
-#define TTYS0_LCR (CONFIG_TTYS0_BASE+0x03)
-#define TTYS0_MCR (CONFIG_TTYS0_BASE+0x04)
-#define TTYS0_DLL TTYS0_RBR
-#define TTYS0_DLM TTYS0_IER
-
-/* Status */
-#define TTYS0_LSR (CONFIG_TTYS0_BASE+0x05)
-#define TTYS0_MSR (CONFIG_TTYS0_BASE+0x06)
-#define TTYS0_SCR (CONFIG_TTYS0_BASE+0x07)
-	
-	mov	%al, %ah
-10:	mov	$TTYS0_LSR, %dx
-	inb	%dx, %al
-	test	$0x20, %al
-	je	10b
-	mov	$TTYS0_TBR, %dx
-	mov	%ah, %al
-	outb	%al, %dx
-
-	jmp crt_console_tx_string
-#endif /* __CRT_CONSOLE_TX_STRING */
-
-#if defined(CONSOLE_DEBUG_TX_STRING) && (ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG)
-.section ".rom.data"
-#if CONFIG_COMPRESS
-str_copying_to_ram:  .string "Uncompressing coreboot to RAM.\r\n"
-#else
-str_copying_to_ram:  .string "Copying coreboot to RAM.\r\n"
-#endif
-str_pre_main:        .string "Jumping to coreboot.\r\n"
-.previous
-
-#endif /* ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG */
-
-str_coreboot_ram_name:	.ascii CONFIG_CBFS_PREFIX
-			.string "/coreboot_ram"

src/cpu/amd/car/copy_and_run.c

@@ -19,13 +19,13 @@
 
 void cbfs_and_run_core(const char *filename, unsigned ebp);
 
-static void copy_and_run(unsigned cpu_reset)
+static void __attribute__((regparm(0))) copy_and_run(unsigned cpu_reset)
 {
 	cbfs_and_run_core(CONFIG_CBFS_PREFIX "/coreboot_ram", cpu_reset);
 }
 
 #if CONFIG_AP_CODE_IN_CAR == 1
-static void copy_and_run_ap_code_in_car(unsigned ret_addr)
+static void __attribute__((regparm(0))) copy_and_run_ap_code_in_car(unsigned ret_addr)
 {
 	cbfs_and_run_core(CONFIG_CBFS_PREFIX "/coreboot_ap", ret_addr);
 }

src/cpu/x86/car/copy_and_run.c

@@ -21,7 +21,7 @@
 
 void cbfs_and_run_core(const char *filename, unsigned ebp);
 
-static void copy_and_run(unsigned cpu_reset)
+static void __attribute__((regparm(0))) copy_and_run(unsigned cpu_reset)
 {
 	if (cpu_reset == 1) cpu_reset = -1;
 	else cpu_reset = 0;