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oryp11: Do not configure clock reqs, FSP will do that

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Change-Id: I75e0b2fe7dfbcbc9400825e03218a6c21c265ff2
This commit is contained in:
Jeremy Soller
2023-02-27 08:47:19 -07:00
parent f8b75214c2
commit 10b360c0d9
1 changed files with 6 additions and 6 deletions
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12
src/mainboard/system76/rpl/variants/oryp11/gpio.c
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@ -102,10 +102,10 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPO(GPP_D2, 0, DEEP), // ROM_I2C_EN
PAD_CFG_GPO(GPP_D3, 1, DEEP),
PAD_CFG_GPO(GPP_D4, 0, DEEP), // PS8461_SW
PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), // PEX_SSD2_CLKREQ#
// GPP_D5 (PEX_SSD2_CLKREQ#) configured by FSP
PAD_CFG_GPO(GPP_D6, 1, DEEP),
PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), // WLAN_CLKREQ#
PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), // PEG_CLKREQ#
// GPP_D7 (WLAN_CLKREQ#) configured by FSP
// GPP_D8 (PEG_CLKREQ#) configured by FSP
PAD_CFG_GPO(GPP_D9, 1, DEEP),
PAD_CFG_GPO(GPP_D10, 0, DEEP), // GPP_D10
_PAD_CFG_STRUCT(GPP_D11, 0x44001700, 0x3c00),
@ -150,7 +150,7 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), // CNVI_RGI_DT
PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), // CNVI_RGI_RSP
PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), // CNVI_RF_RST#
PAD_CFG_NF(GPP_F5, NONE, DEEP, NF2), // XTAL_CLKREQ
// GPP_F5 (XTAL_CLKREQ) configured by FSP
PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING
PAD_CFG_GPO(GPP_F7, 1, DEEP), // LAN_PLT_RST#
PAD_CFG_GPO(GPP_F8, 1, DEEP),
@ -164,7 +164,7 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPI(GPP_F16, NONE, PLTRST), // GPU_EVENT#
PAD_CFG_GPO(GPP_F17, 1, DEEP),
PAD_CFG_GPO(GPP_F18, 1, DEEP),
PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // LAN_CLKREQ#
// GPP_F19 (LAN_CLKREQ#) configured by FSP
PAD_CFG_GPO(GPP_F20, 1, PLTRST), // M2_SSD2_RST#
PAD_CFG_GPO(GPP_F21, 1, DEEP),
PAD_CFG_GPO(GPP_F22, 1, DEEP),
@ -194,7 +194,7 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPI(GPP_H20, NONE, DEEP),
PAD_CFG_GPI(GPP_H21, NONE, DEEP),
PAD_CFG_GPO(GPP_H22, 0, DEEP),
PAD_CFG_NF(GPP_H23, NONE, DEEP, NF2), // CARD_CLKREQ#
// GPP_H23 (CARD_CLKREQ#) configured by FSP
/* ------- GPIO Group GPP_R ------- */
PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), // HDA_BITCLK