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AGESA f15 cimx/sb700: Remove vendorcode source

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Change-Id: If5a72786d1119908073488c1d6d8787ac0f4f95c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/23276
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Kyösti Mälkki
2018-01-13 17:11:37 +02:00
parent c618b90119
commit 11284d7d43
613 changed files with 0 additions and 200311 deletions
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3562
src/vendorcode/amd/agesa/f15/AGESA.h
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src/vendorcode/amd/agesa/f15/AMD.h
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/* $NoKeywords:$ */
/**
* @file
*
* Agesa structures and definitions
*
* Contains AMD AGESA core interface
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Include
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _AMD_H_
#define _AMD_H_
#define AGESA_REVISION "Arch2008"
#define AGESA_ID "AGESA"
#define Int16FromChar(a,b) ((a) << 0 | (b) << 8)
#define Int32FromChar(a,b,c,d) ((a) << 0 | (b) << 8 | (c) << 16 | (d) << 24)
//
//
// AGESA Types and Definitions
//
//
#define LAST_ENTRY 0xFFFFFFFF
#define IMAGE_SIGNATURE Int32FromChar ('$', 'A', 'M', 'D')
#define IOCF8 0xCF8
#define IOCFC 0xCFC
/// The return status for all AGESA public services.
///
/// Services return the most severe status of any logged event. Status other than SUCCESS, UNSUPPORTED, and BOUNDS_CHK
/// will have log entries with more detail.
///
typedef enum {
AGESA_SUCCESS = 0, ///< The service completed normally. Info may be logged.
AGESA_UNSUPPORTED, ///< The dispatcher or create struct had an unimplemented function requested.
///< Not logged.
AGESA_BOUNDS_CHK, ///< A dynamic parameter was out of range and the service was not provided.
///< Example, memory address not installed, heap buffer handle not found.
///< Not Logged.
// AGESA_STATUS of greater severity (the ones below this line), always have a log entry available.
AGESA_ALERT, ///< An observed condition, but no loss of function.
///< See log. Example, HT CRC.
AGESA_WARNING, ///< Possible or minor loss of function. See Log.
AGESA_ERROR, ///< Significant loss of function, boot may be possible. See Log.
AGESA_CRITICAL, ///< Continue boot only to notify user. See Log.
AGESA_FATAL, ///< Halt booting. See Log, however Fatal errors pertaining to heap problems
///< may not be able to reliably produce log events.
AgesaStatusMax ///< Not a status, for limit checking.
} AGESA_STATUS;
/// For checking whether a status is at or above the mandatory log level.
#define AGESA_STATUS_LOG_LEVEL AGESA_ALERT
/**
* Callout method to the host environment.
*
* Callout using a dispatch with appropriate thunk layer, which is determined by the host environment.
*
* @param[in] Function The specific callout function being invoked.
* @param[in] FcnData Function specific data item.
* @param[in,out] ConfigPtr Reference to Callout params.
*/
typedef AGESA_STATUS (*CALLOUT_ENTRY) (
IN UINT32 Function,
IN UINTN FcnData,
IN OUT VOID *ConfigPtr
);
typedef AGESA_STATUS (*IMAGE_ENTRY) (VOID *ConfigPtr);
typedef AGESA_STATUS (*MODULE_ENTRY) (VOID *ConfigPtr);
///This allocation type is used by the AmdCreateStruct entry point
typedef enum {
PreMemHeap = 0, ///< Create heap in cache.
PostMemDram, ///< Create heap in memory.
ByHost ///< Create heap by Host.
} ALLOCATION_METHOD;
/// These width descriptors are used by the library function, and others, to specify the data size
typedef enum ACCESS_WIDTH {
AccessWidth8 = 1, ///< Access width is 8 bits.
AccessWidth16, ///< Access width is 16 bits.
AccessWidth32, ///< Access width is 32 bits.
AccessWidth64, ///< Access width is 64 bits.
AccessS3SaveWidth8 = 0x81, ///< Save 8 bits data.
AccessS3SaveWidth16, ///< Save 16 bits data.
AccessS3SaveWidth32, ///< Save 32 bits data.
AccessS3SaveWidth64, ///< Save 64 bits data.
} ACCESS_WIDTH;
/// AGESA struct name
typedef enum {
// AGESA BASIC FUNCTIONS
AMD_INIT_RECOVERY = 0x00020000, ///< AmdInitRecovery entry point handle
AMD_CREATE_STRUCT, ///< AmdCreateStruct handle
AMD_INIT_EARLY, ///< AmdInitEarly entry point handle
AMD_INIT_ENV, ///< AmdInitEnv entry point handle
AMD_INIT_LATE, ///< AmdInitLate entry point handle
AMD_INIT_MID, ///< AmdInitMid entry point handle
AMD_INIT_POST, ///< AmdInitPost entry point handle
AMD_INIT_RESET, ///< AmdInitReset entry point handle
AMD_INIT_RESUME, ///< AmdInitResume entry point handle
AMD_RELEASE_STRUCT, ///< AmdReleaseStruct handle
AMD_S3LATE_RESTORE, ///< AmdS3LateRestore entry point handle
AMD_S3_SAVE, ///< AmdS3Save entry point handle
AMD_GET_APIC_ID, ///< AmdGetApicId entry point handle
AMD_GET_PCI_ADDRESS, ///< AmdGetPciAddress entry point handle
AMD_IDENTIFY_CORE, ///< AmdIdentifyCore general service handle
AMD_READ_EVENT_LOG, ///< AmdReadEventLog general service handle
AMD_GET_EXECACHE_SIZE, ///< AmdGetAvailableExeCacheSize general service handle
AMD_LATE_RUN_AP_TASK, ///< AmdLateRunApTask entry point handle
AMD_IDENTIFY_DIMMS ///< AmdIdentifyDimm general service handle
} AGESA_STRUCT_NAME;
/* ResetType constant values */
#define WARM_RESET_WHENEVER 1
#define COLD_RESET_WHENEVER 2
#define WARM_RESET_IMMEDIATELY 3
#define COLD_RESET_IMMEDIATELY 4
// AGESA Structures
/// The standard header for all AGESA services.
/// For internal AGESA naming conventions, see @ref amdconfigparamname .
typedef struct {
IN UINT32 ImageBasePtr; ///< The AGESA Image base address.
IN UINT32 Func; ///< The service desired
IN UINT32 AltImageBasePtr; ///< Alternate Image location
IN CALLOUT_ENTRY CalloutPtr; ///< For Callout from AGESA
IN UINT8 HeapStatus; ///< For heap status from boot time slide.
IN UINT64 HeapBasePtr; ///< Location of the heap
IN OUT UINT8 Reserved[7]; ///< This space is reserved for future use.
} AMD_CONFIG_PARAMS;
/// Create Struct Interface.
typedef struct {
IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
IN AGESA_STRUCT_NAME AgesaFunctionName; ///< The service to init
IN ALLOCATION_METHOD AllocationMethod; ///< How to handle buffer allocation
IN OUT UINT32 NewStructSize; ///< The size of the allocated data, in for ByHost, else out only.
IN OUT VOID *NewStructPtr; ///< The struct for the service.
///< The struct to init for ByHost allocation,
///< the initialized struct on return.
} AMD_INTERFACE_PARAMS;
#define FUNC_0 0 // bit-placed for PCI address creation
#define FUNC_1 1
#define FUNC_2 2
#define FUNC_3 3
#define FUNC_4 4
#define FUNC_5 5
#define FUNC_6 6
#define FUNC_7 7
/// AGESA Binary module header structure
typedef struct {
IN UINT32 Signature; ///< Binary Signature
IN CHAR8 CreatorID[8]; ///< 8 characters ID
IN CHAR8 Version[12]; ///< 12 characters version
IN UINT32 ModuleInfoOffset; ///< Offset of module
IN UINT32 EntryPointAddress; ///< Entry address
IN UINT32 ImageBase; ///< Image base
IN UINT32 RelocTableOffset; ///< Relocate Table offset
IN UINT32 ImageSize; ///< Size
IN UINT16 Checksum; ///< Checksum
IN UINT8 ImageType; ///< Type
IN UINT8 V_Reserved; ///< Reserved
} AMD_IMAGE_HEADER;
/// AGESA Binary module header structure
typedef struct _AMD_MODULE_HEADER {
IN UINT32 ModuleHeaderSignature; ///< Module signature
IN CHAR8 ModuleIdentifier[8]; ///< 8 characters ID
IN CHAR8 ModuleVersion[12]; ///< 12 characters version
IN VOID *ModuleDispatcher; ///< A pointer point to dispatcher
IN struct _AMD_MODULE_HEADER *NextBlock; ///< Next module header link
} AMD_MODULE_HEADER;
// AMD_CODE_HEADER Signatures.
#define AGESA_CODE_SIGNATURE {'!', '!', 'A', 'G', 'E', 'S', 'A', ' '}
#define CIMXNB_CODE_SIGNATURE {'!', '!', 'C', 'I', 'M', 'X', 'N', 'B'}
#define CIMXSB_CODE_SIGNATURE {'!', '!', 'C', 'I', 'M', 'X', 'S', 'B'}
/// AGESA_CODE_SIGNATURE
typedef struct {
IN CHAR8 Signature[8]; ///< code header Signature
IN CHAR8 ComponentName[8]; ///< 8 character name of the code module
IN CHAR8 Version[12]; ///< 12 character version string
IN CHAR8 TerminatorNull; ///< null terminated string
IN CHAR8 VerReserved[7]; ///< reserved space
} AMD_CODE_HEADER;
/// Extended PCI address format
typedef struct {
IN OUT UINT32 Register:12; ///< Register offset
IN OUT UINT32 Function:3; ///< Function number
IN OUT UINT32 Device:5; ///< Device number
IN OUT UINT32 Bus:8; ///< Bus number
IN OUT UINT32 Segment:4; ///< Segment
} EXT_PCI_ADDR;
/// Union type for PCI address
typedef union _PCI_ADDR {
IN UINT32 AddressValue; ///< Formal address
IN EXT_PCI_ADDR Address; ///< Extended address
} PCI_ADDR;
// SBDFO - Segment Bus Device Function Offset
// 31:28 Segment (4-bits)
// 27:20 Bus (8-bits)
// 19:15 Device (5-bits)
// 14:12 Function(3-bits)
// 11:00 Offset (12-bits)
#define MAKE_SBDFO(Seg, Bus, Dev, Fun, Off) ((((UINT32) (Seg)) << 28) | (((UINT32) (Bus)) << 20) | \
(((UINT32)(Dev)) << 15) | (((UINT32)(Fun)) << 12) | ((UINT32)(Off)))
#define ILLEGAL_SBDFO 0xFFFFFFFF
/// CPUID data received registers format
typedef struct {
OUT UINT32 EAX_Reg; ///< CPUID instruction result in EAX
OUT UINT32 EBX_Reg; ///< CPUID instruction result in EBX
OUT UINT32 ECX_Reg; ///< CPUID instruction result in ECX
OUT UINT32 EDX_Reg; ///< CPUID instruction result in EDX
} CPUID_DATA;
/// HT frequency for external callbacks
typedef enum {
HT_FREQUENCY_200M = 0, ///< HT speed 200 for external callbacks
HT_FREQUENCY_400M = 2, ///< HT speed 400 for external callbacks
HT_FREQUENCY_600M = 4, ///< HT speed 600 for external callbacks
HT_FREQUENCY_800M = 5, ///< HT speed 800 for external callbacks
HT_FREQUENCY_1000M = 6, ///< HT speed 1000 for external callbacks
HT_FREQUENCY_1200M = 7, ///< HT speed 1200 for external callbacks
HT_FREQUENCY_1400M = 8, ///< HT speed 1400 for external callbacks
HT_FREQUENCY_1600M = 9, ///< HT speed 1600 for external callbacks
HT_FREQUENCY_1800M = 10, ///< HT speed 1800 for external callbacks
HT_FREQUENCY_2000M = 11, ///< HT speed 2000 for external callbacks
HT_FREQUENCY_2200M = 12, ///< HT speed 2200 for external callbacks
HT_FREQUENCY_2400M = 13, ///< HT speed 2400 for external callbacks
HT_FREQUENCY_2600M = 14, ///< HT speed 2600 for external callbacks
HT_FREQUENCY_2800M = 17, ///< HT speed 2800 for external callbacks
HT_FREQUENCY_3000M = 18, ///< HT speed 3000 for external callbacks
HT_FREQUENCY_3200M = 19, ///< HT speed 3200 for external callbacks
HT_FREQUENCY_MAX ///< Limit check.
} HT_FREQUENCIES;
// The minimum HT3 frequency
#define HT3_FREQUENCY_MIN HT_FREQUENCY_1200M
#ifndef BIT0
#define BIT0 0x0000000000000001ull
#endif
#ifndef BIT1
#define BIT1 0x0000000000000002ull
#endif
#ifndef BIT2
#define BIT2 0x0000000000000004ull
#endif
#ifndef BIT3
#define BIT3 0x0000000000000008ull
#endif
#ifndef BIT4
#define BIT4 0x0000000000000010ull
#endif
#ifndef BIT5
#define BIT5 0x0000000000000020ull
#endif
#ifndef BIT6
#define BIT6 0x0000000000000040ull
#endif
#ifndef BIT7
#define BIT7 0x0000000000000080ull
#endif
#ifndef BIT8
#define BIT8 0x0000000000000100ull
#endif
#ifndef BIT9
#define BIT9 0x0000000000000200ull
#endif
#ifndef BIT10
#define BIT10 0x0000000000000400ull
#endif
#ifndef BIT11
#define BIT11 0x0000000000000800ull
#endif
#ifndef BIT12
#define BIT12 0x0000000000001000ull
#endif
#ifndef BIT13
#define BIT13 0x0000000000002000ull
#endif
#ifndef BIT14
#define BIT14 0x0000000000004000ull
#endif
#ifndef BIT15
#define BIT15 0x0000000000008000ull
#endif
#ifndef BIT16
#define BIT16 0x0000000000010000ull
#endif
#ifndef BIT17
#define BIT17 0x0000000000020000ull
#endif
#ifndef BIT18
#define BIT18 0x0000000000040000ull
#endif
#ifndef BIT19
#define BIT19 0x0000000000080000ull
#endif
#ifndef BIT20
#define BIT20 0x0000000000100000ull
#endif
#ifndef BIT21
#define BIT21 0x0000000000200000ull
#endif
#ifndef BIT22
#define BIT22 0x0000000000400000ull
#endif
#ifndef BIT23
#define BIT23 0x0000000000800000ull
#endif
#ifndef BIT24
#define BIT24 0x0000000001000000ull
#endif
#ifndef BIT25
#define BIT25 0x0000000002000000ull
#endif
#ifndef BIT26
#define BIT26 0x0000000004000000ull
#endif
#ifndef BIT27
#define BIT27 0x0000000008000000ull
#endif
#ifndef BIT28
#define BIT28 0x0000000010000000ull
#endif
#ifndef BIT29
#define BIT29 0x0000000020000000ull
#endif
#ifndef BIT30
#define BIT30 0x0000000040000000ull
#endif
#ifndef BIT31
#define BIT31 0x0000000080000000ull
#endif
#ifndef BIT32
#define BIT32 0x0000000100000000ull
#endif
#ifndef BIT33
#define BIT33 0x0000000200000000ull
#endif
#ifndef BIT34
#define BIT34 0x0000000400000000ull
#endif
#ifndef BIT35
#define BIT35 0x0000000800000000ull
#endif
#ifndef BIT36
#define BIT36 0x0000001000000000ull
#endif
#ifndef BIT37
#define BIT37 0x0000002000000000ull
#endif
#ifndef BIT38
#define BIT38 0x0000004000000000ull
#endif
#ifndef BIT39
#define BIT39 0x0000008000000000ull
#endif
#ifndef BIT40
#define BIT40 0x0000010000000000ull
#endif
#ifndef BIT41
#define BIT41 0x0000020000000000ull
#endif
#ifndef BIT42
#define BIT42 0x0000040000000000ull
#endif
#ifndef BIT43
#define BIT43 0x0000080000000000ull
#endif
#ifndef BIT44
#define BIT44 0x0000100000000000ull
#endif
#ifndef BIT45
#define BIT45 0x0000200000000000ull
#endif
#ifndef BIT46
#define BIT46 0x0000400000000000ull
#endif
#ifndef BIT47
#define BIT47 0x0000800000000000ull
#endif
#ifndef BIT48
#define BIT48 0x0001000000000000ull
#endif
#ifndef BIT49
#define BIT49 0x0002000000000000ull
#endif
#ifndef BIT50
#define BIT50 0x0004000000000000ull
#endif
#ifndef BIT51
#define BIT51 0x0008000000000000ull
#endif
#ifndef BIT52
#define BIT52 0x0010000000000000ull
#endif
#ifndef BIT53
#define BIT53 0x0020000000000000ull
#endif
#ifndef BIT54
#define BIT54 0x0040000000000000ull
#endif
#ifndef BIT55
#define BIT55 0x0080000000000000ull
#endif
#ifndef BIT56
#define BIT56 0x0100000000000000ull
#endif
#ifndef BIT57
#define BIT57 0x0200000000000000ull
#endif
#ifndef BIT58
#define BIT58 0x0400000000000000ull
#endif
#ifndef BIT59
#define BIT59 0x0800000000000000ull
#endif
#ifndef BIT60
#define BIT60 0x1000000000000000ull
#endif
#ifndef BIT61
#define BIT61 0x2000000000000000ull
#endif
#ifndef BIT62
#define BIT62 0x4000000000000000ull
#endif
#ifndef BIT63
#define BIT63 0x8000000000000000ull
#endif
#endif // _AMD_H_

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src/vendorcode/amd/agesa/f15/Config/OptionApmInstall.h
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/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: Application Power Management (APM).
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 54493 $ @e \$Date: 2011-06-08 15:21:06 -0600 (Wed, 08 Jun 2011) $
*/
/*****************************************************************************
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
***************************************************************************/
#ifndef _OPTION_APM_INSTALL_H_
#define _OPTION_APM_INSTALL_H_
#include "cpuApm.h"
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#define OPTION_CPU_APM_FEAT
#define F15_APM_SUPPORT
#if OPTION_CPU_APM == TRUE
#if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE)
// Family 15h
#ifdef OPTION_FAMILY15H
#if OPTION_FAMILY15H == TRUE
#if (OPTION_FAMILY15H_OR == TRUE) || (OPTION_FAMILY15H_KM == TRUE)
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureApm;
#undef OPTION_CPU_APM_FEAT
#define OPTION_CPU_APM_FEAT &CpuFeatureApm,
extern CONST APM_FAMILY_SERVICES ROMDATA F15ApmSupport;
#undef F15_APM_SUPPORT
#define F15_APM_SUPPORT {AMD_FAMILY_15_OR | AMD_FAMILY_15_KM, &F15ApmSupport},
#endif
#endif
#endif
#endif
#endif
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA ApmFamilyServiceArray[] =
{
F15_APM_SUPPORT
{0, NULL}
};
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA ApmFamilyServiceTable =
{
(sizeof (ApmFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
&ApmFamilyServiceArray[0]
};
#endif // _OPTION_APM_INSTALL_H_

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src/vendorcode/amd/agesa/f15/Config/OptionC6Install.h
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/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: C6 C-state
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $
*/
/*****************************************************************************
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
***************************************************************************/
#ifndef _OPTION_C6_STATE_INSTALL_H_
#define _OPTION_C6_STATE_INSTALL_H_
#include "cpuC6State.h"
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#define OPTION_C6_STATE_FEAT
#define F12_C6_STATE_SUPPORT
#define F14_ON_C6_STATE_SUPPORT
#define F15_OR_C6_STATE_SUPPORT
#if OPTION_C6_STATE == TRUE
#if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE)
#ifdef OPTION_FAMILY12H
#if OPTION_FAMILY12H == TRUE
#if OPTION_FAMILY12H_LN == TRUE
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureC6State;
#undef OPTION_C6_STATE_FEAT
#define OPTION_C6_STATE_FEAT &CpuFeatureC6State,
extern CONST C6_FAMILY_SERVICES ROMDATA F12C6Support;
#undef F12_C6_STATE_SUPPORT
#define F12_C6_STATE_SUPPORT {AMD_FAMILY_12_LN, &F12C6Support},
#if OPTION_EARLY_SAMPLES == TRUE
extern F_F12_ES_C6_INIT F12C6A0Workaround;
CONST F12_ES_C6_SUPPORT ROMDATA F12EarlySampleC6Support =
{
F12C6A0Workaround
};
#else
CONST F12_ES_C6_SUPPORT ROMDATA F12EarlySampleC6Support =
{
(PF_F12_ES_C6_INIT) CommonVoid
};
#endif
#endif
#endif
#endif
#ifdef OPTION_FAMILY14H
#if OPTION_FAMILY14H == TRUE
#if (OPTION_FAMILY14H_ON == TRUE)
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureC6State;
#undef OPTION_C6_STATE_FEAT
#define OPTION_C6_STATE_FEAT &CpuFeatureC6State,
extern CONST C6_FAMILY_SERVICES ROMDATA F14OnC6Support;
#undef F14_ON_C6_STATE_SUPPORT
#define F14_ON_C6_STATE_SUPPORT {AMD_FAMILY_14_ON, &F14OnC6Support},
#if (OPTION_EARLY_SAMPLES == TRUE)
extern F_F14_ON_ES_IS_C6_SUPPORTED F14IsC6DisabledEarlySample;
extern F_F14_ON_ES_C6_INIT F14C6A0Workaround;
CONST F14_ON_ES_C6_SUPPORT ROMDATA F14OnEarlySampleC6Support =
{
F14IsC6DisabledEarlySample,
F14C6A0Workaround
};
#else
CONST F14_ON_ES_C6_SUPPORT ROMDATA F14OnEarlySampleC6Support =
{
(PF_F14_ON_ES_IS_C6_SUPPORTED) CommonVoid,
(PF_F14_ON_ES_C6_INIT) CommonVoid
};
#endif
#endif
#endif
#endif
#ifdef OPTION_FAMILY15H
#if OPTION_FAMILY15H == TRUE
#if (OPTION_FAMILY15H_OR == TRUE)
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureC6State;
#undef OPTION_C6_STATE_FEAT
#define OPTION_C6_STATE_FEAT &CpuFeatureC6State,
extern CONST C6_FAMILY_SERVICES ROMDATA F15OrC6Support;
#undef F15_OR_C6_STATE_SUPPORT
#define F15_OR_C6_STATE_SUPPORT {AMD_FAMILY_15_OR, &F15OrC6Support},
#if (OPTION_EARLY_SAMPLES == TRUE)
extern F_F15_OR_ES_IS_C6_SUPPORTED F15OrIsC6DisabledEarlySample;
CONST F15_OR_ES_C6_SUPPORT ROMDATA F15OrEarlySampleC6Support =
{
F15OrIsC6DisabledEarlySample
};
#else
CONST F15_OR_ES_C6_SUPPORT ROMDATA F15OrEarlySampleC6Support =
{
(PF_F15_OR_ES_IS_C6_SUPPORTED) CommonVoid
};
#endif
#endif
#endif
#endif
#endif
#endif
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA C6FamilyServiceArray[] =
{
F12_C6_STATE_SUPPORT
F14_ON_C6_STATE_SUPPORT
F15_OR_C6_STATE_SUPPORT
{0, NULL}
};
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA C6FamilyServiceTable =
{
(sizeof (C6FamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
&C6FamilyServiceArray[0]
};
#endif // _OPTION_C6_STATE_INSTALL_H_

170
src/vendorcode/amd/agesa/f15/Config/OptionCpbInstall.h
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@ -1,170 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: Core Performance Boost
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 46389 $ @e \$Date: 2011-01-31 20:22:49 -0700 (Mon, 31 Jan 2011) $
*/
/*****************************************************************************
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
***************************************************************************/
#ifndef _OPTION_CPB_INSTALL_H_
#define _OPTION_CPB_INSTALL_H_
#include "cpuCpb.h"
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#define OPTION_CPB_FEAT
#define F10_CPB_SUPPORT
#define F12_CPB_SUPPORT
#define F14_ON_CPB_SUPPORT
#define F15_OR_CPB_SUPPORT
#if OPTION_CPB == TRUE
#if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE)
// Family 10h
#ifdef OPTION_FAMILY10H
#if OPTION_FAMILY10H == TRUE
#if OPTION_FAMILY10H_PH == TRUE
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCpb;
#undef OPTION_CPB_FEAT
#define OPTION_CPB_FEAT &CpuFeatureCpb,
extern CONST CPB_FAMILY_SERVICES ROMDATA F10CpbSupport;
#undef F10_CPB_SUPPORT
#define F10_CPB_SUPPORT {AMD_FAMILY_10_PH, &F10CpbSupport},
#endif
#endif
#endif
// Family 12h
#ifdef OPTION_FAMILY12H
#if OPTION_FAMILY12H == TRUE
#if OPTION_FAMILY12H_LN == TRUE
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCpb;
#undef OPTION_CPB_FEAT
#define OPTION_CPB_FEAT &CpuFeatureCpb,
extern CONST CPB_FAMILY_SERVICES ROMDATA F12CpbSupport;
#undef F12_CPB_SUPPORT
#define F12_CPB_SUPPORT {AMD_FAMILY_12_LN, &F12CpbSupport},
#if OPTION_EARLY_SAMPLES == TRUE
#if (AGESA_ENTRY_INIT_EARLY == TRUE)
extern F_F12_ES_CPB_INIT F12LnA1CpbHook;
CONST F12_ES_CPB_SUPPORT ROMDATA F12EarlySampleCpbSupport =
{
F12LnA1CpbHook
};
#else
CONST F12_ES_CPB_SUPPORT ROMDATA F12EarlySampleCpbSupport =
{
(PF_F12_ES_CPB_INIT) CommonVoid
};
#endif
#else
CONST F12_ES_CPB_SUPPORT ROMDATA F12EarlySampleCpbSupport =
{
(PF_F12_ES_CPB_INIT) CommonVoid
};
#endif
#endif
#endif
#endif
// Family 14h
#ifdef OPTION_FAMILY14H
#if OPTION_FAMILY14H == TRUE
#if OPTION_FAMILY14H_ON == TRUE
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCpb;
#undef OPTION_CPB_FEAT
#define OPTION_CPB_FEAT &CpuFeatureCpb,
extern CONST CPB_FAMILY_SERVICES ROMDATA F14OnCpbSupport;
#undef F14_ON_CPB_SUPPORT
#define F14_ON_CPB_SUPPORT {AMD_FAMILY_14_ON, &F14OnCpbSupport},
#endif
#endif
#endif
// Family 15h
#ifdef OPTION_FAMILY15H
#if OPTION_FAMILY15H == TRUE
#if (OPTION_FAMILY15H_OR == TRUE)
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCpb;
#undef OPTION_CPB_FEAT
#define OPTION_CPB_FEAT &CpuFeatureCpb,
extern CONST CPB_FAMILY_SERVICES ROMDATA F15OrCpbSupport;
#undef F15_OR_CPB_SUPPORT
#define F15_OR_CPB_SUPPORT {AMD_FAMILY_15_OR, &F15OrCpbSupport},
#if OPTION_EARLY_SAMPLES == TRUE
extern F_F15_OR_ES_IS_CPB_SUPPORTED F15OrIsCpbDisabledEarlySample;
CONST F15_OR_ES_CPB_SUPPORT ROMDATA F15OrEarlySampleCpbSupport =
{
F15OrIsCpbDisabledEarlySample
};
#else
CONST F15_OR_ES_CPB_SUPPORT ROMDATA F15OrEarlySampleCpbSupport =
{
(PF_F15_OR_ES_IS_CPB_SUPPORTED) CommonVoid
};
#endif
#endif
#endif
#endif
#endif
#endif
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA CpbFamilyServiceArray[] =
{
F10_CPB_SUPPORT
F12_CPB_SUPPORT
F14_ON_CPB_SUPPORT
F15_OR_CPB_SUPPORT
{0, NULL}
};
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA CpbFamilyServiceTable =
{
(sizeof (CpbFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
&CpbFamilyServiceArray[0]
};
#endif // _OPTION_CPB_INSTALL_H_

126
src/vendorcode/amd/agesa/f15/Config/OptionCpuCacheFlushOnHaltInstall.h
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@ -1,126 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: CPU Cache Flush On Halt
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 56186 $ @e \$Date: 2011-07-08 15:35:23 -0600 (Fri, 08 Jul 2011) $
*/
/*****************************************************************************
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
***************************************************************************/
#ifndef _OPTION_CPU_CACHEFLUSHONHALT_INSTALL_H_
#define _OPTION_CPU_CACHEFLUSHONHALT_INSTALL_H_
#include "cpuPostInit.h"
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#define OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT
#define F10_BL_CPU_CFOH_SUPPORT
#define F10_DA_CPU_CFOH_SUPPORT
#define F10_CPU_CFOH_SUPPORT
#define F15_OR_CPU_CFOH_SUPPORT
#define F15_TN_CPU_CFOH_SUPPORT
#if OPTION_CPU_CFOH == TRUE
#if (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE)
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCacheFlushOnHalt;
#ifdef OPTION_FAMILY10H
#if OPTION_FAMILY10H == TRUE
#undef OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT
#define OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT &CpuFeatureCacheFlushOnHalt,
#if OPTION_FAMILY10H_BL == TRUE
extern CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F10BlCacheFlushOnHalt;
#undef F10_BL_CPU_CFOH_SUPPORT
#define F10_BL_CPU_CFOH_SUPPORT {AMD_FAMILY_10_BL, &F10BlCacheFlushOnHalt},
#endif
#if OPTION_FAMILY10H_DA == TRUE
extern CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F10DaCacheFlushOnHalt;
#undef F10_DA_CPU_CFOH_SUPPORT
#define F10_DA_CPU_CFOH_SUPPORT {AMD_FAMILY_10_DA, &F10DaCacheFlushOnHalt},
#endif
#if (OPTION_FAMILY10H_RB == TRUE) || (OPTION_FAMILY10H_HY == TRUE) || (OPTION_FAMILY10H_PH == TRUE)
extern CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F10CacheFlushOnHalt;
#undef F10_CPU_CFOH_SUPPORT
#define F10_CPU_CFOH_SUPPORT {AMD_FAMILY_10_RB | AMD_FAMILY_10_HY | AMD_FAMILY_10_PH, &F10CacheFlushOnHalt},
#endif
#endif
#endif
#ifdef OPTION_FAMILY15H
#if OPTION_FAMILY15H == TRUE
#undef OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT
#define OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT &CpuFeatureCacheFlushOnHalt,
#if OPTION_FAMILY15H_OR == TRUE
extern CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F15OrCacheFlushOnHalt;
#undef F15_OR_CPU_CFOH_SUPPORT
#define F15_OR_CPU_CFOH_SUPPORT {AMD_FAMILY_15_OR, &F15OrCacheFlushOnHalt},
#endif
#if OPTION_FAMILY15H_TN == TRUE
extern CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F15TnCacheFlushOnHalt;
#undef F15_TN_CPU_CFOH_SUPPORT
#define F15_TN_CPU_CFOH_SUPPORT {AMD_FAMILY_15_TN, &F15TnCacheFlushOnHalt},
#endif
#endif
#endif
#endif
#endif
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA CacheFlushOnHaltFamilyServiceArray[] =
{
F10_BL_CPU_CFOH_SUPPORT
F10_DA_CPU_CFOH_SUPPORT
F10_CPU_CFOH_SUPPORT
F15_OR_CPU_CFOH_SUPPORT
F15_TN_CPU_CFOH_SUPPORT
{0, NULL}
};
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA CacheFlushOnHaltFamilyServiceTable =
{
(sizeof (CacheFlushOnHaltFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
&CacheFlushOnHaltFamilyServiceArray[0]
};
#endif // _OPTION_CPU_CACHEFLUSHONHALT_INSTALL_H_

120
src/vendorcode/amd/agesa/f15/Config/OptionCpuCoreLevelingInstall.h
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@ -1,120 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: CPU Core Leveling
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 56186 $ @e \$Date: 2011-07-08 15:35:23 -0600 (Fri, 08 Jul 2011) $
*/
/*****************************************************************************
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
***************************************************************************/
#ifndef _OPTION_CPU_CORELEVELING_INSTALL_H_
#define _OPTION_CPU_CORELEVELING_INSTALL_H_
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#define OPTION_CPU_CORE_LEVELING_FEAT
#define F10_REVE_CPU_CORELEVELING_SUPPORT
#define F10_REVD_CPU_CORELEVELING_SUPPORT
#define F10_REVC_CPU_CORELEVELING_SUPPORT
#define F15_OR_CPU_CORELEVELING_SUPPORT
#define F15_TN_CPU_CORELEVELING_SUPPORT
#if OPTION_CPU_CORELEVLING == TRUE
#if (AGESA_ENTRY_INIT_EARLY == TRUE)
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCoreLeveling;
// Family 10h
#if OPTION_FAMILY10H == TRUE
#undef OPTION_CPU_CORE_LEVELING_FEAT
#define OPTION_CPU_CORE_LEVELING_FEAT &CpuFeatureCoreLeveling,
#if OPTION_FAMILY10H_HY == TRUE
extern CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F10RevDCoreLeveling;
#undef F10_REVD_CPU_CORELEVELING_SUPPORT
#define F10_REVD_CPU_CORELEVELING_SUPPORT {AMD_FAMILY_10_HY, &F10RevDCoreLeveling},
#endif
#if (OPTION_FAMILY10H_RB == TRUE) || (OPTION_FAMILY10H_BL == TRUE) || (OPTION_FAMILY10H_DA == TRUE)
extern CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F10RevCCoreLeveling;
#undef F10_REVC_CPU_CORELEVELING_SUPPORT
#define F10_REVC_CPU_CORELEVELING_SUPPORT {AMD_FAMILY_10_RB | AMD_FAMILY_10_BL | AMD_FAMILY_10_DA, &F10RevCCoreLeveling},
#endif
#if (OPTION_FAMILY10H_PH == TRUE)
extern CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F10RevECoreLeveling;
#undef F10_REVE_CPU_CORELEVELING_SUPPORT
#define F10_REVE_CPU_CORELEVELING_SUPPORT {AMD_FAMILY_10_PH, &F10RevECoreLeveling},
#endif
#endif
// Family 15h
#if OPTION_FAMILY15H == TRUE
#undef OPTION_CPU_CORE_LEVELING_FEAT
#define OPTION_CPU_CORE_LEVELING_FEAT &CpuFeatureCoreLeveling,
#if (OPTION_FAMILY15H_OR == TRUE)
extern CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F15OrCoreLeveling;
#undef F15_OR_CPU_CORELEVELING_SUPPORT
#define F15_OR_CPU_CORELEVELING_SUPPORT {AMD_FAMILY_15_OR, &F15OrCoreLeveling},
#endif
#if (OPTION_FAMILY15H_TN == TRUE)
extern CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F15TnCoreLeveling;
#undef F15_TN_CPU_CORELEVELING_SUPPORT
#define F15_TN_CPU_CORELEVELING_SUPPORT {AMD_FAMILY_15_TN, &F15TnCoreLeveling},
#endif
#endif
#endif
#endif
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA CoreLevelingFamilyServiceArray[] =
{
F15_TN_CPU_CORELEVELING_SUPPORT
F15_OR_CPU_CORELEVELING_SUPPORT
F10_REVE_CPU_CORELEVELING_SUPPORT
F10_REVD_CPU_CORELEVELING_SUPPORT
F10_REVC_CPU_CORELEVELING_SUPPORT
{0, NULL}
};
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA CoreLevelingFamilyServiceTable =
{
(sizeof (CoreLevelingFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
&CoreLevelingFamilyServiceArray[0]
};
#endif // _OPTION_CPU_CORELEVELING_INSTALL_H_

382
src/vendorcode/amd/agesa/f15/Config/OptionCpuFamiliesInstall.h
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@ -1,382 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Install of all appropriate CPU family specific support.
*
* This file generates the defaults tables for all family specific
* combinations.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Core
* @e \$Revision: 50628 $ @e \$Date: 2011-04-12 15:18:38 -0600 (Tue, 12 Apr 2011) $
*/
/*****************************************************************************
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
***************************************************************************/
/* Default all CPU Specific Service members to off. They
will be enabled as needed by cross referencing families
with entry points in the family / model install files. */
#define GET_PSTATE_POWER FALSE
#define GET_PSTATE_FREQ FALSE
#define DISABLE_PSTATE FALSE
#define TRANSITION_PSTATE FALSE
#define PROC_IDD_MAX FALSE
#define GET_TSC_RATE FALSE
#define PSTATE_TRANSITION_LATENCY FALSE
#define GET_PSTATE_REGISTER_INFO FALSE
#define GET_PSTATE_MAX_STATE FALSE
#define SET_PSTATE_LEVELING_REG FALSE
#define GET_NB_FREQ FALSE
#define GET_NB_IDD_MAX FALSE
#define IS_NBCOF_INIT_NEEDED FALSE
#define AP_INITIAL_LAUNCH FALSE
#define GET_AP_MAILBOX_FROM_HW FALSE
#define SET_AP_CORE_NUMBER FALSE
#define GET_AP_CORE_NUMBER FALSE
#define TRANSFER_AP_CORE_NUMBER FALSE
#define ID_POSITION_INITIAL_APICID FALSE
#define SAVE_FEATURES FALSE
#define WRITE_FEATURES FALSE
#define SET_DOWN_CORE_REG FALSE
#define SET_WARM_RESET_FLAG FALSE
#define GET_WARM_RESET_FLAG FALSE
#define USES_REGISTER_TABLES FALSE
#define BASE_FAMILY_PCI FALSE
#define MODEL_SPECIFIC_PCI FALSE
#define BASE_FAMILY_MSR FALSE
#define MODEL_SPECIFIC_MSR FALSE
#define BRAND_STRING1 FALSE
#define BRAND_STRING2 FALSE
#define BASE_FAMILY_HT_PCI FALSE
#define MODEL_SPECIFIC_HT_PCI FALSE
#define BASE_FAMILY_WORKAROUNDS FALSE
#define GET_PATCHES FALSE
#define GET_PATCHES_EQUIVALENCE_TABLE FALSE
#define GET_CACHE_INFO FALSE
#define GET_SYSTEM_PM_TABLE FALSE
#define GET_WHEA_INIT FALSE
#define GET_CFOH_REG FALSE
#define GET_PLATFORM_TYPE_SPECIFIC_INFO FALSE
#define IS_NB_PSTATE_ENABLED FALSE
/*
* Pull in family specific services based on entry point
*/
#if AGESA_ENTRY_INIT_RESET == TRUE
#undef ID_POSITION_INITIAL_APICID
#define ID_POSITION_INITIAL_APICID TRUE
#undef GET_AP_MAILBOX_FROM_HW
#define GET_AP_MAILBOX_FROM_HW TRUE
#undef SET_WARM_RESET_FLAG
#define SET_WARM_RESET_FLAG TRUE
#undef GET_WARM_RESET_FLAG
#define GET_WARM_RESET_FLAG TRUE
#undef GET_CACHE_INFO
#define GET_CACHE_INFO TRUE
#undef GET_AP_CORE_NUMBER
#define GET_AP_CORE_NUMBER TRUE
#undef TRANSFER_AP_CORE_NUMBER
#define TRANSFER_AP_CORE_NUMBER TRUE
#endif
#if AGESA_ENTRY_INIT_EARLY == TRUE
#undef TRANSITION_PSTATE
#define TRANSITION_PSTATE TRUE
#undef DISABLE_PSTATE
#define DISABLE_PSTATE TRUE
#undef PROC_IDD_MAX
#define PROC_IDD_MAX TRUE
#undef GET_TSC_RATE
#define GET_TSC_RATE TRUE
#undef GET_NB_FREQ
#define GET_NB_FREQ TRUE
#undef GET_NB_IDD_MAX
#define GET_NB_IDD_MAX TRUE
#undef IS_NBCOF_INIT_NEEDED
#define IS_NBCOF_INIT_NEEDED TRUE
#undef AP_INITIAL_LAUNCH
#define AP_INITIAL_LAUNCH TRUE
#undef GET_AP_MAILBOX_FROM_HW
#define GET_AP_MAILBOX_FROM_HW TRUE
#undef SET_AP_CORE_NUMBER
#define SET_AP_CORE_NUMBER TRUE
#undef GET_AP_CORE_NUMBER
#define GET_AP_CORE_NUMBER TRUE
#undef TRANSFER_AP_CORE_NUMBER
#define TRANSFER_AP_CORE_NUMBER TRUE
#undef ID_POSITION_INITIAL_APICID
#define ID_POSITION_INITIAL_APICID TRUE
#undef SET_DOWN_CORE_REG
#define SET_DOWN_CORE_REG TRUE
#undef SET_WARM_RESET_FLAG
#define SET_WARM_RESET_FLAG TRUE
#undef GET_WARM_RESET_FLAG
#define GET_WARM_RESET_FLAG TRUE
#undef USES_REGISTER_TABLES
#define USES_REGISTER_TABLES TRUE
#undef BASE_FAMILY_PCI
#define BASE_FAMILY_PCI TRUE
#undef MODEL_SPECIFIC_PCI
#define MODEL_SPECIFIC_PCI TRUE
#undef BASE_FAMILY_MSR
#define BASE_FAMILY_MSR TRUE
#undef MODEL_SPECIFIC_MSR
#define MODEL_SPECIFIC_MSR TRUE
#undef BRAND_STRING1
#define BRAND_STRING1 TRUE
#undef BRAND_STRING2
#define BRAND_STRING2 TRUE
#undef BASE_FAMILY_HT_PCI
#define BASE_FAMILY_HT_PCI TRUE
#undef MODEL_SPECIFIC_HT_PCI
#define MODEL_SPECIFIC_HT_PCI TRUE
#undef BASE_FAMILY_WORKAROUNDS
#define BASE_FAMILY_WORKAROUNDS TRUE
#undef GET_PATCHES
#define GET_PATCHES TRUE
#undef GET_PATCHES_EQUIVALENCE_TABLE
#define GET_PATCHES_EQUIVALENCE_TABLE TRUE
#undef GET_SYSTEM_PM_TABLE
#define GET_SYSTEM_PM_TABLE TRUE
#undef GET_CACHE_INFO
#define GET_CACHE_INFO TRUE
#undef GET_PLATFORM_TYPE_SPECIFIC_INFO
#define GET_PLATFORM_TYPE_SPECIFIC_INFO TRUE
#undef IS_NB_PSTATE_ENABLED
#define IS_NB_PSTATE_ENABLED TRUE
#endif
#if AGESA_ENTRY_INIT_POST == TRUE
#undef ID_POSITION_INITIAL_APICID
#define ID_POSITION_INITIAL_APICID TRUE
#undef GET_PSTATE_POWER
#define GET_PSTATE_POWER TRUE
#undef GET_PSTATE_FREQ
#define GET_PSTATE_FREQ TRUE
#undef TRANSITION_PSTATE
#define TRANSITION_PSTATE TRUE
#undef PROC_IDD_MAX
#define PROC_IDD_MAX TRUE
#undef GET_AP_CORE_NUMBER
#define GET_AP_CORE_NUMBER TRUE
#undef GET_PSTATE_REGISTER_INFO
#define GET_PSTATE_REGISTER_INFO TRUE
#undef GET_PSTATE_MAX_STATE
#define GET_PSTATE_MAX_STATE TRUE
#undef SET_PSTATE_LEVELING_REG
#define SET_PSTATE_LEVELING_REG TRUE
#undef SET_WARM_RESET_FLAG
#define SET_WARM_RESET_FLAG TRUE
#undef GET_WARM_RESET_FLAG
#define GET_WARM_RESET_FLAG TRUE
#undef SAVE_FEATURES
#define SAVE_FEATURES TRUE
#undef WRITE_FEATURES
#define WRITE_FEATURES TRUE
#undef GET_CFOH_REG
#define GET_CFOH_REG TRUE
#undef IS_NB_PSTATE_ENABLED
#define IS_NB_PSTATE_ENABLED TRUE
#endif
#if AGESA_ENTRY_INIT_ENV == TRUE
#endif
#if AGESA_ENTRY_INIT_MID == TRUE
#endif
#if AGESA_ENTRY_INIT_LATE == TRUE
#undef GET_AP_CORE_NUMBER
#define GET_AP_CORE_NUMBER TRUE
#undef GET_PSTATE_FREQ
#define GET_PSTATE_FREQ TRUE
#undef TRANSITION_PSTATE
#define TRANSITION_PSTATE TRUE
#undef PSTATE_TRANSITION_LATENCY
#define PSTATE_TRANSITION_LATENCY TRUE
#undef GET_WHEA_INIT
#define GET_WHEA_INIT TRUE
#undef GET_PLATFORM_TYPE_SPECIFIC_INFO
#define GET_PLATFORM_TYPE_SPECIFIC_INFO TRUE
#undef GET_TSC_RATE
#define GET_TSC_RATE TRUE
#undef BRAND_STRING1
#define BRAND_STRING1 TRUE
#undef BRAND_STRING2
#define BRAND_STRING2 TRUE
#endif
#if AGESA_ENTRY_INIT_S3SAVE == TRUE
#endif
#if AGESA_ENTRY_INIT_RESUME == TRUE
#undef GET_CFOH_REG
#define GET_CFOH_REG TRUE
#endif
#if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE
#endif
#if AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE
#undef ID_POSITION_INITIAL_APICID
#define ID_POSITION_INITIAL_APICID TRUE
#endif
/*
* Initialize PCI MMIO mask to 0
*/
#define FAMILY_MMIO_BASE_MASK (0ull)
/*
* Initialize all families to disabled
*/
#define OPT_F10_TABLE
#define OPT_F12_TABLE
#define OPT_F14_TABLE
#define OPT_F15_TABLE
#define OPT_F10_ID_TABLE
#define OPT_F12_ID_TABLE
#define OPT_F14_ID_TABLE
#define OPT_F15_ID_TABLE
/*
* Install family specific support
*/
#if (OPTION_FAMILY10H == TRUE)
#include "OptionFamily10hInstall.h"
#endif
#if (OPTION_FAMILY12H == TRUE)
#include "OptionFamily12hInstall.h"
#endif
#if (OPTION_FAMILY14H == TRUE)
#include "OptionFamily14hInstall.h"
#endif
#if (OPTION_FAMILY15H_OR == TRUE) || (OPTION_FAMILY15H_TN == TRUE) || (OPTION_FAMILY15H_KM == TRUE)
#include "OptionFamily15hInstall.h"
#endif
/*
* Process PCI MMIO mask
*/
// If size is 0, but base is not, break the build.
#if (CFG_PCI_MMIO_BASE != 0) && (CFG_PCI_MMIO_SIZE == 0)
#error BLDCFG: Invalid PCI MMIO size -- acceptable values are 1, 2, 4, 8, 16, 32, 64, 128, and 256
#endif
// If base is 0, but size is not, break the build.
#if (CFG_PCI_MMIO_BASE == 0) && (CFG_PCI_MMIO_SIZE != 0)
#error BLDCFG: Invalid PCI MMIO base -- must be 8MB or greater
#endif
#if (CFG_PCI_MMIO_BASE != 0) && (CFG_PCI_MMIO_SIZE != 0)
// Both are non-zero, begin further processing.
// Heap runs from 4MB to 8MB. Disallow any addresses below 8MB.
#if (CFG_PCI_MMIO_BASE < 0x800000)
#error BLDCFG: Invalid PCI MMIO base -- must be 8MB or greater
#endif
// Break the build if the address is too high for the enabled families.
#if ((CFG_PCI_MMIO_BASE & FAMILY_MMIO_BASE_MASK) != 0)
#error BLDCFG: Invalid PCI MMIO base address for the installed CPU families
#endif
// If the size parameter is not valid, break the build.
#if (CFG_PCI_MMIO_SIZE != 1) && (CFG_PCI_MMIO_SIZE != 2) && (CFG_PCI_MMIO_SIZE != 4) && (CFG_PCI_MMIO_SIZE != 8) && (CFG_PCI_MMIO_SIZE != 16)
#if (CFG_PCI_MMIO_SIZE != 32) && (CFG_PCI_MMIO_SIZE != 64) && (CFG_PCI_MMIO_SIZE != 128) && (CFG_PCI_MMIO_SIZE != 256)
#error BLDCFG: Invalid PCI MMIO size -- acceptable values are 1, 2, 4, 8, 16, 32, 64, 128, and 256
#endif
#endif
#define PCI_MMIO_ALIGNMENT ((0x100000 * CFG_PCI_MMIO_SIZE) - 1)
// If the base is not aligned according to size, break the build.
#if ((CFG_PCI_MMIO_BASE & PCI_MMIO_ALIGNMENT) != 0)
#error BLDCFG: Invalid PCI MMIO base -- must be properly aligned according to MMIO size
#endif
#undef PCI_MMIO_ALIGNMENT
#endif
/*
* Process sockets / modules
*/
#ifndef ADVCFG_PLATFORM_SOCKETS
#error BLDOPT Set Family supported sockets.
#endif
#ifndef ADVCFG_PLATFORM_MODULES
#error BLDOPT Set Family supported modules.
#endif
CONST OPTIONS_CONFIG_TOPOLOGY ROMDATA TopologyConfiguration =
{
ADVCFG_PLATFORM_SOCKETS,
ADVCFG_PLATFORM_MODULES
};
/*
* Instantiate global data needed for processor identification
*/
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA CpuSupportedFamiliesArray[] =
{
OPT_F10_TABLE
OPT_F12_TABLE
OPT_F14_TABLE
OPT_F15_TABLE
};
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA CpuSupportedFamiliesTable =
{
(sizeof (CpuSupportedFamiliesArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
&CpuSupportedFamiliesArray[0]
};
CONST CPU_LOGICAL_ID_FAMILY_XLAT ROMDATA CpuSupportedFamilyIdArray[] =
{
OPT_F10_ID_TABLE
OPT_F12_ID_TABLE
OPT_F14_ID_TABLE
OPT_F15_ID_TABLE
};
CONST CPU_FAMILY_ID_XLAT_TABLE ROMDATA CpuSupportedFamilyIdTable =
{
(sizeof (CpuSupportedFamilyIdArray) / sizeof (CPU_LOGICAL_ID_FAMILY_XLAT)),
CpuSupportedFamilyIdArray
};

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@ -1,80 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Install of multiple CPU features.
*
* Aggregates enabled CPU features into a list for the dispatcher to process.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 54493 $ @e \$Date: 2011-06-08 15:21:06 -0600 (Wed, 08 Jun 2011) $
*/
/*****************************************************************************
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
***************************************************************************/
#ifndef _OPTION_CPU_FEATURES_INSTALL_H_
#define _OPTION_CPU_FEATURES_INSTALL_H_
#include "OptionHwC1eInstall.h"
#include "OptionMsgBasedC1eInstall.h"
#include "OptionSwC1eInstall.h"
#include "OptionL3FeaturesInstall.h"
#include "OptionCpuCoreLevelingInstall.h"
#include "OptionIoCstateInstall.h"
#include "OptionC6Install.h"
#include "OptionCpbInstall.h"
#include "OptionCpuCacheFlushOnHaltInstall.h"
#include "OptionPstateHpcModeInstall.h"
#include "OptionLowPwrPstateInstall.h"
#include "OptionApmInstall.h"
#include "OptionPreserveMailboxInstall.h"
CONST CPU_FEATURE_DESCRIPTOR* ROMDATA SupportedCpuFeatureList[] =
{
OPTION_HW_C1E_FEAT
OPTION_MSG_BASED_C1E_FEAT
OPTION_SW_C1E_FEAT
OPTION_L3_FEAT
OPTION_CPU_CORE_LEVELING_FEAT
OPTION_IO_CSTATE_FEAT
OPTION_C6_STATE_FEAT
OPTION_CPB_FEAT
OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT
OPTION_CPU_PSTATE_HPC_MODE_FEAT // this function should be run before low power pstate for prochot
OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT_FEAT // this function should be run before creating ACPI objects and after Pstate initialization
OPTION_CPU_APM_FEAT
OPTION_PRESERVE_MAILBOX_FEAT
NULL
};
#endif // _OPTION_CPU_FEATURES_INSTALL_H_

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src/vendorcode/amd/agesa/f15/Config/OptionDmiInstall.h
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@ -1,213 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: DMI
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $
*/
/*****************************************************************************
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
***************************************************************************/
#ifndef _OPTION_DMI_INSTALL_H_
#define _OPTION_DMI_INSTALL_H_
#include "cpuLateInit.h"
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#if AGESA_ENTRY_INIT_LATE == TRUE
#ifndef OPTION_DMI
#error BLDOPT: Option not defined: "OPTION_DMI"
#endif
#if OPTION_DMI == TRUE
OPTION_DMI_FEATURE GetDmiInfoMain;
OPTION_DMI_RELEASE_BUFFER ReleaseDmiBuffer;
#define USER_DMI_OPTION &GetDmiInfoMain
#define USER_DMI_RELEASE_BUFFER &ReleaseDmiBuffer
// This additional check keeps AP launch routines from being unnecessarily included
// in single socket systems.
#if OPTION_MULTISOCKET == TRUE
#define CPU_DMI_AP_GET_TYPE4_TYPE7 {AP_LATE_TASK_GET_TYPE4_TYPE7, (IMAGE_ENTRY) GetType4Type7Info},
#else
#define CPU_DMI_AP_GET_TYPE4_TYPE7
#endif
// Family 10
#ifdef OPTION_FAMILY10H
#if OPTION_FAMILY10H == TRUE
extern PROC_FAMILY_TABLE ProcFamily10DmiTable;
#define FAM10_DMI_SUPPORT FAM10_ENABLED,
#define FAM10_DMI_TABLE &ProcFamily10DmiTable,
#else
#define FAM10_DMI_SUPPORT
#define FAM10_DMI_TABLE
#endif
#else
#define FAM10_DMI_SUPPORT
#define FAM10_DMI_TABLE
#endif
// Family 12
#ifdef OPTION_FAMILY12H
#if OPTION_FAMILY12H == TRUE
extern PROC_FAMILY_TABLE ProcFamily12DmiTable;
#define FAM12_DMI_SUPPORT FAM12_ENABLED,
#define FAM12_DMI_TABLE &ProcFamily12DmiTable,
#else
#define FAM12_DMI_SUPPORT
#define FAM12_DMI_TABLE
#endif
#else
#define FAM12_DMI_SUPPORT
#define FAM12_DMI_TABLE
#endif
// Family 14
#ifdef OPTION_FAMILY14H
#if OPTION_FAMILY14H == TRUE
extern PROC_FAMILY_TABLE ProcFamily14DmiTable;
#define FAM14_DMI_SUPPORT FAM14_ENABLED,
#define FAM14_DMI_TABLE &ProcFamily14DmiTable,
#else
#define FAM14_DMI_SUPPORT
#define FAM14_DMI_TABLE
#endif
#else
#define FAM14_DMI_SUPPORT
#define FAM14_DMI_TABLE
#endif
// Family 15
#ifdef OPTION_FAMILY15H
#if OPTION_FAMILY15H == TRUE
#if OPTION_FAMILY15H_OR == TRUE
extern PROC_FAMILY_TABLE ProcFamily15OrDmiTable;
#define FAM15_OR_DMI_SUPPORT FAM15_OR_ENABLED,
#define FAM15_OR_DMI_TABLE &ProcFamily15OrDmiTable,
#else
#define FAM15_OR_DMI_SUPPORT
#define FAM15_OR_DMI_TABLE
#endif
#if OPTION_FAMILY15H_TN == TRUE
extern PROC_FAMILY_TABLE ProcFamily15TnDmiTable;
#define FAM15_TN_DMI_SUPPORT FAM15_TN_ENABLED,
#define FAM15_TN_DMI_TABLE &ProcFamily15TnDmiTable,
#else
#define FAM15_TN_DMI_SUPPORT
#define FAM15_TN_DMI_TABLE
#endif
#else
#define FAM15_OR_DMI_SUPPORT
#define FAM15_OR_DMI_TABLE
#define FAM15_TN_DMI_SUPPORT
#define FAM15_TN_DMI_TABLE
#endif
#else
#define FAM15_OR_DMI_SUPPORT
#define FAM15_OR_DMI_TABLE
#define FAM15_TN_DMI_SUPPORT
#define FAM15_TN_DMI_TABLE
#endif
#else
OPTION_DMI_FEATURE GetDmiInfoStub;
OPTION_DMI_RELEASE_BUFFER ReleaseDmiBufferStub;
#define USER_DMI_OPTION GetDmiInfoStub
#define USER_DMI_RELEASE_BUFFER ReleaseDmiBufferStub
#define FAM10_DMI_SUPPORT
#define FAM10_DMI_TABLE
#define FAM12_DMI_SUPPORT
#define FAM12_DMI_TABLE
#define FAM14_DMI_SUPPORT
#define FAM14_DMI_TABLE
#define FAM15_OR_DMI_SUPPORT
#define FAM15_OR_DMI_TABLE
#define FAM15_TN_DMI_SUPPORT
#define FAM15_TN_DMI_TABLE
#define CPU_DMI_AP_GET_TYPE4_TYPE7
#endif
#else
OPTION_DMI_FEATURE GetDmiInfoStub;
OPTION_DMI_RELEASE_BUFFER ReleaseDmiBufferStub;
#define USER_DMI_OPTION GetDmiInfoStub
#define USER_DMI_RELEASE_BUFFER ReleaseDmiBufferStub
#define FAM10_DMI_SUPPORT
#define FAM10_DMI_TABLE
#define FAM12_DMI_SUPPORT
#define FAM12_DMI_TABLE
#define FAM14_DMI_SUPPORT
#define FAM14_DMI_TABLE
#define FAM15_OR_DMI_SUPPORT
#define FAM15_OR_DMI_TABLE
#define FAM15_TN_DMI_SUPPORT
#define FAM15_TN_DMI_TABLE
#define CPU_DMI_AP_GET_TYPE4_TYPE7
#endif
/// DMI supported families enum
typedef enum {
FAM10_DMI_SUPPORT ///< Conditionally define F10 support
FAM12_DMI_SUPPORT ///< Conditionally define F12 support
FAM14_DMI_SUPPORT ///< Conditionally define F14 support
FAM15_OR_DMI_SUPPORT ///< Conditionally define F15 OR support
FAM15_TN_DMI_SUPPORT ///< Conditionally define F15 TN support
NUM_DMI_FAMILIES ///< Number of installed families
} AGESA_DMI_SUPPORTED_FAM;
/* Declare the Family List. An array of pointers to tables that each describe a family */
CONST PROC_FAMILY_TABLE ROMDATA *ProcTables[] = {
FAM10_DMI_TABLE
FAM12_DMI_TABLE
FAM14_DMI_TABLE
FAM15_OR_DMI_TABLE
FAM15_TN_DMI_TABLE
NULL
};
/* Declare the instance of the DMI option configuration structure */
CONST OPTION_DMI_CONFIGURATION ROMDATA OptionDmiConfiguration = {
DMI_STRUCT_VERSION,
USER_DMI_OPTION,
USER_DMI_RELEASE_BUFFER,
NUM_DMI_FAMILIES,
(VOID *((*)[])) &ProcTables // Compiler says array size must match struct decl
};
#endif // _OPTION_DMI_INSTALL_H_

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@ -1,988 +0,0 @@
/*********************************************************************************
;
; Copyright (C) 2012 Advanced Micro Devices, Inc.
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; * Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; * Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; * Neither the name of Advanced Micro Devices, Inc. nor the names of
; its contributors may be used to endorse or promote products derived
; from this software without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;
;*********************************************************************************/
#ifndef _OPTION_FCH_INSTALL_H_
#define _OPTION_FCH_INSTALL_H_
#include "AmdFch.h"
#define FCH_SUPPORT FALSE
/* ACPI block register offset definitions */
#define PM1_STATUS_OFFSET 0x00
#define PM1_ENABLE_OFFSET 0x02
#define PM_CONTROL_OFFSET 0x04
#define PM_TIMER_OFFSET 0x08
#define CPU_CONTROL_OFFSET 0x10
#define EVENT_STATUS_OFFSET 0x20
#define EVENT_ENABLE_OFFSET 0x24
#if FCH_SUPPORT == TRUE
/*
* FCH subfunctions
*/
#ifdef AGESA_ENTRY_INIT_RESET
#if AGESA_ENTRY_INIT_RESET == TRUE
extern FCH_TASK_ENTRY FchInitResetHwAcpiP;
extern FCH_TASK_ENTRY FchInitResetHwAcpi;
extern FCH_TASK_ENTRY FchInitResetAb;
extern FCH_TASK_ENTRY FchInitResetSpi;
extern FCH_TASK_ENTRY FchInitResetGec;
extern FCH_TASK_ENTRY FchInitResetSata;
extern FCH_TASK_ENTRY FchInitResetLpc;
extern FCH_TASK_ENTRY FchInitResetPcib;
extern FCH_TASK_ENTRY FchInitResetPcie;
extern FCH_TASK_ENTRY FchInitResetGpp;
extern FCH_TASK_ENTRY FchInitResetUsb;
extern FCH_TASK_ENTRY FchInitResetEhci;
extern FCH_TASK_ENTRY FchInitResetOhci;
extern FCH_TASK_ENTRY FchInitResetXhci;
extern FCH_TASK_ENTRY FchInitResetImc;
#endif
#endif
#ifdef AGESA_ENTRY_INIT_ENV
#if AGESA_ENTRY_INIT_ENV == TRUE
extern FCH_TASK_ENTRY FchInitEnvUsbXhci;
extern FCH_TASK_ENTRY FchInitEnvUsbOhci;
extern FCH_TASK_ENTRY FchInitEnvUsbEhci;
extern FCH_TASK_ENTRY FchInitEnvUsb;
extern FCH_TASK_ENTRY FchInitEnvAb;
extern FCH_TASK_ENTRY FchInitEnvGpp;
extern FCH_TASK_ENTRY FchInitEnvPcie;
extern FCH_TASK_ENTRY FchInitEnvPcib;
extern FCH_TASK_ENTRY FchInitEnvHwAcpiP;
extern FCH_TASK_ENTRY FchInitEnvHwAcpi;
extern FCH_TASK_ENTRY FchInitEnvAbSpecial;
extern FCH_TASK_ENTRY FchInitEnvSpi;
extern FCH_TASK_ENTRY FchInitEnvGec;
extern FCH_TASK_ENTRY FchInitEnvSata;
extern FCH_TASK_ENTRY FchInitEnvIde;
extern FCH_TASK_ENTRY FchInitEnvSd;
extern FCH_TASK_ENTRY FchInitEnvIr;
extern FCH_TASK_ENTRY FchInitEnvAzalia;
extern FCH_TASK_ENTRY FchInitEnvHwm;
extern FCH_TASK_ENTRY FchInitEnvImc;
#endif
#endif
#ifdef AGESA_ENTRY_INIT_MID
#if AGESA_ENTRY_INIT_MID == TRUE
extern FCH_TASK_ENTRY FchInitMidHwm;
extern FCH_TASK_ENTRY FchInitMidAzalia;
extern FCH_TASK_ENTRY FchInitMidGec;
extern FCH_TASK_ENTRY FchInitMidSata;
extern FCH_TASK_ENTRY FchInitMidIde;
extern FCH_TASK_ENTRY FchInitMidAb;
extern FCH_TASK_ENTRY FchInitMidUsb;
extern FCH_TASK_ENTRY FchInitMidUsbEhci;
extern FCH_TASK_ENTRY FchInitMidUsbOhci;
extern FCH_TASK_ENTRY FchInitMidUsbXhci;
extern FCH_TASK_ENTRY FchInitMidImc;
#endif
#endif
#ifdef AGESA_ENTRY_INIT_LATE
#if AGESA_ENTRY_INIT_LATE == TRUE
extern FCH_TASK_ENTRY FchInitLateHwAcpi;
extern FCH_TASK_ENTRY FchInitLateSpi;
extern FCH_TASK_ENTRY FchInitLateGec;
extern FCH_TASK_ENTRY FchInitLateSata;
extern FCH_TASK_ENTRY FchInitLateIde;
extern FCH_TASK_ENTRY FchInitLatePcib;
extern FCH_TASK_ENTRY FchInitLateAb;
extern FCH_TASK_ENTRY FchInitLatePcie;
extern FCH_TASK_ENTRY FchInitLateGpp;
extern FCH_TASK_ENTRY FchInitLateUsb;
extern FCH_TASK_ENTRY FchInitLateUsbEhci;
extern FCH_TASK_ENTRY FchInitLateUsbOhci;
extern FCH_TASK_ENTRY FchInitLateUsbXhci;
extern FCH_TASK_ENTRY FchInitLateImc;
extern FCH_TASK_ENTRY FchInitLateAzalia;
extern FCH_TASK_ENTRY FchInitLateHwm;
#endif
#endif
extern FCH_TASK_ENTRY FchTaskDummy;
extern FCH_TASK_ENTRY FchGppHotplugSmiCallback;
/* FCH Interface entries */
extern FCH_INIT CommonFchInitStub;
/* FCH Interface entries */
#ifdef AGESA_ENTRY_INIT_RESET
#if AGESA_ENTRY_INIT_RESET == TRUE
extern FCH_INIT FchInitReset;
extern FCH_INIT FchResetConstructor;
#define FP_FCH_INIT_RESET &FchInitReset
#define FP_FCH_INIT_RESET_CONSTRUCT &FchResetConstructor
#else
#define FP_FCH_INIT_RESET &CommonFchInitStub
#define FP_FCH_INIT_RESET_CONSTRUCT &CommonFchInitStub
#endif
#endif
#ifdef AGESA_ENTRY_INIT_ENV
#if AGESA_ENTRY_INIT_ENV == TRUE
extern FCH_INIT FchInitEnv;
extern FCH_INIT FchEnvConstructor;
#define FP_FCH_INIT_ENV &FchInitEnv
#define FP_FCH_INIT_ENV_CONSTRUCT &FchEnvConstructor
#else
#define FP_FCH_INIT_ENV &CommonFchInitStub
#define FP_FCH_INIT_ENV_CONSTRUCT &CommonFchInitStub
#endif
#endif
#ifdef AGESA_ENTRY_INIT_MID
#if AGESA_ENTRY_INIT_MID == TRUE
extern FCH_INIT FchInitMid;
extern FCH_INIT FchMidConstructor;
#define FP_FCH_INIT_MID &FchInitMid
#define FP_FCH_INIT_MID_CONSTRUCT &FchMidConstructor
#else
#define FP_FCH_INIT_MID &CommonFchInitStub
#define FP_FCH_INIT_MID_CONSTRUCT &CommonFchInitStub
#endif
#endif
#ifdef AGESA_ENTRY_INIT_LATE
#if AGESA_ENTRY_INIT_LATE == TRUE
extern FCH_INIT FchInitLate;
extern FCH_INIT FchLateConstructor;
#define FP_FCH_INIT_LATE &FchInitLate
#define FP_FCH_INIT_LATE_CONSTRUCT &FchLateConstructor
#else
#define FP_FCH_INIT_LATE &CommonFchInitStub
#define FP_FCH_INIT_LATE_CONSTRUCT &CommonFchInitStub
#endif
#endif
/* FCH subcomponent build options */
#undef FCH_NO_HWACPI_SUPPORT
#undef FCH_NO_AB_SUPPORT
#undef FCH_NO_SPI_SUPPORT
#undef FCH_NO_GEC_SUPPORT
#undef FCH_NO_SATA_SUPPORT
#undef FCH_NO_IDE_SUPPORT
#undef FCH_NO_LPC_SUPPORT
#undef FCH_NO_PCIB_SUPPORT
#undef FCH_NO_PCIE_SUPPORT
#undef FCH_NO_GPP_SUPPORT
#undef FCH_NO_USB_SUPPORT
#undef FCH_NO_EHCI_SUPPORT
#undef FCH_NO_OHCI_SUPPORT
#undef FCH_NO_XHCI_SUPPORT
#undef FCH_NO_IMC_SUPPORT
#undef FCH_NO_SD_SUPPORT
#undef FCH_NO_IR_SUPPORT
#undef FCH_NO_AZALIA_SUPPORT
#undef FCH_NO_HWM_SUPPORT
//
// Installable blocks depending on build switches
//
#ifndef FCH_NO_HWACPI_SUPPORT
#define BLOCK_HWACPI_SIZE sizeof (FCH_ACPI)
#define InstallFchInitResetHwAcpiP &FchInitResetHwAcpiP
#define InstallFchInitResetHwAcpi &FchInitResetHwAcpi
#define InstallFchInitEnvHwAcpiP &FchInitEnvHwAcpiP
#define InstallFchInitEnvHwAcpi &FchInitEnvHwAcpi
#define InstallFchInitMidHwAcpi &FchTaskDummy
#define InstallFchInitLateHwAcpi &FchInitLateHwAcpi
#else
#define BLOCK_HWACPI_SIZE 0
#define InstallFchInitResetHwAcpiP &FchTaskDummy
#define InstallFchInitResetHwAcpi &FchTaskDummy
#define InstallFchInitEnvHwAcpi &FchTaskDummy
#define InstallFchInitMidHwAcpi &FchTaskDummy
#define InstallFchInitLateHwAcpi &FchTaskDummy
#endif
#ifndef FCH_NO_AB_SUPPORT
#define BLOCK_AB_SIZE sizeof (FCH_AB)
#define InstallFchInitResetAb &FchInitResetAb
#define InstallFchInitEnvAb &FchInitEnvAb
#define InstallFchInitEnvAbS &FchInitEnvAbSpecial
#define InstallFchInitMidAb &FchInitMidAb
#define InstallFchInitLateAb &FchInitLateAb
#else
#define BLOCK_AB_SIZE 0
#define InstallFchInitResetAb &FchTaskDummy
#define InstallFchInitEnvAb &FchTaskDummy
#define InstallFchInitEnvAbS &FchTaskDummy
#define InstallFchInitMidAb &FchTaskDummy
#define InstallFchInitLateAb &FchTaskDummy
#endif
#ifndef FCH_NO_SPI_SUPPORT
#define BLOCK_SPI_SIZE sizeof (FCH_SPI)
#define InstallFchInitResetSpi &FchInitResetSpi
#define InstallFchInitEnvSpi &FchInitEnvSpi
#define InstallFchInitMidSpi &FchTaskDummy
#define InstallFchInitLateSpi &FchInitLateSpi
#else
#define BLOCK_SPI_SIZE 0
#define InstallFchInitResetSpi &FchTaskDummy
#define InstallFchInitEnvSpi &FchTaskDummy
#define InstallFchInitMidSpi &FchTaskDummy
#define InstallFchInitLateSpi &FchTaskDummy
#endif
#ifndef FCH_NO_GEC_SUPPORT
#define BLOCK_GEC_SIZE sizeof (FCH_GEC)
#define InstallFchInitResetGec &FchInitResetGec
#define InstallFchInitEnvGec &FchInitEnvGec
#define InstallFchInitMidGec &FchInitMidGec
#define InstallFchInitLateGec &FchInitLateGec
#else
#define BLOCK_GEC_SIZE 0
#define InstallFchInitResetGec &FchTaskDummy
#define InstallFchInitEnvGec &FchTaskDummy
#define InstallFchInitMidGec &FchTaskDummy
#define InstallFchInitLateGec &FchTaskDummy
#endif
#ifndef FCH_NO_SATA_SUPPORT
#define BLOCK_SATA_SIZE sizeof (FCH_SATA)
#define InstallFchInitResetSata &FchInitResetSata
#define InstallFchInitEnvSata &FchInitEnvSata
#define InstallFchInitMidSata &FchInitMidSata
#define InstallFchInitLateSata &FchInitLateSata
#else
#define BLOCK_SATA_SIZE 0
#define InstallFchInitResetSata &FchTaskDummy
#define InstallFchInitEnvSata &FchTaskDummy
#define InstallFchInitMidSata &FchTaskDummy
#define InstallFchInitLateSata &FchTaskDummy
#endif
#ifndef FCH_NO_IDE_SUPPORT
#define BLOCK_IDE_SIZE sizeof (FCH_IDE)
#define InstallFchInitResetIde &FchTaskDummy
#define InstallFchInitEnvIde &FchInitEnvIde
#define InstallFchInitMidIde &FchInitMidIde
#define InstallFchInitLateIde &FchInitLateIde
#else
#define BLOCK_IDE_SIZE 0
#define InstallFchInitResetIde &FchTaskDummy
#define InstallFchInitEnvIde &FchTaskDummy
#define InstallFchInitMidIde &FchTaskDummy
#define InstallFchInitLateIde &FchTaskDummy
#endif
#ifndef FCH_NO_LPC_SUPPORT
#define BLOCK_LPC_SIZE sizeof (FCH_LPC)
#define InstallFchInitResetLpc &FchInitResetLpc
#define InstallFchInitEnvLpc &FchTaskDummy
#define InstallFchInitMidLpc &FchTaskDummy
#define InstallFchInitLateLpc &FchTaskDummy
#else
#define BLOCK_LPC_SIZE 0
#define InstallFchInitResetLpc &FchTaskDummy
#define InstallFchInitEnvLpc &FchTaskDummy
#define InstallFchInitMidLpc &FchTaskDummy
#define InstallFchInitLateLpc &FchTaskDummy
#endif
#ifndef FCH_NO_PCIB_SUPPORT
#define BLOCK_PCIB_SIZE sizeof (FCH_PCIB)
#define InstallFchInitResetPcib &FchInitResetPcib
#define InstallFchInitEnvPcib &FchInitEnvPcib
#define InstallFchInitMidPcib &FchTaskDummy
#define InstallFchInitLatePcib &FchInitLatePcib
#else
#define BLOCK_PCIB_SIZE 0
#define InstallFchInitResetPcib &FchTaskDummy
#define InstallFchInitEnvPcib &FchTaskDummy
#define InstallFchInitMidPcib &FchTaskDummy
#define InstallFchInitLatePcib &FchTaskDummy
#endif
#ifndef FCH_NO_PCIE_SUPPORT
#define InstallFchInitResetPcie &FchInitResetPcie
#define InstallFchInitEnvPcie &FchInitEnvPcie
#define InstallFchInitMidPcie &FchTaskDummy
#define InstallFchInitLatePcie &FchInitLatePcie
#else
#define InstallFchInitResetPcie &FchTaskDummy
#define InstallFchInitEnvPcie &FchTaskDummy
#define InstallFchInitMidPcie &FchTaskDummy
#define InstallFchInitLatePcie &FchTaskDummy
#endif
#ifndef FCH_NO_GPP_SUPPORT
#define BLOCK_GPP_SIZE sizeof (FCH_GPP)
#define InstallFchInitResetGpp &FchInitResetGpp
#define InstallFchInitEnvGpp &FchInitEnvGpp
#define InstallFchInitMidGpp &FchTaskDummy
#define InstallFchInitLateGpp &FchInitLateGpp
#define InstallHpSmiCallback &FchGppHotplugSmiCallback
#else
#define BLOCK_GPP_SIZE 0
#define InstallFchInitResetGpp &FchTaskDummy
#define InstallFchInitEnvGpp &FchTaskDummy
#define InstallFchInitMidGpp &FchTaskDummy
#define InstallFchInitLateGpp &FchTaskDummy
#define InstallHpSmiCallback &FchTaskDummy
#endif
#ifndef FCH_NO_USB_SUPPORT
#define BLOCK_USB_SIZE sizeof (FCH_USB)
#define InstallFchInitResetUsb &FchInitResetUsb
#define InstallFchInitEnvUsb &FchInitEnvUsb
#define InstallFchInitMidUsb &FchInitMidUsb
#define InstallFchInitLateUsb &FchInitLateUsb
#else
#define BLOCK_USB_SIZE 0
#define InstallFchInitResetUsb &FchTaskDummy
#define InstallFchInitEnvUsb &FchTaskDummy
#define InstallFchInitMidUsb &FchTaskDummy
#define InstallFchInitLateUsb &FchTaskDummy
#endif
#ifndef FCH_NO_EHCI_SUPPORT
#define InstallFchInitResetUsbEhci &FchInitResetEhci
#define InstallFchInitEnvUsbEhci &FchInitEnvUsbEhci
#define InstallFchInitMidUsbEhci &FchInitMidUsbEhci
#define InstallFchInitLateUsbEhci &FchInitLateUsbEhci
#else
#define InstallFchInitResetUsbEhci &FchTaskDummy
#define InstallFchInitEnvUsbEhci &FchTaskDummy
#define InstallFchInitMidUsbEhci &FchTaskDummy
#define InstallFchInitLateUsbEhci &FchTaskDummy
#endif
#ifndef FCH_NO_OHCI_SUPPORT
#define InstallFchInitResetUsbOhci &FchInitResetOhci
#define InstallFchInitEnvUsbOhci &FchInitEnvUsbOhci
#define InstallFchInitMidUsbOhci &FchInitMidUsbOhci
#define InstallFchInitLateUsbOhci &FchInitLateUsbOhci
#else
#define InstallFchInitResetUsbOhci &FchTaskDummy
#define InstallFchInitEnvUsbOhci &FchTaskDummy
#define InstallFchInitMidUsbOhci &FchTaskDummy
#define InstallFchInitLateUsbOhci &FchTaskDummy
#endif
#ifndef FCH_NO_XHCI_SUPPORT
#define InstallFchInitResetUsbXhci &FchInitResetXhci
#define InstallFchInitEnvUsbXhci &FchInitEnvUsbXhci
#define InstallFchInitMidUsbXhci &FchInitMidUsbXhci
#define InstallFchInitLateUsbXhci &FchInitLateUsbXhci
#else
#define InstallFchInitResetUsbXhci &FchTaskDummy
#define InstallFchInitEnvUsbXhci &FchTaskDummy
#define InstallFchInitMidUsbXhci &FchTaskDummy
#define InstallFchInitLateUsbXhci &FchTaskDummy
#endif
#ifndef FCH_NO_IMC_SUPPORT
#define BLOCK_IMC_SIZE sizeof (FCH_IMC)
#define InstallFchInitResetImc &FchInitResetImc
#define InstallFchInitEnvImc &FchInitEnvImc
#define InstallFchInitMidImc &FchInitMidImc
#define InstallFchInitLateImc &FchInitLateImc
#else
#define BLOCK_IMC_SIZE 0
#define InstallFchInitResetImc &FchTaskDummy
#define InstallFchInitEnvImc &FchTaskDummy
#define InstallFchInitMidImc &FchTaskDummy
#define InstallFchInitLateImc &FchTaskDummy
#endif
#ifndef FCH_NO_SD_SUPPORT
#define BLOCK_SD_SIZE sizeof (FCH_SD)
#define InstallFchInitResetSd &FchTaskDummy
#define InstallFchInitEnvSd &FchInitEnvSd
#define InstallFchInitMidSd &FchTaskDummy
#define InstallFchInitLateSd &FchTaskDummy
#else
#define BLOCK_SD_SIZE 0
#define InstallFchInitResetSd &FchTaskDummy
#define InstallFchInitEnvSd &FchTaskDummy
#define InstallFchInitMidSd &FchTaskDummy
#define InstallFchInitLateSd &FchTaskDummy
#endif
#ifndef FCH_NO_IR_SUPPORT
#define BLOCK_IR_SIZE sizeof (FCH_IR)
#define InstallFchInitResetIr &FchTaskDummy
#define InstallFchInitEnvIr &FchInitEnvIr
#define InstallFchInitMidIr &FchTaskDummy
#define InstallFchInitLateIr &FchTaskDummy
#else
#define BLOCK_IR_SIZE 0
#define InstallFchInitResetIr &FchTaskDummy
#define InstallFchInitEnvIr &FchTaskDummy
#define InstallFchInitMidIr &FchTaskDummy
#define InstallFchInitLateIr &FchTaskDummy
#endif
#ifndef FCH_NO_AZALIA_SUPPORT
#define BLOCK_AZALIA_SIZE sizeof (FCH_AZALIA)
#define InstallFchInitResetAzalia &FchTaskDummy
#define InstallFchInitEnvAzalia &FchInitEnvAzalia
#define InstallFchInitMidAzalia &FchInitMidAzalia
#define InstallFchInitLateAzalia &FchInitLateAzalia
#else
#define BLOCK_AZALIA_SIZE 0
#define InstallFchInitResetAzalia &FchTaskDummy
#define InstallFchInitEnvAzalia &FchTaskDummy
#define InstallFchInitMidAzalia &FchTaskDummy
#define InstallFchInitLateAzalia &FchTaskDummy
#endif
#ifndef FCH_NO_HWM_SUPPORT
#define BLOCK_HWM_SIZE sizeof (FCH_HWM)
#define InstallFchInitResetHwm &FchTaskDummy
#define InstallFchInitEnvHwm &FchInitEnvHwm
#define InstallFchInitMidHwm &FchInitMidHwm
#define InstallFchInitLateHwm &FchInitLateHwm
#else
#define InstallFchInitResetHwm &FchTaskDummy
#define InstallFchInitEnvHwm &FchTaskDummy
#define InstallFchInitMidHwm &FchTaskDummy
#define InstallFchInitLateHwm &FchTaskDummy
#endif
#define BLOCK_SMBUS_SIZE sizeof (FCH_SMBUS)
#define BLOCK_HPET_SIZE sizeof (FCH_HPET)
#define BLOCK_GCPU_SIZE sizeof (FCH_GCPU)
#define BLOCK_SDB_SIZE sizeof (FCH_SERIALDB)
#define BLOCK_MISC_SIZE sizeof (FCH_MISC)
// Optionally declare OEM hooks after each phase
#ifndef FCH_INIT_RESET_HOOK
#define InstallFchInitResetHook FchTaskDummy
#else
#define InstallFchInitResetHook OemFchInitResetHook
#endif
//
// Define FCH build time options and configurations
//
#ifdef BLDCFG_SMBUS0_BASE_ADDRESS
#define CFG_SMBUS0_BASE_ADDRESS BLDCFG_SMBUS0_BASE_ADDRESS
#else
#define CFG_SMBUS0_BASE_ADDRESS DFLT_SMBUS0_BASE_ADDRESS
#endif
#ifdef BLDCFG_SMBUS1_BASE_ADDRESS
#define CFG_SMBUS1_BASE_ADDRESS BLDCFG_SMBUS1_BASE_ADDRESS
#else
#define CFG_SMBUS1_BASE_ADDRESS DFLT_SMBUS1_BASE_ADDRESS
#endif
#ifdef BLDCFG_SIO_PME_BASE_ADDRESS
#define CFG_SIO_PME_BASE_ADDRESS BLDCFG_SIO_PME_BASE_ADDRESS
#else
#define CFG_SIO_PME_BASE_ADDRESS DFLT_SIO_PME_BASE_ADDRESS
#endif
#ifdef BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS
#define CFG_ACPI_PM1_EVT_BLOCK_ADDRESS BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS
#else
#define CFG_ACPI_PM1_EVT_BLOCK_ADDRESS DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS
#endif
#ifdef BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS
#define CFG_ACPI_PM1_CNT_BLOCK_ADDRESS BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS
#else
#define CFG_ACPI_PM1_CNT_BLOCK_ADDRESS DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS
#endif
#ifdef BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS
#define CFG_ACPI_PM_TMR_BLOCK_ADDRESS BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS
#else
#define CFG_ACPI_PM_TMR_BLOCK_ADDRESS DFLT_ACPI_PM_TMR_BLOCK_ADDRESS
#endif
#ifdef BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS
#define CFG_ACPI_CPU_CNT_BLOCK_ADDRESS BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS
#else
#define CFG_ACPI_CPU_CNT_BLOCK_ADDRESS DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS
#endif
#ifdef BLDCFG_ACPI_GPE0_BLOCK_ADDRESS
#define CFG_ACPI_GPE0_BLOCK_ADDRESS BLDCFG_ACPI_GPE0_BLOCK_ADDRESS
#else
#define CFG_ACPI_GPE0_BLOCK_ADDRESS DFLT_ACPI_GPE0_BLOCK_ADDRESS
#endif
#ifdef BLDCFG_WATCHDOG_TIMER_BASE
#define CFG_WATCHDOG_TIMER_BASE BLDCFG_WATCHDOG_TIMER_BASE
#else
#define CFG_WATCHDOG_TIMER_BASE DFLT_WATCHDOG_TIMER_BASE_ADDRESS
#endif
#ifdef BLDCFG_ACPI_PMA_BLK_ADDRESS
#define CFG_ACPI_PMA_CNTBLK_ADDRESS BLDCFG_ACPI_PMA_BLK_ADDRESS
#else
#define CFG_ACPI_PMA_CNTBLK_ADDRESS DFLT_ACPI_PMA_CNT_BLK_ADDRESS
#endif
#ifdef BLDCFG_SMI_CMD_PORT_ADDRESS
#define CFG_SMI_CMD_PORT_ADDRESS BLDCFG_SMI_CMD_PORT_ADDRESS
#else
#define CFG_SMI_CMD_PORT_ADDRESS DFLT_SMI_CMD_PORT
#endif
#ifdef BLDCFG_ROM_BASE_ADDRESS
#define CFG_SPI_ROM_BASE_ADDRESS BLDCFG_ROM_BASE_ADDRESS
#else
#define CFG_SPI_ROM_BASE_ADDRESS DFLT_SPI_BASE_ADDRESS
#endif
#ifdef BLDCFG_GEC_SHADOW_ROM_BASE
#define CFG_GEC_SHADOW_ROM_BASE BLDCFG_GEC_SHADOW_ROM_BASE
#else
#define CFG_GEC_SHADOW_ROM_BASE DFLT_GEC_BASE_ADDRESS
#endif
#ifdef BLDCFG_HPET_BASE_ADDRESS
#define CFG_HPET_BASE_ADDRESS BLDCFG_HPET_BASE_ADDRESS
#else
#define CFG_HPET_BASE_ADDRESS DFLT_HPET_BASE_ADDRESS
#endif
#ifdef BLDCFG_AZALIA_SSID
#define CFG_AZALIA_SSID BLDCFG_AZALIA_SSID
#else
#define CFG_AZALIA_SSID DFLT_AZALIA_SSID
#endif
#ifdef BLDCFG_SMBUS_SSID
#define CFG_SMBUS_SSID BLDCFG_SMBUS_SSID
#else
#define CFG_SMBUS_SSID DFLT_SMBUS_SSID
#endif
#ifdef BLDCFG_IDE_SSID
#define CFG_IDE_SSID BLDCFG_IDE_SSID
#else
#define CFG_IDE_SSID DFLT_IDE_SSID
#endif
#ifdef BLDCFG_SATA_AHCI_SSID
#define CFG_SATA_AHCI_SSID BLDCFG_SATA_AHCI_SSID
#else
#define CFG_SATA_AHCI_SSID DFLT_SATA_AHCI_SSID
#endif
#ifdef BLDCFG_SATA_IDE_SSID
#define CFG_SATA_IDE_SSID BLDCFG_SATA_IDE_SSID
#else
#define CFG_SATA_IDE_SSID DFLT_SATA_IDE_SSID
#endif
#ifdef BLDCFG_SATA_RAID5_SSID
#define CFG_SATA_RAID5_SSID BLDCFG_SATA_RAID5_SSID
#else
#define CFG_SATA_RAID5_SSID DFLT_SATA_RAID5_SSID
#endif
#ifdef BLDCFG_SATA_RAID_SSID
#define CFG_SATA_RAID_SSID BLDCFG_SATA_RAID_SSID
#else
#define CFG_SATA_RAID_SSID DFLT_SATA_RAID_SSID
#endif
#ifdef BLDCFG_EHCI_SSID
#define CFG_EHCI_SSID BLDCFG_EHCI_SSID
#else
#define CFG_EHCI_SSID DFLT_EHCI_SSID
#endif
#ifdef BLDCFG_OHCI_SSID
#define CFG_OHCI_SSID BLDCFG_OHCI_SSID
#else
#define CFG_OHCI_SSID DFLT_OHCI_SSID
#endif
#ifdef BLDCFG_LPC_SSID
#define CFG_LPC_SSID BLDCFG_LPC_SSID
#else
#define CFG_LPC_SSID DFLT_LPC_SSID
#endif
#ifdef BLDCFG_SD_SSID
#define CFG_SD_SSID BLDCFG_SD_SSID
#else
#define CFG_SD_SSID DFLT_SD_SSID
#endif
#ifdef BLDCFG_XHCI_SSID
#define CFG_XHCI_SSID BLDCFG_XHCI_SSID
#else
#define CFG_XHCI_SSID DFLT_XHCI_SSID
#endif
#ifdef BLDCFG_FCH_PORT80_BEHIND_PCIB
#define CFG_FCH_PORT80_BEHIND_PCIB BLDCFG_FCH_PORT80_BEHIND_PCIB
#else
#define CFG_FCH_PORT80_BEHIND_PCIB DFLT_FCH_PORT80_BEHIND_PCIB
#endif
#ifdef BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP
#define CFG_FCH_ENABLE_ACPI_SLEEP_TRAP BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP
#else
#define CFG_FCH_ENABLE_ACPI_SLEEP_TRAP DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP
#endif
#ifdef BLDCFG_FCH_GPP_LINK_CONFIG
#define CFG_FCH_GPP_LINK_CONFIG BLDCFG_FCH_GPP_LINK_CONFIG
#else
#define CFG_FCH_GPP_LINK_CONFIG DFLT_FCH_GPP_LINK_CONFIG
#endif
#ifdef BLDCFG_FCH_GPP_PORT0_PRESENT
#define CFG_FCH_GPP_PORT0_PRESENT BLDCFG_FCH_GPP_PORT0_PRESENT
#else
#define CFG_FCH_GPP_PORT0_PRESENT DFLT_FCH_GPP_PORT0_PRESENT
#endif
#ifdef BLDCFG_FCH_GPP_PORT1_PRESENT
#define CFG_FCH_GPP_PORT1_PRESENT BLDCFG_FCH_GPP_PORT1_PRESENT
#else
#define CFG_FCH_GPP_PORT1_PRESENT DFLT_FCH_GPP_PORT1_PRESENT
#endif
#ifdef BLDCFG_FCH_GPP_PORT2_PRESENT
#define CFG_FCH_GPP_PORT2_PRESENT BLDCFG_FCH_GPP_PORT2_PRESENT
#else
#define CFG_FCH_GPP_PORT2_PRESENT DFLT_FCH_GPP_PORT2_PRESENT
#endif
#ifdef BLDCFG_FCH_GPP_PORT3_PRESENT
#define CFG_FCH_GPP_PORT3_PRESENT BLDCFG_FCH_GPP_PORT3_PRESENT
#else
#define CFG_FCH_GPP_PORT3_PRESENT DFLT_FCH_GPP_PORT3_PRESENT
#endif
#ifdef BLDCFG_FCH_GPP_PORT0_HOTPLUG
#define CFG_FCH_GPP_PORT0_HOTPLUG BLDCFG_FCH_GPP_PORT0_HOTPLUG
#else
#define CFG_FCH_GPP_PORT0_HOTPLUG DFLT_FCH_GPP_PORT0_HOTPLUG
#endif
#ifdef BLDCFG_FCH_GPP_PORT1_HOTPLUG
#define CFG_FCH_GPP_PORT1_HOTPLUG BLDCFG_FCH_GPP_PORT1_HOTPLUG
#else
#define CFG_FCH_GPP_PORT1_HOTPLUG DFLT_FCH_GPP_PORT1_HOTPLUG
#endif
#ifdef BLDCFG_FCH_GPP_PORT2_HOTPLUG
#define CFG_FCH_GPP_PORT2_HOTPLUG BLDCFG_FCH_GPP_PORT2_HOTPLUG
#else
#define CFG_FCH_GPP_PORT2_HOTPLUG DFLT_FCH_GPP_PORT2_HOTPLUG
#endif
#ifdef BLDCFG_FCH_GPP_PORT3_HOTPLUG
#define CFG_FCH_GPP_PORT3_HOTPLUG BLDCFG_FCH_GPP_PORT3_HOTPLUG
#else
#define CFG_FCH_GPP_PORT3_HOTPLUG DFLT_FCH_GPP_PORT3_HOTPLUG
#endif
#ifdef BLDCFG_FCH_ESATA_PORT_BITMAP
#define CFG_FCH_ESATA_PORT_BITMAP BLDCFG_FCH_ESATA_PORT_BITMAP
#else
#define CFG_FCH_ESATA_PORT_BITMAP 0
#endif
#ifdef BLDCFG_FCH_IR_PIN_CONTROL
#define CFG_FCH_IR_PIN_CONTROL BLDCFG_FCH_IR_PIN_CONTROL
#else
#define CFG_FCH_IR_PIN_CONTROL (BIT5 | BIT1 | BIT0)
#endif
#ifdef BLDCFG_FCH_SD_CLOCK_CONTROL
#define CFG_FCH_SD_CLOCK_CONTROL BLDCFG_FCH_SD_CLOCK_CONTROL
#else
#define CFG_FCH_SD_CLOCK_CONTROL Sd50MhzTraceCableLengthWithinSixInches
#endif
#ifdef BLDCFG_FCH_SCI_MAP_LIST
#define CFG_FCH_SCI_MAP_LIST BLDCFG_FCH_SCI_MAP_LIST
#else
#define CFG_FCH_SCI_MAP_LIST NULL
#endif
#ifdef BLDCFG_FCH_SATA_PHY_LIST
#define CFG_FCH_SATA_PHY_LIST BLDCFG_FCH_SATA_PHY_LIST
#else
#define CFG_FCH_SATA_PHY_LIST NULL
#endif
#ifdef BLDCFG_FCH_GPIO_CONTROL_LIST
#define CFG_FCH_GPIO_CONTROL_LIST BLDCFG_FCH_GPIO_CONTROL_LIST
#else
#define CFG_FCH_GPIO_CONTROL_LIST NULL
#endif
#ifdef AGESA_ENTRY_INIT_RESET
#if AGESA_ENTRY_INIT_RESET == TRUE
//
// Define task list for InitReset phase
//
FCH_TASK_ENTRY ROMDATA *FchInitResetTaskTable[] = {
InstallFchInitResetHwAcpiP,
InstallFchInitResetAb,
InstallFchInitResetSpi,
InstallFchInitResetGec,
InstallFchInitResetHwAcpi,
InstallFchInitResetSata,
InstallFchInitResetLpc,
InstallFchInitResetPcib,
InstallFchInitResetPcie,
InstallFchInitResetGpp,
InstallFchInitResetUsb,
InstallFchInitResetUsbEhci,
InstallFchInitResetUsbOhci,
InstallFchInitResetUsbXhci,
InstallFchInitResetImc,
NULL
};
#endif
#endif
#ifdef AGESA_ENTRY_INIT_ENV
#if AGESA_ENTRY_INIT_ENV == TRUE
//
// Define task list for InitEnv phase
//
FCH_TASK_ENTRY ROMDATA *FchInitEnvTaskTable[] = {
InstallFchInitEnvHwAcpiP,
InstallFchInitEnvPcib,
InstallFchInitEnvPcie,
InstallFchInitEnvIr,
InstallFchInitEnvHwAcpi,
InstallFchInitEnvSpi,
InstallFchInitEnvSd,
InstallFchInitEnvImc,
InstallFchInitEnvUsb,
InstallFchInitEnvUsbEhci,
InstallFchInitEnvUsbOhci,
InstallFchInitEnvUsbXhci,
InstallFchInitEnvSata,
InstallFchInitEnvIde,
InstallFchInitEnvGec,
InstallFchInitEnvAzalia,
InstallFchInitEnvAb,
InstallFchInitEnvGpp,
InstallFchInitEnvAbS,
InstallFchInitEnvHwm,
NULL
};
#endif
#endif
#ifdef AGESA_ENTRY_INIT_MID
#if AGESA_ENTRY_INIT_MID == TRUE
//
// Define task list for InitMid phase
//
FCH_TASK_ENTRY ROMDATA *FchInitMidTaskTable[] = {
InstallFchInitMidImc,
InstallFchInitMidUsb,
InstallFchInitMidUsbEhci,
InstallFchInitMidUsbOhci,
InstallFchInitMidUsbXhci,
InstallFchInitMidSata,
InstallFchInitMidIde,
InstallFchInitMidGec,
InstallFchInitMidAzalia,
InstallFchInitMidHwm,
NULL
};
#endif
#endif
#ifdef AGESA_ENTRY_INIT_LATE
#if AGESA_ENTRY_INIT_LATE == TRUE
//
// Define task list for InitLate phase
//
FCH_TASK_ENTRY ROMDATA *FchInitLateTaskTable[] = {
InstallFchInitLatePcie,
InstallFchInitLatePcib,
InstallFchInitLateSpi,
InstallFchInitLateUsb,
InstallFchInitLateUsbEhci,
InstallFchInitLateUsbOhci,
InstallFchInitLateUsbXhci,
InstallFchInitLateSata,
InstallFchInitLateIde,
InstallFchInitLateGec,
InstallFchInitLateAzalia,
InstallFchInitLateImc,
InstallFchInitLateHwm,
InstallFchInitLateGpp,
InstallFchInitLateHwAcpi,
NULL
};
#endif
#endif
#ifdef AGESA_ENTRY_INIT_ENV
#if AGESA_ENTRY_INIT_ENV == TRUE
//
// Define task list for S3 resume before PCI phase
//
FCH_TASK_ENTRY ROMDATA *FchInitS3EarlyTaskTable[] = {
InstallFchInitEnvPcie,
InstallFchInitEnvPcib,
InstallFchInitEnvIr,
InstallFchInitEnvHwAcpi,
InstallFchInitEnvSpi,
InstallFchInitEnvSd,
InstallFchInitEnvUsb,
InstallFchInitEnvSata,
InstallFchInitEnvIde,
InstallFchInitEnvGec,
InstallFchInitEnvAzalia,
InstallFchInitEnvAb,
InstallFchInitEnvGpp,
InstallFchInitEnvAbS,
NULL
};
#endif
#endif
#ifdef AGESA_ENTRY_INIT_LATE
#if AGESA_ENTRY_INIT_LATE == TRUE
//
// Define task list for S3 resume after PCI phase
//
FCH_TASK_ENTRY ROMDATA *FchInitS3LateTaskTable[] = {
InstallFchInitLatePcie,
InstallFchInitLatePcib,
InstallFchInitLateSpi,
InstallFchInitLateUsb,
InstallFchInitLateUsbEhci,
InstallFchInitLateUsbOhci,
InstallFchInitLateUsbXhci,
InstallFchInitMidSata,
InstallFchInitMidIde,
InstallFchInitMidGec,
InstallFchInitMidAzalia,
InstallFchInitLateSata,
InstallFchInitLateIde,
InstallFchInitLateHwAcpi,
InstallFchInitEnvHwm,
InstallFchInitLateHwm,
NULL
};
#endif
#endif
FCH_TASK_ENTRY *FchGppHotplugSmiCallbackPtr = InstallHpSmiCallback;
#else // FCH_SUPPORT == FALSE
/* FCH Interface entries */
extern FCH_INIT CommonFchInitStub;
#define FP_FCH_INIT_RESET &CommonFchInitStub
#define FP_FCH_INIT_RESET_CONSTRUCT &CommonFchInitStub
#define FP_FCH_INIT_ENV &CommonFchInitStub
#define FP_FCH_INIT_ENV_CONSTRUCT &CommonFchInitStub
#define FP_FCH_INIT_MID &CommonFchInitStub
#define FP_FCH_INIT_MID_CONSTRUCT &CommonFchInitStub
#define FP_FCH_INIT_LATE &CommonFchInitStub
#define FP_FCH_INIT_LATE_CONSTRUCT &CommonFchInitStub
#define CFG_SMBUS0_BASE_ADDRESS 0
#define CFG_SMBUS1_BASE_ADDRESS 0
#define CFG_SIO_PME_BASE_ADDRESS 0
#define CFG_ACPI_PM1_EVT_BLOCK_ADDRESS 0
#define CFG_ACPI_PM1_CNT_BLOCK_ADDRESS 0
#define CFG_ACPI_PM_TMR_BLOCK_ADDRESS 0
#define CFG_ACPI_CPU_CNT_BLOCK_ADDRESS 0
#define CFG_ACPI_GPE0_BLOCK_ADDRESS 0
#define CFG_SPI_ROM_BASE_ADDRESS 0
#define CFG_WATCHDOG_TIMER_BASE 0
#define CFG_HPET_BASE_ADDRESS 0
#define CFG_SMI_CMD_PORT_ADDRESS 0
#define CFG_ACPI_PMA_CNTBLK_ADDRESS 0
#define CFG_GEC_SHADOW_ROM_BASE 0
#define CFG_AZALIA_SSID 0
#define CFG_SMBUS_SSID 0
#define CFG_IDE_SSID 0
#define CFG_SATA_AHCI_SSID 0
#define CFG_SATA_IDE_SSID 0
#define CFG_SATA_RAID5_SSID 0
#define CFG_SATA_RAID_SSID 0
#define CFG_EHCI_SSID 0
#define CFG_OHCI_SSID 0
#define CFG_LPC_SSID 0
#define CFG_SD_SSID 0
#define CFG_XHCI_SSID 0
#define CFG_FCH_PORT80_BEHIND_PCIB 0
#define CFG_FCH_ENABLE_ACPI_SLEEP_TRAP 0
#define CFG_FCH_GPP_LINK_CONFIG 0
#define CFG_FCH_GPP_PORT0_PRESENT 0
#define CFG_FCH_GPP_PORT1_PRESENT 0
#define CFG_FCH_GPP_PORT2_PRESENT 0
#define CFG_FCH_GPP_PORT3_PRESENT 0
#define CFG_FCH_GPP_PORT0_HOTPLUG 0
#define CFG_FCH_GPP_PORT1_HOTPLUG 0
#define CFG_FCH_GPP_PORT2_HOTPLUG 0
#define CFG_FCH_GPP_PORT3_HOTPLUG 0
#define CFG_FCH_ESATA_PORT_BITMAP 0
#define CFG_FCH_IR_PIN_CONTROL 0
#define CFG_FCH_SD_CLOCK_CONTROL 0
#define CFG_FCH_SCI_MAP_LIST 0
#define CFG_FCH_SATA_PHY_LIST 0
#define CFG_FCH_GPIO_CONTROL_LIST 0
#endif
CONST BLDOPT_FCH_FUNCTION ROMDATA BldoptFchFunction = {
FP_FCH_INIT_RESET,
FP_FCH_INIT_RESET_CONSTRUCT,
FP_FCH_INIT_ENV,
FP_FCH_INIT_ENV_CONSTRUCT,
FP_FCH_INIT_MID,
FP_FCH_INIT_MID_CONSTRUCT,
FP_FCH_INIT_LATE,
FP_FCH_INIT_LATE_CONSTRUCT,
};
#endif // _OPTION_FCH_INSTALL_H_

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@ -1,52 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: GfxRecovery
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_GFX_RECOVERY_INSTALL_H_
#define _OPTION_GFX_RECOVERY_INSTALL_H_
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#endif // _OPTION_GFX_RECOVERY_INSTALL_H_

591
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@ -1,591 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: GNB
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 53099 $ @e \$Date: 2011-05-16 01:08:27 -0600 (Mon, 16 May 2011) $
*/
/*****************************************************************************
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
***************************************************************************/
#ifndef _OPTION_GNB_INSTALL_H_
#define _OPTION_GNB_INSTALL_H_
#include "S3SaveState.h"
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
//---------------------------------------------------------------------------------------------------
// Family installation
//---------------------------------------------------------------------------------------------------
#define GNB_TYPE_LN FALSE
#define GNB_TYPE_ON FALSE
#if (OPTION_FAMILY14H_ON == TRUE)
#undef GNB_TYPE_ON
#define GNB_TYPE_ON TRUE
#endif
#if (OPTION_FAMILY12H_LN == TRUE)
#undef GNB_TYPE_LN
#define GNB_TYPE_LN TRUE
#endif
#if (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
//---------------------------------------------------------------------------------------------------
// Service installation
//---------------------------------------------------------------------------------------------------
#include "Gnb.h"
#include "GnbPcie.h"
#define SERVICES_POINTER NULL
GNB_SERVICE *ServiceTable = SERVICES_POINTER;
//---------------------------------------------------------------------------------------------------
// BUILD options
//---------------------------------------------------------------------------------------------------
#ifndef CFG_IGFX_AS_PCIE_EP
#define CFG_IGFX_AS_PCIE_EP TRUE
#endif
#ifndef CFG_LCLK_DEEP_SLEEP_EN
#define CFG_LCLK_DEEP_SLEEP_EN TRUE
#endif
#ifndef CFG_LCLK_DPM_EN
#define CFG_LCLK_DPM_EN TRUE
#endif
#ifndef CFG_GMC_POWER_GATE_STUTTER_ONLY
#define CFG_GMC_POWER_GATE_STUTTER_ONLY FALSE
#endif
#ifndef CFG_SMU_SCLK_CLOCK_GATING_ENABLE
#if (GNB_TYPE_ON == TRUE)
#define CFG_SMU_SCLK_CLOCK_GATING_ENABLE TRUE
#else
#define CFG_SMU_SCLK_CLOCK_GATING_ENABLE FALSE
#endif
#endif
#ifndef CFG_PCIE_ASPM_BLACK_LIST_ENABLE
#define CFG_PCIE_ASPM_BLACK_LIST_ENABLE TRUE
#endif
#ifndef CFG_GNB_IVRS_RELATIVE_ADDR_NAMES_SUPPORT
#define CFG_GNB_IVRS_RELATIVE_ADDR_NAMES_SUPPORT FALSE
#endif
#ifndef CFG_GNB_LOAD_REAL_FUSE
#define CFG_GNB_LOAD_REAL_FUSE TRUE
#endif
#ifndef CFG_GNB_PCIE_LINK_RECEIVER_DETECTION_POOLING
#define CFG_GNB_PCIE_LINK_RECEIVER_DETECTION_POOLING (60 * 1000)
#endif
#ifndef CFG_GNB_PCIE_LINK_L0_POOLING
#define CFG_GNB_PCIE_LINK_L0_POOLING (60 * 1000)
#endif
#ifndef CFG_GNB_PCIE_LINK_GPIO_RESET_ASSERT_TIME
#define CFG_GNB_PCIE_LINK_GPIO_RESET_ASSERT_TIME (2 * 1000)
#endif
#ifndef CFG_GNB_PCIE_LINK_RESET_TO_TRAINING_TIME
#define CFG_GNB_PCIE_LINK_RESET_TO_TRAINING_TIME (2 * 1000)
#endif
#ifdef BLDCFG_PCIE_TRAINING_ALGORITHM
#define CFG_GNB_PCIE_TRAINING_ALGORITHM BLDCFG_PCIE_TRAINING_ALGORITHM
#else
#define CFG_GNB_PCIE_TRAINING_ALGORITHM PcieTrainingStandard
#endif
#ifndef CFG_GNB_FORCE_CABLESAFE_OFF
#define CFG_GNB_FORCE_CABLESAFE_OFF FALSE
#endif
#ifndef CFG_ORB_CLOCK_GATING_ENABLE
#define CFG_ORB_CLOCK_GATING_ENABLE TRUE
#endif
#ifndef CFG_GNB_PCIE_POWERGATING_FLAGS
#define CFG_GNB_PCIE_POWERGATING_FLAGS 0x0
#endif
#ifndef CFG_IOC_LCLK_CLOCK_GATING_ENABLE
#define CFG_IOC_LCLK_CLOCK_GATING_ENABLE FALSE
#endif
#ifndef CFG_IOC_SCLK_CLOCK_GATING_ENABLE
#define CFG_IOC_SCLK_CLOCK_GATING_ENABLE FALSE
#endif
#ifndef CFG_IOMMU_L1_CLOCK_GATING_ENABLE
#define CFG_IOMMU_L1_CLOCK_GATING_ENABLE FALSE
#endif
#ifndef CFG_IOMMU_L2_CLOCK_GATING_ENABLE
#define CFG_IOMMU_L2_CLOCK_GATING_ENABLE FALSE
#endif
#ifndef CFG_GNB_ALTVDDNB_SUPPORT
#define CFG_GNB_ALTVDDNB_SUPPORT TRUE
#endif
#ifndef CFG_GNB_BAPM_SUPPORT
#define CFG_GNB_BAPM_SUPPORT TRUE
#endif
#ifndef CFG_UNUSED_SIMD_POWERGATING_ENABLE
#define CFG_UNUSED_SIMD_POWERGATING_ENABLE TRUE
#endif
#ifndef CFG_UNUSED_RB_POWERGATING_ENABLE
#define CFG_UNUSED_RB_POWERGATING_ENABLE FALSE
#endif
GNB_BUILD_OPTIONS ROMDATA GnbBuildOptions = {
CFG_IGFX_AS_PCIE_EP,
CFG_LCLK_DEEP_SLEEP_EN,
CFG_LCLK_DPM_EN,
CFG_GMC_POWER_GATE_STUTTER_ONLY,
CFG_SMU_SCLK_CLOCK_GATING_ENABLE,
CFG_PCIE_ASPM_BLACK_LIST_ENABLE,
CFG_GNB_IVRS_RELATIVE_ADDR_NAMES_SUPPORT,
CFG_GNB_LOAD_REAL_FUSE,
CFG_GNB_PCIE_LINK_RECEIVER_DETECTION_POOLING,
CFG_GNB_PCIE_LINK_L0_POOLING,
CFG_GNB_PCIE_LINK_GPIO_RESET_ASSERT_TIME,
CFG_GNB_PCIE_LINK_RESET_TO_TRAINING_TIME,
CFG_GNB_PCIE_TRAINING_ALGORITHM,
CFG_GNB_FORCE_CABLESAFE_OFF,
CFG_ORB_CLOCK_GATING_ENABLE,
CFG_GNB_PCIE_POWERGATING_FLAGS,
CFG_IOC_LCLK_CLOCK_GATING_ENABLE,
CFG_IOC_SCLK_CLOCK_GATING_ENABLE,
CFG_IOMMU_L1_CLOCK_GATING_ENABLE,
CFG_IOMMU_L2_CLOCK_GATING_ENABLE,
CFG_GNB_ALTVDDNB_SUPPORT,
CFG_GNB_BAPM_SUPPORT,
CFG_UNUSED_SIMD_POWERGATING_ENABLE,
CFG_UNUSED_RB_POWERGATING_ENABLE
};
//---------------------------------------------------------------------------------------------------
// Module entries
//---------------------------------------------------------------------------------------------------
#if (AGESA_ENTRY_INIT_EARLY == TRUE)
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_NB_EARLY_INIT
#define OPTION_NB_EARLY_INIT TRUE
#endif
#if (OPTION_NB_EARLY_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
OPTION_GNB_FEATURE NbInitAtEarly;
#define OPTION_NBINITATEARLY_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, NbInitAtEarly},
#else
#define OPTION_NBINITATEARLY_ENTRY
#endif
//---------------------------------------------------------------------------------------------------
// SMU init
#ifndef OPTION_SMU
#define OPTION_SMU TRUE
#endif
#if (OPTION_SMU == TRUE) && (GNB_TYPE_LN == TRUE)
OPTION_GNB_FEATURE F12NbSmuInitFeature;
#define OPTION_F12NBSMUINITFEATURE_ENTRY {AMD_FAMILY_LN, F12NbSmuInitFeature},
#else
#define OPTION_F12NBSMUINITFEATURE_ENTRY
#endif
#if (OPTION_SMU == TRUE) && (GNB_TYPE_ON == TRUE)
OPTION_GNB_FEATURE F14NbSmuInitFeature;
#define OPTION_F14NBSMUINITFEATURE_ENTRY {AMD_FAMILY_ON, F14NbSmuInitFeature},
#else
#define OPTION_F14NBSMUINITFEATURE_ENTRY
#endif
#define OPTION_KRNBSMUINITFEATURE_ENTRY
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_PCIE_CONFIG_MAP
#define OPTION_PCIE_CONFIG_MAP TRUE
#endif
#if (OPTION_PCIE_CONFIG_MAP == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
OPTION_GNB_FEATURE PcieConfigurationMap;
#define OPTION_PCIECONFIGURATIONMAP_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieConfigurationMap},
#else
#define OPTION_PCIECONFIGURATIONMAP_ENTRY
#endif
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_PCIE_EARLY_INIT
#define OPTION_PCIE_EARLY_INIT TRUE
#endif
#if (OPTION_PCIE_EARLY_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
OPTION_GNB_FEATURE PcieInitAtEarly;
#define OPTION_PCIEINITATEARLY_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieInitAtEarly},
#else
#define OPTION_PCIEINITATEARLY_ENTRY
#endif
//---------------------------------------------------------------------------------------------------
OPTION_GNB_CONFIGURATION GnbEarlyFeatureTable[] = {
OPTION_NBINITATEARLY_ENTRY
OPTION_F12NBSMUINITFEATURE_ENTRY
OPTION_F14NBSMUINITFEATURE_ENTRY
OPTION_PCIECONFIGURATIONMAP_ENTRY
OPTION_PCIEINITATEARLY_ENTRY
{0, NULL}
};
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_PCIE_CONFIG_INIT
#define OPTION_PCIE_CONFIG_INIT TRUE
#endif
#if (OPTION_PCIE_CONFIG_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
OPTION_GNB_FEATURE PcieConfigurationInit;
#define OPTION_PCIECONFIGURATIONINIT_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieConfigurationInit},
#else
#define OPTION_PCIECONFIGURATIONINIT_ENTRY
#endif
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_NB_EARLIER_INIT
#define OPTION_NB_EARLIER_INIT TRUE
#endif
OPTION_GNB_CONFIGURATION GnbEarlierFeatureTable[] = {
OPTION_PCIECONFIGURATIONINIT_ENTRY
{0, NULL}
};
#endif
#if (AGESA_ENTRY_INIT_POST == TRUE)
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_GFX_CONFIG_POST_INIT
#define OPTION_GFX_CONFIG_POST_INIT TRUE
#endif
#if (OPTION_GFX_CONFIG_POST_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
OPTION_GNB_FEATURE GfxConfigPostInterface;
#define OPTION_GFXCONFIGPOSTINTERFACE_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, GfxConfigPostInterface},
#else
#define OPTION_GFXCONFIGPOSTINTERFACE_ENTRY
#endif
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_GFX_POST_INIT
#define OPTION_GFX_POST_INIT TRUE
#endif
#if (OPTION_GFX_POST_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
OPTION_GNB_FEATURE GfxInitAtPost;
#define OPTION_GFXINITATPOST_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, GfxInitAtPost},
#else
#define OPTION_GFXINITATPOST_ENTRY
#endif
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_NB_POST_INIT
#define OPTION_NB_POST_INIT TRUE
#endif
#if (OPTION_NB_POST_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
OPTION_GNB_FEATURE NbInitAtPost;
#define OPTION_NBINITATPOST_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, NbInitAtPost},
#else
#define OPTION_NBINITATPOST_ENTRY
#endif
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_PCIE_POST_EALRY_INIT
#define OPTION_PCIE_POST_EALRY_INIT TRUE
#endif
#if (OPTION_PCIE_POST_EALRY_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
OPTION_GNB_FEATURE PcieInitAtPostEarly;
#define OPTION_PCIEINITATPOSTEARLY_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieInitAtPostEarly},
#else
#define OPTION_PCIEINITATPOSTEARLY_ENTRY
#endif
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_PCIE_POST_INIT
#define OPTION_PCIE_POST_INIT TRUE
#endif
#if (OPTION_PCIE_POST_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
OPTION_GNB_FEATURE PcieInitAtPost;
#define OPTION_PCIEINITATPOST_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieInitAtPost},
#else
#define OPTION_PCIEINITATPOST_ENTRY
#endif
//---------------------------------------------------------------------------------------------------
OPTION_GNB_CONFIGURATION GnbPostFeatureTable[] = {
OPTION_PCIEINITATPOSTEARLY_ENTRY
OPTION_GFXCONFIGPOSTINTERFACE_ENTRY
OPTION_GFXINITATPOST_ENTRY
OPTION_GFXPOSTINTERFACETN_ENTRY
{0, NULL}
};
OPTION_GNB_CONFIGURATION GnbPostAfterDramFeatureTable[] = {
OPTION_NBINITATPOST_ENTRY
OPTION_PCIEINITATPOST_ENTRY
OPTION_PCIEPOSTINTERFACETN_ENTRY
OPTION_PCIEPOSTINTERFACEKM_ENTRY
{0, NULL}
};
#endif
#if (AGESA_ENTRY_INIT_ENV == TRUE)
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_FUSE_TABLE_INIT
#define OPTION_FUSE_TABLE_INIT TRUE
#endif
#if (OPTION_FUSE_TABLE_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
OPTION_GNB_FEATURE NbFuseTableFeature;
#define OPTION_NBFUSETABLEFEATURE_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, NbFuseTableFeature},
#else
#define OPTION_NBFUSETABLEFEATURE_ENTRY
#endif
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_NB_ENV_INIT
#define OPTION_NB_ENV_INIT TRUE
#endif
#if (OPTION_NB_ENV_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
OPTION_GNB_FEATURE NbInitAtEnv;
#define OPTION_NBINITATENVT_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, NbInitAtEnv},
#else
#define OPTION_NBINITATENVT_ENTRY
#endif
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_GFX_CONFIG_ENV_INIT
#define OPTION_GFX_CONFIG_ENV_INIT TRUE
#endif
#if (OPTION_GFX_CONFIG_ENV_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
OPTION_GNB_FEATURE GfxConfigEnvInterface;
#define OPTION_GFXCONFIGENVINTERFACE_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, GfxConfigEnvInterface},
#else
#define OPTION_GFXCONFIGENVINTERFACE_ENTRY
#endif
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_GFX_ENV_INIT
#define OPTION_GFX_ENV_INIT TRUE
#endif
#if (OPTION_GFX_ENV_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
OPTION_GNB_FEATURE GfxInitAtEnvPost;
#define OPTION_GFXINITATENVPOST_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, GfxInitAtEnvPost},
#else
#define OPTION_GFXINITATENVPOST_ENTRY
#endif
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_POWER_GATE
#define OPTION_POWER_GATE TRUE
#endif
#if (OPTION_POWER_GATE == TRUE) && (GNB_TYPE_LN == TRUE)
OPTION_GNB_FEATURE F12NbPowerGateFeature;
#define OPTION_F12NBPOWERGATEFEATURE_ENTRY {AMD_FAMILY_LN, F12NbPowerGateFeature},
#else
#define OPTION_F12NBPOWERGATEFEATURE_ENTRY
#endif
#if (OPTION_POWER_GATE == TRUE) && (GNB_TYPE_ON == TRUE)
OPTION_GNB_FEATURE F14NbPowerGateFeature;
#define OPTION_F14NBPOWERGATEFEATURE_ENTRY {AMD_FAMILY_ON, F14NbPowerGateFeature},
#else
#define OPTION_F14NBPOWERGATEFEATURE_ENTRY
#endif
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_PCIE_ENV_INIT
#define OPTION_PCIE_ENV_INIT TRUE
#endif
#if (OPTION_PCIE_ENV_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
OPTION_GNB_FEATURE PcieInitAtEnv;
#define OPTION_PCIEINITATENV_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieInitAtEnv},
#else
#define OPTION_PCIEINITATENV_ENTRY
#endif
//---------------------------------------------------------------------------------------------------
OPTION_GNB_CONFIGURATION GnbEnvFeatureTable[] = {
OPTION_NBFUSETABLEFEATURE_ENTRY
OPTION_NBINITATENVT_ENTRY
OPTION_PCIEINITATENV_ENTRY
OPTION_GFXCONFIGENVINTERFACE_ENTRY
OPTION_GFXINITATENVPOST_ENTRY
OPTION_F12NBPOWERGATEFEATURE_ENTRY
OPTION_F14NBPOWERGATEFEATURE_ENTRY
OPTION_KRNBPOWERGATEFEATURE_ENTRY
{0, NULL}
};
#endif
#if (AGESA_ENTRY_INIT_MID == TRUE)
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_GNB_CABLESAFE
#define OPTION_GNB_CABLESAFE TRUE
#endif
#if (OPTION_GNB_CABLESAFE == TRUE) && (GNB_TYPE_LN == TRUE)
OPTION_GNB_FEATURE GnbCableSafeEntry;
#define OPTION_GNBCABLESAFEENTRY_ENTRY {AMD_FAMILY_LN, GnbCableSafeEntry},
#else
#define OPTION_GNBCABLESAFEENTRY_ENTRY
#endif
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_NB_LCLK_NCLK_RATIO
#define OPTION_NB_LCLK_NCLK_RATIO TRUE
#endif
#if (OPTION_NB_LCLK_NCLK_RATIO == TRUE) && (GNB_TYPE_ON == TRUE)
OPTION_GNB_FEATURE F14NbLclkNclkRatioFeature;
#define OPTION_F14NBLCLKNCLKRATIOFEATURE_ENTRY {AMD_FAMILY_ON, F14NbLclkNclkRatioFeature},
#else
#define OPTION_F14NBLCLKNCLKRATIOFEATURE_ENTRY
#endif
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_NB_LCLK_DPM_INIT
#define OPTION_NB_LCLK_DPM_INIT TRUE
#endif
#if (OPTION_NB_LCLK_DPM_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
OPTION_GNB_FEATURE NbLclkDpmFeature;
#define OPTION_NBLCLKDPMFEATURE_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, NbLclkDpmFeature},
#else
#define OPTION_NBLCLKDPMFEATURE_ENTRY
#endif
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_PCIE_POWER_GATE
#define OPTION_PCIE_POWER_GATE TRUE
#endif
#if (OPTION_PCIE_POWER_GATE == TRUE) && (GNB_TYPE_LN == TRUE)
OPTION_GNB_FEATURE PciePowerGateFeature;
#define OPTION_PCIEPOWERGATEFEATURE_ENTRY {AMD_FAMILY_LN, PciePowerGateFeature},
#else
#define OPTION_PCIEPOWERGATEFEATURE_ENTRY
#endif
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_GFX_MID_INIT
#define OPTION_GFX_MID_INIT TRUE
#endif
#if (OPTION_GFX_MID_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
OPTION_GNB_FEATURE GfxInitAtMidPost;
#define OPTION_GFXINITATMIDPOST_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, GfxInitAtMidPost},
#else
#define OPTION_GFXINITATMIDPOST_ENTRY
#endif
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_GFX_INTEGRATED_TABLE_INIT
#define OPTION_GFX_INTEGRATED_TABLE_INIT TRUE
#endif
#if (OPTION_GFX_INTEGRATED_TABLE_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
OPTION_GNB_FEATURE GfxIntegratedInfoTableEntry;
#define OPTION_GFXINTEGRATEDINFOTABLE_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, GfxIntegratedInfoTableEntry},
#else
#define OPTION_GFXINTEGRATEDINFOTABLE_ENTRY
#endif
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_PCIe_MID_INIT
#define OPTION_PCIe_MID_INIT TRUE
#endif
#if (OPTION_PCIe_MID_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
OPTION_GNB_FEATURE PcieInitAtMid;
#define OPTION_PCIEINITATMID_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieInitAtMid},
#else
#define OPTION_PCIEINITATMID_ENTRY
#endif
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_NB_MID_INIT
#define OPTION_NB_MID_INIT TRUE
#endif
#if (OPTION_NB_MID_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
OPTION_GNB_FEATURE NbInitAtLatePost;
#define OPTION_NBINITATLATEPOST_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, NbInitAtLatePost},
#else
#define OPTION_NBINITATLATEPOST_ENTRY
#endif
//---------------------------------------------------------------------------------------------------
OPTION_GNB_CONFIGURATION GnbMidFeatureTable[] = {
OPTION_GFXINITATMIDPOST_ENTRY
OPTION_GFXINTEGRATEDINFOTABLE_ENTRY
OPTION_GNBCABLESAFEENTRY_ENTRY
OPTION_PCIEINITATMID_ENTRY
OPTION_NBINITATLATEPOST_ENTRY
OPTION_F14NBLCLKNCLKRATIOFEATURE_ENTRY
OPTION_NBLCLKDPMFEATURE_ENTRY
OPTION_PCIEPOWERGATEFEATURE_ENTRY
{0, NULL}
};
#endif
#if (AGESA_ENTRY_INIT_LATE == TRUE)
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_ALIB
#define OPTION_ALIB FALSE
#endif
#if (OPTION_ALIB == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
OPTION_GNB_FEATURE PcieAlibFeature;
#define OPTION_PCIEALIBFEATURE_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieAlibFeature},
#else
#define OPTION_PCIEALIBFEATURE_ENTRY
#endif
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_IOMMU_ACPI_IVRS
#define OPTION_IOMMU_ACPI_IVRS TRUE
#endif
//---------------------------------------------------------------------------------------------------
OPTION_GNB_CONFIGURATION GnbLateFeatureTable[] = {
OPTION_PCIEALIBFEATURE_ENTRY
OPTIONIOMMUACPIIVRSLATE_ENTRY
{0, NULL}
};
#endif
#if (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
S3_DISPATCH_FUNCTION NbSmuServiceRequestS3Script;
S3_DISPATCH_FUNCTION PcieLateRestoreS3Script;
S3_DISPATCH_FUNCTION NbSmuIndirectWriteS3Script;
#define GNB_S3_DISPATCH_FUNCTION_TABLE \
{NbSmuIndirectWriteS3Script_ID, NbSmuIndirectWriteS3Script}, \
{NbSmuServiceRequestS3Script_ID, NbSmuServiceRequestS3Script}, \
{PcieLateRestoreS3Script_ID, PcieLateRestoreS3Script},
#endif
#endif
#endif // _OPTION_GNB_INSTALL_H_

319
src/vendorcode/amd/agesa/f15/Config/OptionHtInstall.h
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@ -1,319 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: Ht
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 51975 $ @e \$Date: 2011-04-29 01:33:06 -0600 (Fri, 29 Apr 2011) $
*/
/*****************************************************************************
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
***************************************************************************/
#ifndef _OPTION_HT_INSTALL_H_
#define _OPTION_HT_INSTALL_H_
#include "Topology.h"
#include "htFeat.h"
#include "htInterface.h"
#include "htNb.h"
#include "htTopologies.h"
/*
* Advanced Option only, hardware socket naming is the preferred method.
*/
#ifdef BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP
#define CFG_SYSTEM_PHYSICAL_SOCKET_MAP (BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP)
#else
#define CFG_SYSTEM_PHYSICAL_SOCKET_MAP (NULL)
#endif
/*
* OPTION_IS_RECOVERY_HT is true if Basic API is being used.
*/
#ifndef OPTION_IS_RECOVERY_HT
#define OPTION_IS_RECOVERY_HT TRUE
#endif
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition.
*/
#ifndef OPTION_MULTISOCKET
#error BLDOPT: Option not defined: "OPTION_MULTISOCKET"
#endif
/*
* Based on user level options, set Ht internal options.
* For now, Family 10h support will assume single module. For multi module,
* this will have to be changed to not set non-coherent only.
*/
#define OPTION_HT_NON_COHERENT_ONLY FALSE
#if ((OPTION_FAMILY12H == TRUE) || (OPTION_FAMILY14H == TRUE))
/* Families with only PCIe do not need a non-coherent only option. */
#else
// Process Family 10h and 15h Models 00h-0Fh by socket, applying the MultiSocket option where it is allowable.
#if OPTION_G34_SOCKET_SUPPORT == FALSE
// Hydra has coherent support, other Family 10h should follow MultiSocket support.
#if OPTION_MULTISOCKET == FALSE
#undef OPTION_HT_NON_COHERENT_ONLY
#define OPTION_HT_NON_COHERENT_ONLY TRUE
#endif
#endif
#endif
/*
* Macros will generate the correct item reference based on options
*/
#if AGESA_ENTRY_INIT_EARLY == TRUE
// Select the interface and features
#if ((OPTION_FAMILY12H == TRUE) || (OPTION_FAMILY14H == TRUE))
#define INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES NULL
#define INTERNAL_HT_OPTION_FEATURES &HtFeaturesNone
#define INTERNAL_HT_OPTION_INTERFACE &HtInterfaceMapsOnly
#else
// Family 10h and 15h Models 00h-0Fh
#if OPTION_HT_NON_COHERENT_ONLY == FALSE
#define INTERNAL_HT_OPTION_FEATURES &HtFeaturesDefault
#define INTERNAL_HT_OPTION_INTERFACE &HtInterfaceDefault
#else
#define INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES NULL
#define INTERNAL_HT_OPTION_FEATURES &HtFeaturesNonCoherentOnly
#define INTERNAL_HT_OPTION_INTERFACE &HtInterfaceNonCoherentOnly
#endif
#endif
// Select Northbridge components
#if OPTION_FAMILY10H == TRUE
#if OPTION_HT_NON_COHERENT_ONLY == TRUE
#define INTERNAL_HT_OPTION_FAM10_NB &HtFam10NbNonCoherentOnly, &HtFam10RevDNbNonCoherentOnly, &HtFam10RevENbNonCoherentOnly,
#else
#define INTERNAL_HT_OPTION_FAM10_NB &HtFam10NbDefault, &HtFam10RevDNbDefault, &HtFam10RevENbDefault,
#endif
#else
#define INTERNAL_HT_OPTION_FAM10_NB
#endif
#if OPTION_FAMILY12H == TRUE
#define INTERNAL_HT_OPTION_FAM12_NB &HtFam12Nb,
#else
#define INTERNAL_HT_OPTION_FAM12_NB
#endif
#if OPTION_FAMILY14H == TRUE
#define INTERNAL_HT_OPTION_FAM14_NB &HtFam14Nb,
#else
#define INTERNAL_HT_OPTION_FAM14_NB
#endif
#if OPTION_FAMILY15H == TRUE
#if OPTION_FAMILY15H_OR == TRUE
#if OPTION_HT_NON_COHERENT_ONLY == TRUE
#define INTERNAL_HT_OPTION_FAM15_NB &HtFam15NbNonCoherentOnly,
#else
#define INTERNAL_HT_OPTION_FAM15_NB &HtFam15NbDefault,
#endif
#else
#define INTERNAL_HT_OPTION_FAM15_NB
#endif
#define INTERNAL_HT_OPTION_FAM15TN_NB
#define INTERNAL_HT_OPTION_FAM15KM_NB
#else
#define INTERNAL_HT_OPTION_FAM15_NB
#define INTERNAL_HT_OPTION_FAM15TN_NB
#define INTERNAL_HT_OPTION_FAM15KM_NB
#endif
#define INTERNAL_ONLY_NB_LIST_ITEM INTERNAL_ONLY_HT_OPTION_SUPPORTED_NBS,
#ifndef INTERNAL_ONLY_HT_OPTION_SUPPORTED_NBS
#undef INTERNAL_ONLY_NB_LIST_ITEM
#define INTERNAL_ONLY_NB_LIST_ITEM
#endif
/* Install the correct set of northbridge implementations. Each item provides its own comma, the last item
* is ok to have a comma because the final item (NULL) is added below.
*/
#define INTERNAL_HT_OPTION_SUPPORTED_NBS \
INTERNAL_ONLY_NB_LIST_ITEM \
INTERNAL_HT_OPTION_FAM10_NB \
INTERNAL_HT_OPTION_FAM15_NB \
INTERNAL_HT_OPTION_FAM12_NB \
INTERNAL_HT_OPTION_FAM14_NB
#else
// Not Init Early
#define INTERNAL_HT_OPTION_FEATURES NULL
#define INTERNAL_HT_OPTION_INTERFACE NULL
#define INTERNAL_HT_OPTION_SUPPORTED_NBS NULL
#define HT_OPTIONS_PLATFORM NULL
#define INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES NULL
#endif
#ifdef AGESA_ENTRY_INIT_EARLY
#if AGESA_ENTRY_INIT_EARLY == TRUE
extern HT_FEATURES HtFeaturesDefault;
extern HT_FEATURES HtFeaturesNonCoherentOnly;
extern HT_FEATURES HtFeaturesCoherentOnly;
extern HT_FEATURES HtFeaturesNone;
extern HT_INTERFACE HtInterfaceDefault;
extern HT_INTERFACE HtInterfaceNonCoherentOnly;
extern HT_INTERFACE HtInterfaceCoherentOnly;
extern HT_INTERFACE HtInterfaceMapsOnly;
extern HT_INTERFACE HtInterfaceNone;
extern NORTHBRIDGE HtFam10NbDefault;
extern NORTHBRIDGE HtFam10RevDNbDefault;
extern NORTHBRIDGE HtFam10NbNonCoherentOnly;
extern NORTHBRIDGE HtFam10RevDNbNonCoherentOnly;
extern NORTHBRIDGE HtFam10RevENbDefault;
extern NORTHBRIDGE HtFam10RevENbNonCoherentOnly;
extern NORTHBRIDGE HtFam12Nb;
extern NORTHBRIDGE HtFam14Nb;
extern NORTHBRIDGE HtFam10NbNone;
extern NORTHBRIDGE HtFam15NbDefault;
extern NORTHBRIDGE HtFam15NbNonCoherentOnly;
CONST VOID * CONST ROMDATA HtInstalledFamilyNorthbridgeList[] = {
INTERNAL_HT_OPTION_SUPPORTED_NBS
NULL
};
STATIC CONST AMD_HT_INTERFACE ROMDATA HtOptionsPlatform =
{
CFG_STARTING_BUSNUM, CFG_MAXIMUM_BUSNUM, CFG_ALLOCATED_BUSNUM,
(MANUAL_BUID_SWAP_LIST *)CFG_BUID_SWAP_LIST,
(DEVICE_CAP_OVERRIDE *)CFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST,
(CPU_TO_CPU_PCB_LIMITS *)CFG_HTFABRIC_LIMITS_LIST,
(IO_PCB_LIMITS *)CFG_HTCHAIN_LIMITS_LIST,
(OVERRIDE_BUS_NUMBERS *)CFG_BUS_NUMBERS_LIST,
(IGNORE_LINK *)CFG_IGNORE_LINK_LIST,
(SKIP_REGANG *)CFG_LINK_SKIP_REGANG_LIST,
(UINT8 **)CFG_ADDITIONAL_TOPOLOGIES_LIST,
(SYSTEM_PHYSICAL_SOCKET_MAP *)CFG_SYSTEM_PHYSICAL_SOCKET_MAP
};
#ifndef HT_OPTIONS_PLATFORM
#define HT_OPTIONS_PLATFORM &HtOptionsPlatform
#endif
/**
* A list of all the supported topologies.
*
*/
#ifndef INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES
CONST UINT8 *CONST ROMDATA AmdTopolist[] =
{
amdHtTopologySingleNode,
amdHtTopologyDualNode,
amdHtTopologyThreeLine,
amdHtTopologyTriangle,
amdHtTopologyFourLine,
amdHtTopologyFourStar,
amdHtTopologyFourDegenerate,
amdHtTopologyFourSquare,
amdHtTopologyFourKite,
amdHtTopologyFourFully,
amdHtTopologyFiveFully,
amdHtTopologyFiveTwistedLadder,
amdHtTopologySixFully,
amdHtTopologySixDoubloonLower,
amdHtTopologySixDoubloonUpper,
amdHtTopologySixTwistedLadder,
amdHtTopologySevenFully,
amdHtTopologySevenTwistedLadder,
amdHtTopologyEightFully,
amdHtTopologyEightDoubloon,
amdHtTopologyEightTwistedLadder,
amdHtTopologyEightStraightLadder,
amdHtTopologySixTwinTriangles,
amdHtTopologyEightTwinFullyFourWays,
NULL
};
#define INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES AmdTopolist
#endif
/**
* Declare the instance of the Ht option configuration structure
*/
CONST OPTION_HT_CONFIGURATION ROMDATA OptionHtConfiguration = {
OPTION_IS_RECOVERY_HT,
CFG_SET_HTCRC_SYNC_FLOOD,
CFG_USE_UNIT_ID_CLUMPING,
HT_OPTIONS_PLATFORM,
INTERNAL_HT_OPTION_INTERFACE,
INTERNAL_HT_OPTION_FEATURES,
&HtInstalledFamilyNorthbridgeList,
INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES
};
#endif
#endif
#ifndef OPTION_HT_INIIT_RESET_ENTRY
#define OPTION_HT_INIIT_RESET_ENTRY AmdHtInitReset
#define OPTION_HT_INIIT_RESET_CONSTRUCTOR_ENTRY AmdHtResetConstructor
#if ((OPTION_FAMILY12H == TRUE) || (OPTION_FAMILY14H == TRUE))
#undef OPTION_HT_INIIT_RESET_ENTRY
#undef OPTION_HT_INIIT_RESET_CONSTRUCTOR_ENTRY
#define OPTION_HT_INIIT_RESET_ENTRY NULL
#define OPTION_HT_INIIT_RESET_CONSTRUCTOR_ENTRY NULL
#endif
#if ((OPTION_FAMILY10H == TRUE) || (OPTION_FAMILY15H_OR == TRUE))
#undef OPTION_HT_INIIT_RESET_ENTRY
#undef OPTION_HT_INIIT_RESET_CONSTRUCTOR_ENTRY
#define OPTION_HT_INIIT_RESET_ENTRY AmdHtInitReset
#define OPTION_HT_INIIT_RESET_CONSTRUCTOR_ENTRY AmdHtResetConstructor
#endif
#endif
#ifdef AGESA_ENTRY_INIT_RESET
#if AGESA_ENTRY_INIT_RESET == TRUE
CONST AMD_HT_RESET_INTERFACE ROMDATA HtOptionResetDefaults = {
(MANUAL_BUID_SWAP_LIST *)CFG_BUID_SWAP_LIST,
0 // Unused by options
};
CONST OPTION_HT_INIT_RESET ROMDATA HtOptionInitReset = {
OPTION_HT_INIIT_RESET_ENTRY,
OPTION_HT_INIIT_RESET_CONSTRUCTOR_ENTRY
};
#endif
#endif
#endif // _OPTION_HT_INSTALL_H_

79
src/vendorcode/amd/agesa/f15/Config/OptionHwC1eInstall.h
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@ -1,79 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: HW C1e
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_HW_C1E_INSTALL_H_
#define _OPTION_HW_C1E_INSTALL_H_
#include "cpuHwC1e.h"
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#define OPTION_HW_C1E_FEAT
#define F10_HW_C1E_SUPPORT
#if AGESA_ENTRY_INIT_EARLY == TRUE
#ifdef OPTION_FAMILY10H
#if OPTION_FAMILY10H == TRUE
#if (OPTION_FAMILY10H_BL == TRUE) || (OPTION_FAMILY10H_DA == TRUE) || (OPTION_FAMILY10H_RB == TRUE) || (OPTION_FAMILY10H_PH == TRUE)
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureHwC1e;
#undef OPTION_HW_C1E_FEAT
#define OPTION_HW_C1E_FEAT &CpuFeatureHwC1e,
extern CONST HW_C1E_FAMILY_SERVICES ROMDATA F10HwC1e;
#undef F10_HW_C1E_SUPPORT
#define F10_HW_C1E_SUPPORT {(AMD_FAMILY_10_BL | AMD_FAMILY_10_DA | AMD_FAMILY_10_RB | AMD_FAMILY_10_PH), &F10HwC1e},
#endif
#endif
#endif
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA HwC1eFamilyServiceArray[] =
{
F10_HW_C1E_SUPPORT
{0, NULL}
};
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA HwC1eFamilyServiceTable =
{
(sizeof (HwC1eFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
&HwC1eFamilyServiceArray[0]
};
#endif
#endif // _OPTION_HW_C1E_INSTALL_H_

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src/vendorcode/amd/agesa/f15/Config/OptionIdsInstall.h
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@ -1,581 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* IDS Option Install File
*
* This file generates the defaults tables for family 10h model 5 processors.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Core
* @e \$Revision: 55277 $ @e \$Date: 2011-06-19 23:03:21 -0600 (Sun, 19 Jun 2011) $
*/
/*****************************************************************************
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
***************************************************************************/
#ifndef _OPTION_IDS_INSTALL_H_
#define _OPTION_IDS_INSTALL_H_
#include "Ids.h"
#include "IdsHt.h"
#include "IdsLib.h"
#ifdef __IDS_EXTENDED__
#include OPTION_IDS_EXT_INSTALL_FILE
#endif
#define IDS_LATE_RUN_AP_TASK
#define M_HTIDS_PORT_OVERRIDE_HOOK (PF_HtIdsGetPortOverride)CommonVoid
#if (IDSOPT_IDS_ENABLED == TRUE)
#if (IDSOPT_CONTROL_ENABLED == TRUE)
// Check for all families which include HT Features.
#if ((OPTION_FAMILY10H == TRUE) || (OPTION_FAMILY15H_OR == TRUE) || (OPTION_FAMILY15H_KM == TRUE)) && (AGESA_ENTRY_INIT_POST == TRUE)
#undef M_HTIDS_PORT_OVERRIDE_HOOK
#define M_HTIDS_PORT_OVERRIDE_HOOK HtIdsGetPortOverride
#endif
#endif
#endif // OPTION_IDS_LEVEL
CONST PF_HtIdsGetPortOverride ROMDATA pf_HtIdsGetPortOverride = M_HTIDS_PORT_OVERRIDE_HOOK;
#if (IDSOPT_IDS_ENABLED == TRUE)
#if (AGESA_ENTRY_INIT_LATE == TRUE)
#undef IDS_LATE_RUN_AP_TASK
#define IDS_LATE_RUN_AP_TASK
#endif
#endif // OPTION_IDS_LEVEL
#if (IDSOPT_TRACING_ENABLED == TRUE)
#if (AGESA_ENTRY_INIT_POST == TRUE)
#include <mu.h>
CONST SCRIPT_FUNCTION ROMDATA ScriptFuncList[] = {
{ (UINTN) MemUWriteCachelines, "WriteCl(PhyAddrLo,BufferAddr,ClCnt)"},
{ (UINTN) MemUReadCachelines, "ReadCl(BufferAddr,PhyAddrLo,ClCnt)"},
{ (UINTN) MemUFlushPattern, "FlushCl(PhyAddrLo,ClCnt)"}
};
#else
CONST SCRIPT_FUNCTION ROMDATA ScriptFuncList[] = {
{ (UINTN) CommonReturnFalse, "DefRet()"},
{ (UINTN) CommonReturnFalse, "DefRet()"},
{ (UINTN) CommonReturnFalse, "DefRet()"}
};
#endif
#else
CONST SCRIPT_FUNCTION ROMDATA ScriptFuncList[] = {
{ (UINTN) CommonReturnFalse, "DefRet()"},
{ (UINTN) CommonReturnFalse, "DefRet()"},
{ (UINTN) CommonReturnFalse, "DefRet()"}
};
#endif
#define NV_TO_CMOS(Len, NV_ID) {Len, NV_ID},
#define OPTION_IDS_NV_TO_CMOS_END NV_TO_CMOS (IDS_NV_TO_CMOS_LEN_END, IDS_NV_TO_CMOS_ID_END)
#if (IDSOPT_IDS_ENABLED == TRUE)
#if ((IDSOPT_CONTROL_ENABLED == TRUE) && \
((AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_ENV == TRUE) || \
(AGESA_ENTRY_INIT_MID == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || \
(AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE)))
#if (IDSOPT_CONTROL_NV_TO_CMOS == TRUE)
#define OPTION_IDS_NV_TO_CMOS_COMMON
#ifdef OPTION_FAMILY10H
#if OPTION_FAMILY10H == TRUE
#define OPTION_IDS_NV_TO_CMOS_F10
#endif
#endif
#ifdef OPTION_FAMILY12H
#if OPTION_FAMILY12H == TRUE
#define OPTION_IDS_NV_TO_CMOS_F12
#endif
#endif
#ifdef OPTION_FAMILY14H
#if OPTION_FAMILY14H == TRUE
#define OPTION_IDS_NV_TO_CMOS_F14
#endif
#endif
#ifdef OPTION_FAMILY15H_OR
#if OPTION_FAMILY15H_OR == TRUE
#define OPTION_IDS_NV_TO_CMOS_F15_OR
#endif
#endif
#ifdef OPTION_FAMILY15H_TN
#if OPTION_FAMILY15H_TN == TRUE
#define OPTION_IDS_NV_TO_CMOS_F15_TN\
{IDS_NV_TO_CMOS_LEN_BYTE, AGESA_IDS_NV_UCODE},
#endif
#endif
#ifndef OPTION_IDS_NV_TO_CMOS_F10
#define OPTION_IDS_NV_TO_CMOS_F10
#endif
#ifndef OPTION_IDS_NV_TO_CMOS_F12
#define OPTION_IDS_NV_TO_CMOS_F12
#endif
#ifndef OPTION_IDS_NV_TO_CMOS_F14
#define OPTION_IDS_NV_TO_CMOS_F14
#endif
#ifndef OPTION_IDS_NV_TO_CMOS_F15_OR
#define OPTION_IDS_NV_TO_CMOS_F15_OR
#endif
#ifndef OPTION_IDS_NV_TO_CMOS_F15_TN
#define OPTION_IDS_NV_TO_CMOS_F15_TN
#endif
#ifndef OPTION_IDS_NV_TO_CMOS_EXTEND
#define OPTION_IDS_NV_TO_CMOS_EXTEND
#endif
IDS_NV_TO_CMOS gIdsNVToCmos[] = {
OPTION_IDS_NV_TO_CMOS_COMMON
OPTION_IDS_NV_TO_CMOS_F10
OPTION_IDS_NV_TO_CMOS_F12
OPTION_IDS_NV_TO_CMOS_F14
OPTION_IDS_NV_TO_CMOS_F15_OR
OPTION_IDS_NV_TO_CMOS_F15_TN
OPTION_IDS_NV_TO_CMOS_EXTEND
OPTION_IDS_NV_TO_CMOS_END
};
#else
IDS_NV_TO_CMOS gIdsNVToCmos[] = {
OPTION_IDS_NV_TO_CMOS_END
};
#endif
#else
IDS_NV_TO_CMOS gIdsNVToCmos[] = {
OPTION_IDS_NV_TO_CMOS_END
};
#endif
#else
IDS_NV_TO_CMOS gIdsNVToCmos[] = {
OPTION_IDS_NV_TO_CMOS_END
};
#endif
///Ids Feat Options
#if ((IDSOPT_IDS_ENABLED == TRUE) && \
((AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_ENV == TRUE) || \
(AGESA_ENTRY_INIT_MID == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || \
(AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE)))
#if (IDSOPT_CONTROL_ENABLED == TRUE)
#ifndef OPTION_IDS_EXTEND_FEATS
#define OPTION_IDS_EXTEND_FEATS
#endif
#define OPTION_IDS_FEAT_ECCCTRL\
OPTION_IDS_FEAT_ECCCTRL_F10 \
OPTION_IDS_FEAT_ECCCTRL_F12 \
OPTION_IDS_FEAT_ECCCTRL_F15_OR
#define OPTION_IDS_FEAT_GNB_PLATFORMCFG\
OPTION_IDS_FEAT_GNB_PLATFORMCFGF12 \
OPTION_IDS_FEAT_GNB_PLATFORMCFGF14 \
OPTION_IDS_FEAT_GNB_PLATFORMCFGF15TN
#define OPTION_IDS_FEAT_CPB_CTRL\
OPTION_IDS_FEAT_CPB_CTRL_F12
#define OPTION_IDS_FEAT_HTC_CTRL\
OPTION_IDS_FEAT_HTC_CTRL_F15_OR \
OPTION_IDS_FEAT_HTC_CTRL_F15_TN
#define OPTION_IDS_FEAT_MEMORY_MAPPING\
OPTION_IDS_FEAT_MEMORY_MAPPING_F12 \
OPTION_IDS_FEAT_MEMORY_MAPPING_F15_OR \
OPTION_IDS_FEAT_MEMORY_MAPPING_F15_TN
#define OPTION_IDS_FEAT_HT_ASSIST\
OPTION_IDS_FEAT_HT_ASSIST_F10HY \
OPTION_IDS_FEAT_HT_ASSIST_F15_OR
#define OPTION_IDS_FEAT_ECCSYMBOLSIZE\
OPTION_IDS_FEAT_ECCSYMBOLSIZE_F10 \
OPTION_IDS_FEAT_ECCSYMBOLSIZE_F15_OR
/*----------------------------------------------------------------------------
* Family 10 feat blocks
*
*----------------------------------------------------------------------------
*/
#define OPTION_IDS_FEAT_ECCSYMBOLSIZE_F10
#define OPTION_IDS_FEAT_ECCCTRL_F10
#ifdef OPTION_FAMILY10H
#if OPTION_FAMILY10H == TRUE
//Ecc symbol size
extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatEccSymbolSizeBlockF10;
#undef OPTION_IDS_FEAT_ECCSYMBOLSIZE_F10
#define OPTION_IDS_FEAT_ECCSYMBOLSIZE_F10 &IdsFeatEccSymbolSizeBlockF10,
//ECC scrub control
extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatEccCtrlBlockF10;
#undef OPTION_IDS_FEAT_ECCCTRL_F10
#define OPTION_IDS_FEAT_ECCCTRL_F10 &IdsFeatEccCtrlBlockF10,
#endif
#endif
//Misc Features
#define OPTION_IDS_FEAT_HT_ASSIST_F10HY
#ifdef OPTION_FAMILY10H_HY
#if OPTION_FAMILY10H_HY == TRUE
#undef OPTION_IDS_FEAT_HT_ASSIST_F10HY
extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatHtAssistBlockPlatformCfgF10Hy;
#define OPTION_IDS_FEAT_HT_ASSIST_F10HY \
&IdsFeatHtAssistBlockPlatformCfgF10Hy,
#endif
#endif
/*----------------------------------------------------------------------------
* Family 12 feat blocks
*
*----------------------------------------------------------------------------
*/
#define OPTION_IDS_FEAT_GNB_PLATFORMCFGF12
#define OPTION_IDS_FEAT_ECCCTRL_F12
#define OPTION_IDS_FEAT_CPB_CTRL_F12
#define OPTION_IDS_FEAT_MEMORY_MAPPING_F12
#ifdef OPTION_FAMILY12H
#if OPTION_FAMILY12H == TRUE
extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatGnbPlatformCfgBlockF12;
#undef OPTION_IDS_FEAT_GNB_PLATFORMCFGF12
#define OPTION_IDS_FEAT_GNB_PLATFORMCFGF12 &IdsFeatGnbPlatformCfgBlockF12,
//ECC scrub control
extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatEccCtrlBlockF12;
#undef OPTION_IDS_FEAT_ECCCTRL_F12
#define OPTION_IDS_FEAT_ECCCTRL_F12 &IdsFeatEccCtrlBlockF12,
#undef OPTION_IDS_FEAT_CPB_CTRL_F12
extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatCpbCtrlBlockF12;
#define OPTION_IDS_FEAT_CPB_CTRL_F12 &IdsFeatCpbCtrlBlockF12,
extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatMemoryChIntlvPostBeforeBlockF12;
extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatMemoryMappingChIntlvBlockF12;
#undef OPTION_IDS_FEAT_MEMORY_MAPPING_F12
#define OPTION_IDS_FEAT_MEMORY_MAPPING_F12 \
&IdsFeatMemoryChIntlvPostBeforeBlockF12, \
&IdsFeatMemoryMappingChIntlvBlockF12,
#endif
#endif
/*----------------------------------------------------------------------------
* Family 14 feat blocks
*
*----------------------------------------------------------------------------
*/
#define OPTION_IDS_FEAT_GNB_PLATFORMCFGF14
#ifdef OPTION_FAMILY14H
#if OPTION_FAMILY14H == TRUE
extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatGnbPlatformCfgBlockF14;
#undef OPTION_IDS_FEAT_GNB_PLATFORMCFGF14
#define OPTION_IDS_FEAT_GNB_PLATFORMCFGF14 &IdsFeatGnbPlatformCfgBlockF14,
#endif
#endif
/*----------------------------------------------------------------------------
* Family 15 OR feat blocks
*
*----------------------------------------------------------------------------
*/
#define OPTION_IDS_FEAT_HTC_CTRL_F15_OR
#define OPTION_IDS_FEAT_MEMORY_MAPPING_F15_OR
#define OPTION_IDS_FEAT_HT_ASSIST_F15_OR
#define OPTION_IDS_FEAT_ECCCTRL_F15_OR
#define OPTION_IDS_FEAT_ECCSYMBOLSIZE_F15_OR
#ifdef OPTION_FAMILY15H_OR
#if OPTION_FAMILY15H_OR == TRUE
extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatHtcControlBlockF15Or;
extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatHtcControlLateBlockF15Or;
#undef OPTION_IDS_FEAT_HTC_CTRL_F15_OR
#define OPTION_IDS_FEAT_HTC_CTRL_F15_OR\
&IdsFeatHtcControlBlockF15Or,\
&IdsFeatHtcControlLateBlockF15Or,
extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatMemoryMappingPostBeforeBlockF15Or;
extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatMemoryMappingChIntlvBlockF15Or;
#undef OPTION_IDS_FEAT_MEMORY_MAPPING_F15_OR
#define OPTION_IDS_FEAT_MEMORY_MAPPING_F15_OR\
&IdsFeatMemoryMappingPostBeforeBlockF15Or,\
&IdsFeatMemoryMappingChIntlvBlockF15Or,
extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatHtAssistBlockPlatformCfgF15Or;
#undef OPTION_IDS_FEAT_HT_ASSIST_F15_OR
#define OPTION_IDS_FEAT_HT_ASSIST_F15_OR\
&IdsFeatHtAssistBlockPlatformCfgF15Or,
extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatEccCtrlBlockF15Or;
#undef OPTION_IDS_FEAT_ECCCTRL_F15_OR
#define OPTION_IDS_FEAT_ECCCTRL_F15_OR &IdsFeatEccCtrlBlockF15Or,
extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatEccSymbolSizeBlockF15Or;
#undef OPTION_IDS_FEAT_ECCSYMBOLSIZE_F15_OR
#define OPTION_IDS_FEAT_ECCSYMBOLSIZE_F15_OR &IdsFeatEccSymbolSizeBlockF15Or,
#endif
#endif
/*----------------------------------------------------------------------------
* Family 15 TN feat blocks
*
*----------------------------------------------------------------------------
*/
#define OPTION_IDS_FEAT_HTC_CTRL_F15_TN
#define OPTION_IDS_FEAT_MEMORY_MAPPING_F15_TN
#define OPTION_IDS_FEAT_GNB_PLATFORMCFGF15TN
#ifdef OPTION_FAMILY15H_TN
#if OPTION_FAMILY15H_TN == TRUE
extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatHtcControlBlockF15Tn;
#undef OPTION_IDS_FEAT_HTC_CTRL_F15_TN
#define OPTION_IDS_FEAT_HTC_CTRL_F15_TN\
&IdsFeatHtcControlBlockF15Tn,
extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatMemoryMappingPostBeforeBlockF15Tn;
extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatMemoryMappingChIntlvBlockF15Tn;
#undef OPTION_IDS_FEAT_MEMORY_MAPPING_F15_TN
#define OPTION_IDS_FEAT_MEMORY_MAPPING_F15_TN\
&IdsFeatMemoryMappingPostBeforeBlockF15Tn,\
&IdsFeatMemoryMappingChIntlvBlockF15Tn,
extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatGnbPlatformCfgBlockF15Tn;
#undef OPTION_IDS_FEAT_GNB_PLATFORMCFGF15TN
#define OPTION_IDS_FEAT_GNB_PLATFORMCFGF15TN &IdsFeatGnbPlatformCfgBlockF15Tn,
#endif
#endif
#define OPTION_IDS_FEAT_NV_TO_CMOS
#if IDSOPT_CONTROL_NV_TO_CMOS == TRUE
#undef OPTION_IDS_FEAT_NV_TO_CMOS
extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatNvToCmosSaveBlock;
extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatNvToCmosRestoreBlock;
#define OPTION_IDS_FEAT_NV_TO_CMOS\
&IdsFeatNvToCmosSaveBlock, \
&IdsFeatNvToCmosRestoreBlock,
#endif
CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatUcodeBlock =
{
IDS_FEAT_UCODE_UPDATE,
IDS_ALL_CORES,
IDS_UCODE,
IDS_FAMILY_ALL,
IdsSubUCode
};
CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatPowerPolicyBlock =
{
IDS_FEAT_POWER_POLICY,
IDS_ALL_CORES,
IDS_PLATFORMCFG_OVERRIDE,
IDS_FAMILY_ALL,
IdsSubPowerPolicyOverride
};
CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatTargetPstateBlock =
{
IDS_FEAT_TARGET_PSTATE,
IDS_BSP_ONLY,
IDS_INIT_LATE_AFTER,
IDS_FAMILY_ALL,
IdsSubTargetPstate
};
CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatPostPstateBlock =
{
IDS_FEAT_POSTPSTATE,
IDS_ALL_CORES,
IDS_CPU_Early_Override,
IDS_FAMILY_ALL,
IdsSubPostPState
};
//Dram controller Features
CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatDctAllMemClkBlock =
{
IDS_FEAT_DCT_ALLMEMCLK,
IDS_BSP_ONLY,
IDS_ALL_MEMORY_CLOCK,
IDS_FAMILY_ALL,
IdsSubAllMemClkEn
};
CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatDctGangModeBlock =
{
IDS_FEAT_DCT_GANGMODE,
IDS_BSP_ONLY,
IDS_GANGING_MODE,
IDS_FAMILY_ALL,
IdsSubGangingMode
};
CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatDctBurstLengthBlock =
{
IDS_FEAT_DCT_BURSTLENGTH,
IDS_BSP_ONLY,
IDS_BURST_LENGTH32,
AMD_FAMILY_10,
IdsSubBurstLength32
};
CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatDctPowerDownCtrlBlock =
{
IDS_FEAT_DCT_POWERDOWN,
IDS_BSP_ONLY,
IDS_INIT_POST_BEFORE,
IDS_FAMILY_ALL,
IdsSubPowerDownCtrl
};
CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatDctDllShutDownBlock =
{
IDS_FEAT_DCT_DLLSHUTDOWN,
IDS_BSP_ONLY,
IDS_DLL_SHUT_DOWN,
IDS_FAMILY_ALL,
IdsSubDllShutDownSR
};
CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatDctPowerDownModeBlock =
{
IDS_FEAT_DCT_POWERDOWN,
IDS_BSP_ONLY,
IDS_POWERDOWN_MODE,
IDS_FAMILY_ALL,
IdsSubPowerDownMode
};
CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatHdtOutBlock =
{
IDS_FEAT_HDTOUT,
IDS_BSP_ONLY,
IDS_INIT_EARLY_BEFORE,
IDS_FAMILY_ALL,
IdsSubHdtOut
};
CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatHtSettingBlock =
{
IDS_FEAT_HT_SETTING,
IDS_BSP_ONLY,
IDS_HT_CONTROL,
IDS_FAMILY_ALL,
IdsSubHtLinkControl
};
CONST IDS_FAMILY_FEAT_STRUCT* ROMDATA IdsContorlFeats[] =
{
&IdsFeatUcodeBlock,
&IdsFeatPowerPolicyBlock,
&IdsFeatTargetPstateBlock,
&IdsFeatPostPstateBlock,
OPTION_IDS_FEAT_NV_TO_CMOS
OPTION_IDS_FEAT_ECCSYMBOLSIZE
OPTION_IDS_FEAT_ECCCTRL
&IdsFeatDctAllMemClkBlock,
&IdsFeatDctGangModeBlock,
&IdsFeatDctBurstLengthBlock,
&IdsFeatDctPowerDownCtrlBlock,
&IdsFeatDctPowerDownModeBlock,
&IdsFeatDctPowerDownModeBlock,
OPTION_IDS_FEAT_HT_ASSIST
&IdsFeatHdtOutBlock,
&IdsFeatHtSettingBlock,
OPTION_IDS_FEAT_GNB_PLATFORMCFG
OPTION_IDS_FEAT_CPB_CTRL
OPTION_IDS_FEAT_HTC_CTRL
OPTION_IDS_FEAT_MEMORY_MAPPING
OPTION_IDS_EXTEND_FEATS
NULL
};
#else
CONST IDS_FAMILY_FEAT_STRUCT* ROMDATA IdsContorlFeats[] =
{
NULL
};
#endif//IDSOPT_CONTROL_ENABLED
#define OPTION_IDS_FAM_REGACC\
OPTION_IDS_FAM_REGACC_F15TN
#define OPTION_IDS_FAM_REGACC_F15TN
#ifdef OPTION_FAMILY15H_TN
#if OPTION_FAMILY15H_TN == TRUE
extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatRegGmmxF15Tn;
#undef OPTION_IDS_FAM_REGACC_F15TN
#define OPTION_IDS_FAM_REGACC_F15TN \
&IdsFeatRegGmmxF15Tn,
#endif
#endif
CONST IDS_FAMILY_FEAT_STRUCT* ROMDATA IdsRegAccessTbl[] =
{
OPTION_IDS_FAM_REGACC
NULL
};
#else
CONST IDS_FAMILY_FEAT_STRUCT* ROMDATA IdsContorlFeats[] =
{
NULL
};
CONST IDS_FAMILY_FEAT_STRUCT* ROMDATA IdsRegAccessTbl[] =
{
NULL
};
#endif// IDSOPT_IDS_ENABLED
#endif

133
src/vendorcode/amd/agesa/f15/Config/OptionIoCstateInstall.h
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@ -1,133 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: IO C-state
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $
*/
/*****************************************************************************
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
***************************************************************************/
#ifndef _OPTION_IO_CSTATE_INSTALL_H_
#define _OPTION_IO_CSTATE_INSTALL_H_
#include "cpuIoCstate.h"
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#define OPTION_IO_CSTATE_FEAT
#define F10_IO_CSTATE_SUPPORT
#define F12_IO_CSTATE_SUPPORT
#define F14_IO_CSTATE_SUPPORT
#define F15_OR_IO_CSTATE_SUPPORT
#if OPTION_IO_CSTATE == TRUE
#if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE)
#ifdef OPTION_FAMILY10H
#if OPTION_FAMILY10H == TRUE
#if OPTION_FAMILY10H_PH == TRUE
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureIoCstate;
#undef OPTION_IO_CSTATE_FEAT
#define OPTION_IO_CSTATE_FEAT &CpuFeatureIoCstate,
extern CONST IO_CSTATE_FAMILY_SERVICES ROMDATA F10IoCstateSupport;
#undef F10_IO_CSTATE_SUPPORT
#define F10_IO_CSTATE_SUPPORT {AMD_FAMILY_10_PH, &F10IoCstateSupport},
#endif
#endif
#endif
#ifdef OPTION_FAMILY12H
#if OPTION_FAMILY12H == TRUE
#if OPTION_FAMILY12H_LN == TRUE
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureIoCstate;
#undef OPTION_IO_CSTATE_FEAT
#define OPTION_IO_CSTATE_FEAT &CpuFeatureIoCstate,
extern CONST IO_CSTATE_FAMILY_SERVICES ROMDATA F12IoCstateSupport;
#undef F12_IO_CSTATE_SUPPORT
#define F12_IO_CSTATE_SUPPORT {AMD_FAMILY_12_LN, &F12IoCstateSupport},
#endif
#endif
#endif
#ifdef OPTION_FAMILY14H
#if OPTION_FAMILY14H == TRUE
#if (OPTION_FAMILY14H_ON == TRUE)
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureIoCstate;
#undef OPTION_IO_CSTATE_FEAT
#define OPTION_IO_CSTATE_FEAT &CpuFeatureIoCstate,
extern CONST IO_CSTATE_FAMILY_SERVICES ROMDATA F14IoCstateSupport;
#undef F14_IO_CSTATE_SUPPORT
#define F14_IO_CSTATE_SUPPORT {AMD_FAMILY_14, &F14IoCstateSupport},
#endif
#endif
#endif
#ifdef OPTION_FAMILY15H
#if OPTION_FAMILY15H == TRUE
#if OPTION_FAMILY15H_OR == TRUE
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureIoCstate;
#undef OPTION_IO_CSTATE_FEAT
#define OPTION_IO_CSTATE_FEAT &CpuFeatureIoCstate,
extern CONST IO_CSTATE_FAMILY_SERVICES ROMDATA F15OrIoCstateSupport;
#undef F15_OR_IO_CSTATE_SUPPORT
#define F15_OR_IO_CSTATE_SUPPORT {AMD_FAMILY_15_OR, &F15OrIoCstateSupport},
#endif
#endif
#endif
#endif
#endif
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA IoCstateFamilyServiceArray[] =
{
F10_IO_CSTATE_SUPPORT
F12_IO_CSTATE_SUPPORT
F14_IO_CSTATE_SUPPORT
F15_OR_IO_CSTATE_SUPPORT
{0, NULL}
};
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA IoCstateFamilyServiceTable =
{
(sizeof (IoCstateFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
&IoCstateFamilyServiceArray[0]
};
#endif // _OPTION_IO_CSTATE_INSTALL_H_

117
src/vendorcode/amd/agesa/f15/Config/OptionL3FeaturesInstall.h
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@ -1,117 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: L3 Dependent Features
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 56186 $ @e \$Date: 2011-07-08 15:35:23 -0600 (Fri, 08 Jul 2011) $
*/
/*****************************************************************************
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
***************************************************************************/
#ifndef _OPTION_L3_FEATURES_INSTALL_H_
#define _OPTION_L3_FEATURES_INSTALL_H_
#include "cpuL3Features.h"
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#define OPTION_L3_FEAT
#define F10_L3_FEAT_SUPPORT
#define F15_OR_L3_FEAT_SUPPORT
#define F15_KM_L3_FEAT_SUPPORT
#define L3_FEAT_AP_DISABLE_CACHE
#define L3_FEAT_AP_ENABLE_CACHE
#if (OPTION_HT_ASSIST == TRUE || OPTION_ATM_MODE == TRUE)
#if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_MID == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE)
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuL3Features;
#ifdef OPTION_FAMILY10H
#if OPTION_FAMILY10H == TRUE
#if OPTION_FAMILY10H_HY == TRUE
#undef OPTION_L3_FEAT
#define OPTION_L3_FEAT &CpuL3Features,
extern CONST L3_FEATURE_FAMILY_SERVICES ROMDATA F10L3Features;
#undef F10_L3_FEAT_SUPPORT
#define F10_L3_FEAT_SUPPORT {AMD_FAMILY_10_HY, &F10L3Features},
#endif
#endif
#endif
#ifdef OPTION_FAMILY15H_OR
#if OPTION_FAMILY15H_OR == TRUE
#undef OPTION_L3_FEAT
#define OPTION_L3_FEAT &CpuL3Features,
extern CONST L3_FEATURE_FAMILY_SERVICES ROMDATA F15OrL3Features;
#undef F15_OR_L3_FEAT_SUPPORT
#define F15_OR_L3_FEAT_SUPPORT {AMD_FAMILY_15_OR, &F15OrL3Features},
#endif
#endif
#ifdef OPTION_FAMILY15H_KM
#if OPTION_FAMILY15H_KM == TRUE
#undef OPTION_L3_FEAT
#define OPTION_L3_FEAT &CpuL3Features,
extern CONST L3_FEATURE_FAMILY_SERVICES ROMDATA F15KmL3Features;
#undef F15_KM_L3_FEAT_SUPPORT
#define F15_KM_L3_FEAT_SUPPORT {AMD_FAMILY_15_KM, &F15KmL3Features},
#endif
#endif
#undef L3_FEAT_AP_DISABLE_CACHE
#define L3_FEAT_AP_DISABLE_CACHE {AP_LATE_TASK_DISABLE_CACHE, (IMAGE_ENTRY) DisableAllCaches},
#undef L3_FEAT_AP_ENABLE_CACHE
#define L3_FEAT_AP_ENABLE_CACHE {AP_LATE_TASK_ENABLE_CACHE, (IMAGE_ENTRY) EnableAllCaches},
#endif
#endif
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA L3FeatureFamilyServiceArray[] =
{
F10_L3_FEAT_SUPPORT
F15_OR_L3_FEAT_SUPPORT
F15_KM_L3_FEAT_SUPPORT
{0, NULL}
};
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA L3FeatureFamilyServiceTable =
{
(sizeof (L3FeatureFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
&L3FeatureFamilyServiceArray[0]
};
#endif // _OPTION_L3_FEATURES_INSTALL_H_

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/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: Low Power Pstate for PROCHOT_L Throttling.
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_LOW_PWR_PSTATE_INSTALL_H_
#define _OPTION_LOW_PWR_PSTATE_INSTALL_H_
#include "cpuLowPwrPstate.h"
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT_FEAT
#define F15_OR_LOW_PWR_PSTATE_SUPPORT
#if OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT == TRUE
#if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE)
// Family 15h
#ifdef OPTION_FAMILY15H
#if OPTION_FAMILY15H == TRUE
#if OPTION_FAMILY15H_OR == TRUE
#if (OPTION_G34_SOCKET_SUPPORT == TRUE) || (OPTION_C32_SOCKET_SUPPORT == TRUE)
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureLowPwrPstate;
#undef OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT_FEAT
#define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT_FEAT &CpuFeatureLowPwrPstate,
extern CONST LOW_PWR_PSTATE_FAMILY_SERVICES ROMDATA F15OrLowPwrPstateSupport;
#undef F15_OR_LOW_PWR_PSTATE_SUPPORT
#define F15_OR_LOW_PWR_PSTATE_SUPPORT {AMD_FAMILY_15_OR, &F15OrLowPwrPstateSupport},
#endif
#endif
#endif
#endif
#endif
#endif
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA LowPwrPstateFamilyServiceArray[] =
{
F15_OR_LOW_PWR_PSTATE_SUPPORT
{0, NULL}
};
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA LowPwrPstateFamilyServiceTable =
{
(sizeof (LowPwrPstateFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
&LowPwrPstateFamilyServiceArray[0]
};
#endif // _OPTION_LOW_PWR_PSTATE_INSTALL_H_

3778
src/vendorcode/amd/agesa/f15/Config/OptionMemoryInstall.h
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116
src/vendorcode/amd/agesa/f15/Config/OptionMsgBasedC1eInstall.h
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/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: Message-Based C1e
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 56186 $ @e \$Date: 2011-07-08 15:35:23 -0600 (Fri, 08 Jul 2011) $
*/
/*****************************************************************************
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
***************************************************************************/
#ifndef _OPTION_MSG_BASED_C1E_INSTALL_H_
#define _OPTION_MSG_BASED_C1E_INSTALL_H_
#include "cpuMsgBasedC1e.h"
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#define OPTION_MSG_BASED_C1E_FEAT
#define F10_MSG_BASED_C1E_SUPPORT
#define F15_OR_MSG_BASED_C1E_SUPPORT
#if OPTION_MSG_BASED_C1E == TRUE
#if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE)
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureMsgBasedC1e;
#ifdef OPTION_FAMILY10H
#if OPTION_FAMILY10H == TRUE
#if OPTION_FAMILY10H_HY == TRUE
#if (OPTION_G34_SOCKET_SUPPORT == TRUE) || (OPTION_C32_SOCKET_SUPPORT == TRUE)
#undef OPTION_MSG_BASED_C1E_FEAT
#define OPTION_MSG_BASED_C1E_FEAT &CpuFeatureMsgBasedC1e,
#endif
#endif
#endif
#endif
#ifdef OPTION_FAMILY15H_OR
#if OPTION_FAMILY15H_OR == TRUE
#if (OPTION_G34_SOCKET_SUPPORT == TRUE) || (OPTION_C32_SOCKET_SUPPORT == TRUE || OPTION_AM3_SOCKET_SUPPORT == TRUE)
#undef OPTION_MSG_BASED_C1E_FEAT
#define OPTION_MSG_BASED_C1E_FEAT &CpuFeatureMsgBasedC1e,
#endif
#endif
#endif
#ifdef OPTION_FAMILY10H
#if OPTION_FAMILY10H == TRUE
#if OPTION_FAMILY10H_HY == TRUE
#if (OPTION_G34_SOCKET_SUPPORT == TRUE) || (OPTION_C32_SOCKET_SUPPORT == TRUE)
extern CONST MSG_BASED_C1E_FAMILY_SERVICES ROMDATA F10MsgBasedC1e;
#undef F10_MSG_BASED_C1E_SUPPORT
#define F10_MSG_BASED_C1E_SUPPORT {AMD_FAMILY_10_HY, &F10MsgBasedC1e},
#endif
#endif
#endif
#endif
#ifdef OPTION_FAMILY15H_OR
#if OPTION_FAMILY15H_OR == TRUE
#if (OPTION_G34_SOCKET_SUPPORT == TRUE) || (OPTION_C32_SOCKET_SUPPORT == TRUE || OPTION_AM3_SOCKET_SUPPORT == TRUE)
extern CONST MSG_BASED_C1E_FAMILY_SERVICES ROMDATA F15OrMsgBasedC1e;
#undef F15_OR_MSG_BASED_C1E_SUPPORT
#define F15_OR_MSG_BASED_C1E_SUPPORT {AMD_FAMILY_15_OR, &F15OrMsgBasedC1e},
#endif
#endif
#endif
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA MsgBasedC1eFamilyServiceArray[] =
{
F10_MSG_BASED_C1E_SUPPORT
F15_OR_MSG_BASED_C1E_SUPPORT
{0, NULL}
};
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA MsgBasedC1eFamilyServiceTable =
{
(sizeof (MsgBasedC1eFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
&MsgBasedC1eFamilyServiceArray[0]
};
#endif
#endif
#endif // _OPTION_MSG_BASED_C1E_INSTALL_H_

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src/vendorcode/amd/agesa/f15/Config/OptionMultiSocketInstall.h
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/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: Multiple Socket Support
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_MULTISOCKET_INSTALL_H_
#define _OPTION_MULTISOCKET_INSTALL_H_
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#ifndef OPTION_MULTISOCKET
#error BLDOPT: Option not defined: "OPTION_MULTISOCKET"
#endif
#if OPTION_MULTISOCKET == TRUE
OPTION_MULTISOCKET_PM_STEPS GetNumberOfSystemPmStepsPtrMulti;
#define GET_NUM_PM_STEPS GetNumberOfSystemPmStepsPtrMulti
OPTION_MULTISOCKET_PM_CORE0_TASK RunCodeOnAllSystemCore0sMulti;
#define CORE0_PM_TASK RunCodeOnAllSystemCore0sMulti
OPTION_MULTISOCKET_PM_NB_COF GetSystemNbCofMulti;
#define GET_SYS_NB_COF GetSystemNbCofMulti
OPTION_MULTISOCKET_PM_NB_COF_UPDATE GetSystemNbCofVidUpdateMulti;
#define GET_SYS_NB_COF_UPDATE GetSystemNbCofVidUpdateMulti
OPTION_MULTISOCKET_PM_GET_EVENTS GetEarlyPmErrorsMulti;
#define GET_EARLY_PM_ERRORS GetEarlyPmErrorsMulti
OPTION_MULTISOCKET_PM_NB_MIN_COF GetMinNbCofMulti;
#define GET_MIN_NB_COF GetMinNbCofMulti
OPTION_MULTISOCKET_GET_PCI_ADDRESS GetCurrPciAddrMulti;
#define GET_PCI_ADDRESS GetCurrPciAddrMulti
OPTION_MULTISOCKET_MODIFY_CURR_SOCKET_PCI ModifyCurrSocketPciMulti;
#define MODIFY_CURR_SOCKET_PCI ModifyCurrSocketPciMulti
#else
OPTION_MULTISOCKET_PM_STEPS GetNumberOfSystemPmStepsPtrSingle;
#define GET_NUM_PM_STEPS GetNumberOfSystemPmStepsPtrSingle
OPTION_MULTISOCKET_PM_CORE0_TASK RunCodeOnAllSystemCore0sSingle;
#define CORE0_PM_TASK RunCodeOnAllSystemCore0sSingle
OPTION_MULTISOCKET_PM_NB_COF GetSystemNbCofSingle;
#define GET_SYS_NB_COF GetSystemNbCofSingle
OPTION_MULTISOCKET_PM_NB_COF_UPDATE GetSystemNbCofVidUpdateSingle;
#define GET_SYS_NB_COF_UPDATE GetSystemNbCofVidUpdateSingle
OPTION_MULTISOCKET_PM_GET_EVENTS GetEarlyPmErrorsSingle;
#define GET_EARLY_PM_ERRORS GetEarlyPmErrorsSingle
OPTION_MULTISOCKET_PM_NB_MIN_COF GetMinNbCofSingle;
#define GET_MIN_NB_COF GetMinNbCofSingle
OPTION_MULTISOCKET_GET_PCI_ADDRESS GetCurrPciAddrSingle;
#define GET_PCI_ADDRESS GetCurrPciAddrSingle
OPTION_MULTISOCKET_MODIFY_CURR_SOCKET_PCI ModifyCurrSocketPciSingle;
#define MODIFY_CURR_SOCKET_PCI ModifyCurrSocketPciSingle
#endif
/* Declare the instance of the multisocket option configuration structure */
OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration = {
MULTISOCKET_STRUCT_VERSION,
GET_NUM_PM_STEPS,
CORE0_PM_TASK,
GET_SYS_NB_COF,
GET_SYS_NB_COF_UPDATE,
GET_EARLY_PM_ERRORS,
GET_MIN_NB_COF,
GET_PCI_ADDRESS,
MODIFY_CURR_SOCKET_PCI
};
#endif // _OPTION_MULTISOCKET_INSTALL_H_

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src/vendorcode/amd/agesa/f15/Config/OptionPreserveMailboxInstall.h
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/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: Preserve Mailbox
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 56186 $ @e \$Date: 2011-07-08 15:35:23 -0600 (Fri, 08 Jul 2011) $
*/
/*****************************************************************************
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
***************************************************************************/
#ifndef _OPTION_PRESERVE_MAILBOX_INSTALL_H_
#define _OPTION_PRESERVE_MAILBOX_INSTALL_H_
#include "PreserveMailbox.h"
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#define OPTION_PRESERVE_MAILBOX_FEAT
#define F10_PRESERVE_MAILBOX_SUPPORT
#define F15_PRESERVE_MAILBOX_SUPPORT
#if ((AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE))
#if ((OPTION_FAMILY10H == TRUE) || (OPTION_FAMILY15H == TRUE))
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeaturePreserveAroundMailbox;
#undef OPTION_PRESERVE_MAILBOX_FEAT
#define OPTION_PRESERVE_MAILBOX_FEAT &CpuFeaturePreserveAroundMailbox,
#endif
#if OPTION_FAMILY10H == TRUE
CONST PRESERVE_MAILBOX_FAMILY_REGISTER ROMDATA F10PreserveMailboxRegisters [] = {
{
{MAKE_SBDFO (0, 0, 0, 3, 0x168)},
0x00000FFF
},
{
{MAKE_SBDFO (0, 0, 0, 3, 0x170)},
0x00000FFF
},
{
{ILLEGAL_SBDFO},
0
}
};
CONST PRESERVE_MAILBOX_FAMILY_SERVICES ROMDATA F10PreserveMailboxServices = {
0,
TRUE,
(PRESERVE_MAILBOX_FAMILY_REGISTER *)&F10PreserveMailboxRegisters
};
#undef F10_PRESERVE_MAILBOX_SUPPORT
#define F10_PRESERVE_MAILBOX_SUPPORT {AMD_FAMILY_10, &F10PreserveMailboxServices},
#endif
#if OPTION_FAMILY15H == TRUE
CONST PRESERVE_MAILBOX_FAMILY_REGISTER ROMDATA F15PreserveMailboxRegisters [] = {
{
{MAKE_SBDFO (0, 0, 0, 3, 0x168)},
0x00000FFF
},
{
{MAKE_SBDFO (0, 0, 0, 3, 0x170)},
0x00000FFF
},
{
{ILLEGAL_SBDFO},
0
}
};
CONST PRESERVE_MAILBOX_FAMILY_SERVICES ROMDATA F15PreserveMailboxServices = {
0,
TRUE,
(PRESERVE_MAILBOX_FAMILY_REGISTER *)&F15PreserveMailboxRegisters
};
#undef F15_PRESERVE_MAILBOX_SUPPORT
#define F15_PRESERVE_MAILBOX_SUPPORT {AMD_FAMILY_15, &F15PreserveMailboxServices},
#endif
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA PreserveMailboxFamilyServiceArray[] =
{
F10_PRESERVE_MAILBOX_SUPPORT
F15_PRESERVE_MAILBOX_SUPPORT
{0, NULL}
};
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA PreserveMailboxFamilyServiceTable =
{
(sizeof (PreserveMailboxFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
&PreserveMailboxFamilyServiceArray[0]
};
#endif
#endif // _OPTION_PRESERVE_MAILBOX_INSTALL_H_

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src/vendorcode/amd/agesa/f15/Config/OptionPstateHpcModeInstall.h
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/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: Pstate HPC mode.
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 52150 $ @e \$Date: 2011-05-03 01:01:08 -0600 (Tue, 03 May 2011) $
*/
/*****************************************************************************
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
***************************************************************************/
#ifndef _OPTION_PSTATE_HPC_MODE_INSTALL_H_
#define _OPTION_PSTATE_HPC_MODE_INSTALL_H_
#include "cpuPstateHpcMode.h"
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#define OPTION_CPU_PSTATE_HPC_MODE_FEAT
#define F15_PSTATE_HPC_MODE_SUPPORT
#if OPTION_CPU_PSTATE_HPC_MODE == TRUE
#if (AGESA_ENTRY_INIT_POST == TRUE)
// Family 15h
#ifdef OPTION_FAMILY15H
#if OPTION_FAMILY15H == TRUE
// Orochi and Komodo
#if (OPTION_FAMILY15H_OR == TRUE) || (OPTION_FAMILY15H_KM == TRUE)
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeaturePstateHpcMode;
#undef OPTION_CPU_PSTATE_HPC_MODE_FEAT
#define OPTION_CPU_PSTATE_HPC_MODE_FEAT &CpuFeaturePstateHpcMode,
extern CONST PSTATE_HPC_MODE_FAMILY_SERVICES ROMDATA F15PstateHpcSupport;
#undef F15_PSTATE_HPC_MODE_SUPPORT
#define F15_PSTATE_HPC_MODE_SUPPORT {(AMD_FAMILY_15_OR | AMD_FAMILY_15_KM), &F15PstateHpcSupport},
#endif
#endif
#endif
#endif
#endif
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA PstateHpcModeFamilyServiceArray[] =
{
F15_PSTATE_HPC_MODE_SUPPORT
{0, NULL}
};
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA PstateHpcModeFamilyServiceTable =
{
(sizeof (PstateHpcModeFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
&PstateHpcModeFamilyServiceArray[0]
};
#endif // _OPTION_PSTATE_HPC_MODE_INSTALL_H_

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@ -1,264 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: PState
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 52904 $ @e \$Date: 2011-05-12 16:42:35 -0600 (Thu, 12 May 2011) $
*/
/*****************************************************************************
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
***************************************************************************/
#ifndef _OPTION_PSTATE_INSTALL_H_
#define _OPTION_PSTATE_INSTALL_H_
#include "cpuPstateTables.h"
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#define F10_PSTATE_SERVICE_SUPPORT
#define F12_PSTATE_SERVICE_SUPPORT
#define F14_PSTATE_SERVICE_SUPPORT
#define F15_OR_PSTATE_SERVICE_SUPPORT
#define F15_TN_PSTATE_SERVICE_SUPPORT
#define F15_KM_PSTATE_SERVICE_SUPPORT
#if ((AGESA_ENTRY_INIT_LATE == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE))
//
//Define Pstate CPU Family service
//
#ifdef OPTION_FAMILY10H
#if OPTION_FAMILY10H == TRUE
extern CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F10PstateServices;
#undef F10_PSTATE_SERVICE_SUPPORT
#define F10_PSTATE_SERVICE_SUPPORT {AMD_FAMILY_10, &F10PstateServices},
#endif
#endif
#ifdef OPTION_FAMILY12H
#if OPTION_FAMILY12H == TRUE
extern CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F12PstateServices;
#undef F12_PSTATE_SERVICE_SUPPORT
#define F12_PSTATE_SERVICE_SUPPORT {AMD_FAMILY_12, &F12PstateServices},
#endif
#endif
#ifdef OPTION_FAMILY14H
#if OPTION_FAMILY14H == TRUE
extern CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F14PstateServices;
#undef F14_PSTATE_SERVICE_SUPPORT
#define F14_PSTATE_SERVICE_SUPPORT {AMD_FAMILY_14, &F14PstateServices},
#endif
#endif
#ifdef OPTION_FAMILY15H
#if OPTION_FAMILY15H == TRUE
#ifdef OPTION_FAMILY15H_OR
#if OPTION_FAMILY15H_OR == TRUE
extern CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F15OrPstateServices;
#undef F15_OR_PSTATE_SERVICE_SUPPORT
#define F15_OR_PSTATE_SERVICE_SUPPORT {AMD_FAMILY_15_OR, &F15OrPstateServices},
#endif
#endif
#ifdef OPTION_FAMILY15H_TN
#if OPTION_FAMILY15H_TN == TRUE
extern CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F15TnPstateServices;
#undef F15_TN_PSTATE_SERVICE_SUPPORT
#define F15_TN_PSTATE_SERVICE_SUPPORT {AMD_FAMILY_15_TN, &F15TnPstateServices},
#endif
#endif
#ifdef OPTION_FAMILY15H_KM
#if OPTION_FAMILY15H_KM == TRUE
extern CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F15KmPstateServices;
#undef F15_KM_PSTATE_SERVICE_SUPPORT
#define F15_KM_PSTATE_SERVICE_SUPPORT {AMD_FAMILY_15_KM, &F15KmPstateServices},
#endif
#endif
#endif
#endif
//
//Define ACPI Pstate objects.
//
#ifndef OPTION_ACPI_PSTATES
#error BLDOPT: Option not defined: "OPTION_ACPI_PSTATES"
#endif
#if (OPTION_ACPI_PSTATES == TRUE)
OPTION_SSDT_FEATURE GenerateSsdt;
#define USER_SSDT_MAIN GenerateSsdt
#ifndef OPTION_MULTISOCKET
#error BLDOPT: Option not defined: "OPTION_MULTISOCKET"
#endif
OPTION_ACPI_FEATURE CreatePStateAcpiTables;
OPTION_PSTATE_GATHER PStateGatherMain;
#if ((OPTION_MULTISOCKET == TRUE) && (AGESA_ENTRY_INIT_POST == TRUE))
OPTION_PSTATE_LEVELING PStateLevelingMain;
#define USER_PSTATE_OPTION_LEVEL PStateLevelingMain
#else
OPTION_PSTATE_LEVELING PStateLevelingStub;
#define USER_PSTATE_OPTION_LEVEL PStateLevelingStub
#endif
#if AGESA_ENTRY_INIT_LATE == TRUE
#define USER_PSTATE_OPTION_MAIN CreatePStateAcpiTables
#else
OPTION_ACPI_FEATURE CreateAcpiTablesStub;
#define USER_PSTATE_OPTION_MAIN CreateAcpiTablesStub
#endif
#if AGESA_ENTRY_INIT_POST == TRUE
#define USER_PSTATE_OPTION_GATHER PStateGatherMain
#else
OPTION_PSTATE_GATHER PStateGatherStub;
#define USER_PSTATE_OPTION_GATHER PStateGatherStub
#endif
#if CFG_ACPI_PSTATES_PPC == TRUE
#define USER_PSTATE_CFG_PPC TRUE
#else
#define USER_PSTATE_CFG_PPC FALSE
#endif
#if CFG_ACPI_PSTATES_PCT == TRUE
#define USER_PSTATE_CFG_PCT TRUE
#else
#define USER_PSTATE_CFG_PCT FALSE
#endif
#if CFG_ACPI_PSTATES_PSD == TRUE
#define USER_PSTATE_CFG_PSD TRUE
#else
#define USER_PSTATE_CFG_PSD FALSE
#endif
#if CFG_ACPI_PSTATES_PSS == TRUE
#define USER_PSTATE_CFG_PSS TRUE
#else
#define USER_PSTATE_CFG_PSS FALSE
#endif
#if CFG_ACPI_PSTATES_XPSS == TRUE
#define USER_PSTATE_CFG_XPSS TRUE
#else
#define USER_PSTATE_CFG_XPSS FALSE
#endif
#if OPTION_IO_CSTATE == TRUE
OPTION_ACPI_FEATURE CreateCStateAcpiTables;
#define USER_CSTATE_OPTION_MAIN CreateCStateAcpiTables
#else
OPTION_ACPI_FEATURE CreateAcpiTablesStub;
#define USER_CSTATE_OPTION_MAIN CreateAcpiTablesStub
#endif
#else
OPTION_SSDT_FEATURE GenerateSsdtStub;
OPTION_ACPI_FEATURE CreateAcpiTablesStub;
OPTION_PSTATE_GATHER PStateGatherStub;
OPTION_PSTATE_LEVELING PStateLevelingStub;
#define USER_SSDT_MAIN GenerateSsdtStub
#define USER_PSTATE_OPTION_MAIN CreateAcpiTablesStub
#define USER_CSTATE_OPTION_MAIN CreateAcpiTablesStub
#define USER_PSTATE_OPTION_GATHER PStateGatherStub
#define USER_PSTATE_OPTION_LEVEL PStateLevelingStub
#define USER_PSTATE_CFG_PPC FALSE
#define USER_PSTATE_CFG_PCT FALSE
#define USER_PSTATE_CFG_PSD FALSE
#define USER_PSTATE_CFG_PSS FALSE
#define USER_PSTATE_CFG_XPSS FALSE
// If ACPI Objects are disabled for PStates, we still need to check
// whether ACPI Objects are enabled for CStates
#if OPTION_IO_CSTATE == TRUE
OPTION_SSDT_FEATURE GenerateSsdt;
OPTION_PSTATE_GATHER PStateGatherMain;
OPTION_ACPI_FEATURE CreateCStateAcpiTables;
#undef USER_SSDT_MAIN
#define USER_SSDT_MAIN GenerateSsdt
#undef USER_PSTATE_OPTION_GATHER
#define USER_PSTATE_OPTION_GATHER PStateGatherMain
#undef USER_CSTATE_OPTION_MAIN
#define USER_CSTATE_OPTION_MAIN CreateCStateAcpiTables
#endif
#endif
#else
OPTION_SSDT_FEATURE GenerateSsdtStub;
OPTION_ACPI_FEATURE CreateAcpiTablesStub;
OPTION_PSTATE_GATHER PStateGatherStub;
OPTION_PSTATE_LEVELING PStateLevelingStub;
#define USER_SSDT_MAIN GenerateSsdtStub
#define USER_PSTATE_OPTION_MAIN CreateAcpiTablesStub
#define USER_CSTATE_OPTION_MAIN CreateAcpiTablesStub
#define USER_PSTATE_OPTION_GATHER PStateGatherStub
#define USER_PSTATE_OPTION_LEVEL PStateLevelingStub
#define USER_PSTATE_CFG_PPC FALSE
#define USER_PSTATE_CFG_PCT FALSE
#define USER_PSTATE_CFG_PSD FALSE
#define USER_PSTATE_CFG_PSS FALSE
#define USER_PSTATE_CFG_XPSS FALSE
#endif
/* Declare the instance of the PSTATE option configuration structure */
OPTION_PSTATE_POST_CONFIGURATION OptionPstatePostConfiguration = {
PSTATE_STRUCT_VERSION,
USER_PSTATE_OPTION_GATHER,
USER_PSTATE_OPTION_LEVEL
};
OPTION_PSTATE_LATE_CONFIGURATION OptionPstateLateConfiguration = {
PSTATE_STRUCT_VERSION,
USER_SSDT_MAIN,
USER_PSTATE_OPTION_MAIN,
USER_CSTATE_OPTION_MAIN,
USER_PSTATE_CFG_PPC,
USER_PSTATE_CFG_PCT,
USER_PSTATE_CFG_PSD,
USER_PSTATE_CFG_PSS,
USER_PSTATE_CFG_XPSS
};
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA PstateCpuFamilyServiceArray[] =
{
F10_PSTATE_SERVICE_SUPPORT
F12_PSTATE_SERVICE_SUPPORT
F14_PSTATE_SERVICE_SUPPORT
F15_OR_PSTATE_SERVICE_SUPPORT
F15_TN_PSTATE_SERVICE_SUPPORT
F15_KM_PSTATE_SERVICE_SUPPORT
{0, NULL}
};
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA PstateFamilyServiceTable =
{
(sizeof (PstateCpuFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
&PstateCpuFamilyServiceArray[0]
};
#endif // _OPTION_PSTATE_INSTALL_H_

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/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: S3SCRIPT
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_S3SCRIPT_INSTALL_H_
#define _OPTION_S3SCRIPT_INSTALL_H_
#include "S3SaveState.h"
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#ifndef OPTION_S3SCRIPT
#define OPTION_S3SCRIPT FALSE //if not define assume PI not use script
#endif
#if (AGESA_ENTRY_INIT_LATE == TRUE) || (AGESA_ENTRY_INIT_ENV == TRUE) || (AGESA_ENTRY_INIT_MID == TRUE)
#if OPTION_S3SCRIPT == TRUE
#define P_S3_SCRIPT_INIT S3ScriptInitState
#endif
#endif
#if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE
#if OPTION_S3SCRIPT == TRUE
#define P_S3_SCRIPT_RESTORE S3ScriptRestoreState
#endif
#endif
#ifndef P_S3_SCRIPT_INIT
#define P_S3_SCRIPT_INIT S3ScriptInitStateStub
#endif
#ifndef P_S3_SCRIPT_RESTORE
#define P_S3_SCRIPT_RESTORE S3ScriptInitStateStub
#undef GNB_S3_DISPATCH_FUNCTION_TABLE
#endif
#ifndef GNB_S3_DISPATCH_FUNCTION_TABLE
#define GNB_S3_DISPATCH_FUNCTION_TABLE
#endif
/* Declare the instance of the S3SCRIPT option configuration structure */
S3_SCRIPT_CONFIGURATION OptionS3ScriptConfiguration = {
P_S3_SCRIPT_INIT,
P_S3_SCRIPT_RESTORE
};
S3_DISPATCH_FUNCTION_ENTRY S3DispatchFunctionTable [] = {
GNB_S3_DISPATCH_FUNCTION_TABLE
{0, NULL}
};
#endif // _OPTION_S3SCRIPT_INSTALL_H_

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/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: SLIT
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_SLIT_INSTALL_H_
#define _OPTION_SLIT_INSTALL_H_
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#if AGESA_ENTRY_INIT_LATE == TRUE
#ifndef OPTION_SLIT
#error BLDOPT: Option not defined: "OPTION_SLIT"
#endif
#if OPTION_SLIT == TRUE
OPTION_SLIT_FEATURE GetAcpiSlitMain;
OPTION_SLIT_RELEASE_BUFFER ReleaseSlitBuffer;
#define USER_SLIT_OPTION GetAcpiSlitMain
#define USER_SLIT_RELEASE_BUFFER ReleaseSlitBuffer
#else
OPTION_SLIT_FEATURE GetAcpiSlitStub;
OPTION_SLIT_RELEASE_BUFFER ReleaseSlitBufferStub;
#define USER_SLIT_OPTION GetAcpiSlitStub
#define USER_SLIT_RELEASE_BUFFER ReleaseSlitBufferStub
#endif
#else
OPTION_SLIT_FEATURE GetAcpiSlitStub;
OPTION_SLIT_RELEASE_BUFFER ReleaseSlitBufferStub;
#define USER_SLIT_OPTION GetAcpiSlitStub
#define USER_SLIT_RELEASE_BUFFER ReleaseSlitBufferStub
#endif
/* Declare the instance of the SLIT option configuration structure */
OPTION_SLIT_CONFIGURATION OptionSlitConfiguration = {
SLIT_STRUCT_VERSION,
USER_SLIT_OPTION,
USER_SLIT_RELEASE_BUFFER
};
#endif // _OPTION_SLIT_INSTALL_H_

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/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: SRAT
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_SRAT_INSTALL_H_
#define _OPTION_SRAT_INSTALL_H_
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#if AGESA_ENTRY_INIT_LATE == TRUE
#ifndef OPTION_SRAT
#error BLDOPT: Option not defined: "OPTION_SRAT"
#endif
#if OPTION_SRAT == TRUE
OPTION_SRAT_FEATURE GetAcpiSratMain;
#define USER_SRAT_OPTION GetAcpiSratMain
#else
OPTION_SRAT_FEATURE GetAcpiSratStub;
#define USER_SRAT_OPTION GetAcpiSratStub
#endif
#else
OPTION_SRAT_FEATURE GetAcpiSratStub;
#define USER_SRAT_OPTION GetAcpiSratStub
#endif
/* Declare the instance of the WHEA option configuration structure */
OPTION_SRAT_CONFIGURATION OptionSratConfiguration = {
SRAT_STRUCT_VERSION,
USER_SRAT_OPTION
};
#endif // _OPTION_WHEA_INSTALL_H_

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/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: SW C1e
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_SW_C1E_INSTALL_H_
#define _OPTION_SW_C1E_INSTALL_H_
#include "cpuSwC1e.h"
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#define OPTION_SW_C1E_FEAT
#define F10_SW_C1E_SUPPORT
#if AGESA_ENTRY_INIT_EARLY == TRUE
#ifdef OPTION_FAMILY10H
#if OPTION_FAMILY10H == TRUE
#if (OPTION_FAMILY10H_BL == TRUE) || (OPTION_FAMILY10H_DA == TRUE) || (OPTION_FAMILY10H_RB == TRUE) || (OPTION_FAMILY10H_PH == TRUE)
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureSwC1e;
#undef OPTION_SW_C1E_FEAT
#define OPTION_SW_C1E_FEAT &CpuFeatureSwC1e,
extern CONST SW_C1E_FAMILY_SERVICES ROMDATA F10SwC1e;
#undef F10_SW_C1E_SUPPORT
#define F10_SW_C1E_SUPPORT {(AMD_FAMILY_10_BL | AMD_FAMILY_10_DA | AMD_FAMILY_10_RB | AMD_FAMILY_10_PH), &F10SwC1e},
#endif
#endif
#endif
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA SwC1eFamilyServiceArray[] =
{
F10_SW_C1E_SUPPORT
{0, NULL}
};
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA SwC1eFamilyServiceTable =
{
(sizeof (SwC1eFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
&SwC1eFamilyServiceArray[0]
};
#endif
#endif // _OPTION_SW_C1E_INSTALL_H_

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/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: WHEA
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_WHEA_INSTALL_H_
#define _OPTION_WHEA_INSTALL_H_
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#if AGESA_ENTRY_INIT_LATE == TRUE
#ifndef OPTION_WHEA
#error BLDOPT: Option not defined: "OPTION_WHEA"
#endif
#if OPTION_WHEA == TRUE
OPTION_WHEA_FEATURE GetAcpiWheaMain;
#define USER_WHEA_OPTION GetAcpiWheaMain
#else
OPTION_WHEA_FEATURE GetAcpiWheaStub;
#define USER_WHEA_OPTION GetAcpiWheaStub
#endif
#else
OPTION_WHEA_FEATURE GetAcpiWheaStub;
#define USER_WHEA_OPTION GetAcpiWheaStub
#endif
/* Declare the instance of the WHEA option configuration structure */
OPTION_WHEA_CONFIGURATION OptionWheaConfiguration = {
WHEA_STRUCT_VERSION,
USER_WHEA_OPTION
};
#endif // _OPTION_WHEA_INSTALL_H_

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src/vendorcode/amd/agesa/f15/Config/PlatformInstall.h
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/* $NoKeywords:$ */
/**
* @file
*
* AMD Pushhigh Interface
*
* Contains interface to Pushhigh entry
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Legacy
*
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ***************************************************************************
*/
#ifndef _DISPATCHER_H_
#define _DISPATCHER_H_
// AGESA function prototypes
AGESA_STATUS CALLCONV AmdAgesaDispatcher ( IN OUT VOID *ConfigPtr );
AGESA_STATUS CALLCONV AmdAgesaCallout ( IN UINT32 Func, IN UINTN Data, IN OUT VOID *ConfigPtr );
#endif // _DISPATCHER_H_

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src/vendorcode/amd/agesa/f15/Include/AdvancedApi.h
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/* $NoKeywords:$ */
/**
* @file
*
* Advanced API Interface for HT, Memory and CPU
*
* Contains additional declarations need to use HT, Memory and CPU Advanced interface, such as
* would be required by the basic interface implementations.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Include
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _ADVANCED_API_H_
#define _ADVANCED_API_H_
/*----------------------------------------------------------------------------
* HT FUNCTIONS PROTOTYPE
*
*----------------------------------------------------------------------------
*/
/**
* A constructor for the HyperTransport input structure.
*
* Sets inputs to valid, basic level, defaults.
*
* @param[in] StdHeader Opaque handle to standard config header
* @param[in] AmdHtInterface HT Interface structure to initialize.
*
* @retval AGESA_SUCCESS Constructors are not allowed to fail
*/
AGESA_STATUS
AmdHtInterfaceConstructor (
IN AMD_CONFIG_PARAMS *StdHeader,
IN AMD_HT_INTERFACE *AmdHtInterface
);
/**
* The top level external interface for Hypertransport Initialization.
*
* Create our initial internal state, initialize the coherent fabric,
* initialize the non-coherent chains, and perform any required fabric tuning or
* optimization.
*
* @param[in] StdHeader Opaque handle to standard config header
* @param[in] PlatformConfiguration The platform configuration options.
* @param[in] AmdHtInterface HT Interface structure.
*
* @retval AGESA_SUCCESS Only information events logged.
* @retval AGESA_ALERT Sync Flood or CRC error logged.
* @retval AGESA_WARNING Example: expected capability not found
* @retval AGESA_ERROR logged events indicating some devices may not be available
* @retval AGESA_FATAL Mixed Family or MP capability mismatch
*
*/
AGESA_STATUS
AmdHtInitialize (
IN AMD_CONFIG_PARAMS *StdHeader,
IN PLATFORM_CONFIGURATION *PlatformConfiguration,
IN AMD_HT_INTERFACE *AmdHtInterface
);
/*----------------------------------------------------------------------------
* HT Recovery FUNCTIONS PROTOTYPE
*
*----------------------------------------------------------------------------
*/
/**
* A constructor for the HyperTransport input structure.
*
*/
AGESA_STATUS
AmdHtResetConstructor (
IN AMD_CONFIG_PARAMS *StdHeader,
IN AMD_HT_RESET_INTERFACE *AmdHtResetInterface
);
/**
* Initialize HT at Reset for both Normal and Recovery.
*
*/
AGESA_STATUS
AmdHtInitReset (
IN AMD_CONFIG_PARAMS *StdHeader,
IN AMD_HT_RESET_INTERFACE *AmdHtResetInterface
);
/**
* Initialize the Node and Socket maps for an AP Core.
*
*/
AGESA_STATUS
AmdHtInitRecovery (
IN AMD_CONFIG_PARAMS *StdHeader
);
///----------------------------------------------------------------------------
/// MEMORY FUNCTIONS PROTOTYPE
///
///----------------------------------------------------------------------------
AGESA_STATUS
AmdMemRecovery (
IN OUT MEM_DATA_STRUCT *MemPtr
);
AGESA_STATUS
AmdMemAuto (
IN OUT MEM_DATA_STRUCT *MemPtr
);
VOID
AmdMemInitDataStructDef (
IN OUT MEM_DATA_STRUCT *MemPtr,
IN OUT PLATFORM_CONFIGURATION *PlatFormConfig
);
VOID
memDefRet ( VOID );
BOOLEAN
memDefTrue ( VOID );
BOOLEAN
memDefFalse ( VOID );
VOID
MemRecDefRet ( VOID );
BOOLEAN
MemRecDefTrue ( VOID );
#endif // _ADVANCED_API_H_

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/* $NoKeywords:$ */
/**
* @file
*
* Common Return routines.
*
* Routines which do nothing, returning a result (preferably some version of zero) which
* is consistent with "do nothing" or "default". Useful for function pointer tables.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Common
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ***************************************************************************
*
*/
#ifndef _COMMON_RETURNS_H_
#define _COMMON_RETURNS_H_
/**
* Return True
*
* @retval True Default case, no special action
*/
BOOLEAN
CommonReturnTrue ( VOID );
/**
* Return False.
*
* @retval FALSE Default case, no special action
*/
BOOLEAN
CommonReturnFalse ( VOID );
/**
* Return (UINT8)zero.
*
*
* @retval zero None, or only case zero.
*/
UINT8
CommonReturnZero8 ( VOID );
/**
* Return (UINT32)zero.
*
*
* @retval zero None, or only case zero.
*/
UINT32
CommonReturnZero32 ( VOID );
/**
* Return (UINT64)zero.
*
*
* @retval zero None, or only case zero.
*/
UINT64
CommonReturnZero64 ( VOID );
/**
* Return NULL
*
* @retval NULL pointer to nothing
*/
VOID *
CommonReturnNULL ( VOID );
/**
* Return AGESA_SUCCESS.
*
* @retval AGESA_SUCCESS Success.
*/
AGESA_STATUS
CommonReturnAgesaSuccess ( VOID );
/**
* Do Nothing.
*
*/
VOID
CommonVoid ( VOID );
/**
* ASSERT if this routine is called.
*
*/
VOID
CommonAssert ( VOID );
#endif // _COMMON_RETURNS_H_

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src/vendorcode/amd/agesa/f15/Include/Filecode.h
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src/vendorcode/amd/agesa/f15/Include/GeneralServices.h
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/* $NoKeywords:$ */
/**
* @file
*
* General Services
*
* Provides Services similar to the external General Services API, except
* suited to use within AGESA components. Socket, Core and PCI identification.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Common
*
*/
/*
******************************************************************************
*
* Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
#ifndef _GENERAL_SERVICES_H_
#define _GENERAL_SERVICES_H_
/*----------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
#define NUMBER_OF_EVENT_DATA_PARAMS 4
/**
* AMD Device id for MMIO check.
*/
#define AMD_DEV_VEN_ID 0x1022
#define AMD_DEV_VEN_ID_ADDRESS 0
/*----------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*----------------------------------------------------------------------------------------
*/
/**
* An AGESA Event Log entry.
*/
typedef struct {
AGESA_STATUS EventClass; ///< The severity of the event, its associated AGESA_STATUS.
UINT32 EventInfo; ///< Uniquely identifies the event.
UINT32 DataParam1; ///< Event specific additional data
UINT32 DataParam2; ///< Event specific additional data
UINT32 DataParam3; ///< Event specific additional data
UINT32 DataParam4; ///< Event specific additional data
} AGESA_EVENT;
/*----------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*----------------------------------------------------------------------------------------
*/
/**
* Get a specified Core's APIC ID.
*
* @param[in] StdHeader Header for library and services.
* @param[in] Socket The Core's Socket.
* @param[in] Core The Core id.
* @param[out] ApicAddress The Core's APIC ID.
* @param[out] AgesaStatus Aggregates AGESA_STATUS for external interface, Always Succeeds.
*
* @retval TRUE The core is present, APIC Id valid
* @retval FALSE The core is not present, APIC Id not valid.
*/
BOOLEAN
GetApicId (
IN AMD_CONFIG_PARAMS *StdHeader,
IN UINT32 Socket,
IN UINT32 Core,
OUT UINT8 *ApicAddress,
OUT AGESA_STATUS *AgesaStatus
);
/**
* Get Processor Module's PCI Config Space address.
*
* @param[in] StdHeader Header for library and services.
* @param[in] Socket The Core's Socket.
* @param[in] Module The Module in that Processor
* @param[out] PciAddress The Processor's PCI Config Space address (Function 0, Register 0)
* @param[out] AgesaStatus Aggregates AGESA_STATUS for external interface, Always Succeeds.
*
* @retval TRUE The core is present, PCI Address valid
* @retval FALSE The core is not present, PCI Address not valid.
*/
BOOLEAN
GetPciAddress (
IN AMD_CONFIG_PARAMS *StdHeader,
IN UINT32 Socket,
IN UINT32 Module,
OUT PCI_ADDR *PciAddress,
OUT AGESA_STATUS *AgesaStatus
);
/**
* "Who am I" for the current running core.
*
* @param[in] StdHeader Header for library and services.
* @param[out] Socket The current Core's Socket
* @param[out] Module The current Core's Processor Module
* @param[out] Core The current Core's core id.
* @param[out] AgesaStatus Aggregates AGESA_STATUS for external interface, Always Succeeds.
*
*/
VOID
IdentifyCore (
IN AMD_CONFIG_PARAMS *StdHeader,
OUT UINT32 *Socket,
OUT UINT32 *Module,
OUT UINT32 *Core,
OUT AGESA_STATUS *AgesaStatus
);
/**
* A boolean function determine executed CPU is BSP core.
*/
BOOLEAN
IsBsp (
IN OUT AMD_CONFIG_PARAMS *StdHeader,
OUT AGESA_STATUS *AgesaStatus
);
/**
* This function logs AGESA events into the event log.
*/
VOID
PutEventLog (
IN AGESA_STATUS EventClass,
IN UINT32 EventInfo,
IN UINT32 DataParam1,
IN UINT32 DataParam2,
IN UINT32 DataParam3,
IN UINT32 DataParam4,
IN AMD_CONFIG_PARAMS *StdHeader
);
/**
* This function gets event logs from the circular buffer.
*/
AGESA_STATUS
GetEventLog (
OUT AGESA_EVENT *EventRecord,
IN AMD_CONFIG_PARAMS *StdHeader
);
/**
* This function gets event logs from the circular buffer without flushing the entry.
*/
BOOLEAN
PeekEventLog (
OUT AGESA_EVENT *EventRecord,
IN UINT16 Index,
IN AMD_CONFIG_PARAMS *StdHeader
);
/*---------------------------------------------------------------------------------------*/
/**
* This routine programs the registers necessary to get the PCI MMIO mechanism
* up and functioning.
*/
VOID
InitializePciMmio (
IN AMD_CONFIG_PARAMS *StdHeader
);
#endif // _GENERAL_SERVICES_H_

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src/vendorcode/amd/agesa/f15/Include/GnbInterface.h
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/* $NoKeywords:$ */
/**
* @file
*
* GNB API definition.
*
*
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: GNB
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
#ifndef _GNBINTERFACE_H_
#define _GNBINTERFACE_H_
AGESA_STATUS
GnbInitAtReset (
IN AMD_CONFIG_PARAMS *StdHeader
);
AGESA_STATUS
GnbInitAtEarly (
IN OUT AMD_EARLY_PARAMS *EarlyParamsPtr
);
AGESA_STATUS
GnbInitAtPost (
IN OUT AMD_POST_PARAMS *PostParamsPtr
);
VOID
GnbInitDataStructAtEnvDef (
IN OUT GNB_ENV_CONFIGURATION *GnbEnvConfigPtr,
IN AMD_ENV_PARAMS *EnvParamsPtr
);
AGESA_STATUS
GnbInitAtEnv (
IN AMD_ENV_PARAMS *EnvParamsPtr
);
AGESA_STATUS
GnbInitAtMid (
IN OUT AMD_MID_PARAMS *MidParamsPtr
);
AGESA_STATUS
GnbInitAtLate (
IN OUT AMD_LATE_PARAMS *LateParamsPtr
);
AGESA_STATUS
GnbInitAtPostAfterDram (
IN OUT AMD_POST_PARAMS *PostParamsPtr
);
AGESA_STATUS
AmdGnbRecovery (
IN AMD_CONFIG_PARAMS *StdHeader
);
AGESA_STATUS
GnbInitAtEarlier (
IN OUT AMD_EARLY_PARAMS *EarlyParamsPtr
);
#endif

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/* $NoKeywords:$ */
/**
* @file
*
*
*
*
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: GNB
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
AGESA_STATUS
GnbInitAtReset (
IN AMD_CONFIG_PARAMS *StdHeader
);
AGESA_STATUS
GnbInitAtEarly (
IN OUT AMD_EARLY_PARAMS *EarlyParamsPtr
);
VOID
GnbInitDataStructAtEnvDef (
IN OUT GNB_ENV_CONFIGURATION *GnbEnvConfigPtr,
IN AMD_ENV_PARAMS *EnvParamsPtr
);
AGESA_STATUS
GnbInitAtEnv (
IN AMD_ENV_PARAMS *EnvParamsPtr
);
AGESA_STATUS
GnbInitAtPost (
IN OUT AMD_POST_PARAMS *PostParamsPtr
);
AGESA_STATUS
GnbInitAtMid (
IN OUT AMD_MID_PARAMS *MidParamsPtr
);
AGESA_STATUS
GnbInitAtLate (
IN OUT AMD_LATE_PARAMS *LateParamsPtr
);
AGESA_STATUS
AmdGnbRecovery (
IN AMD_CONFIG_PARAMS *StdHeader
);
AGESA_STATUS
GnbInitAtPostAfterDram (
IN OUT AMD_POST_PARAMS *PostParamsPtr
);
AGESA_STATUS
GnbInitAtEarlier (
IN OUT AMD_EARLY_PARAMS *EarlyParamsPtr
);
/*----------------------------------------------------------------------------------------*/
/**
* Init GNB at Reset Stub
*
*
*
* @param[in] StdHeader Standard configuration header
* @retval AGESA_SUCCESS Always succeeds
*/
AGESA_STATUS
GnbInitAtReset (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
return AGESA_SUCCESS;
}
/*----------------------------------------------------------------------------------------*/
/**
* Init GNB at Early Stub
*
*
*
* @param[in,out] EarlyParamsPtr Pointer to early configuration params.
* @retval AGESA_SUCCESS Always succeeds
*/
AGESA_STATUS
GnbInitAtEarly (
IN OUT AMD_EARLY_PARAMS *EarlyParamsPtr
)
{
return AGESA_SUCCESS;
}
/*----------------------------------------------------------------------------------------*/
/**
* Default constructor of GNB configuration at Env
*
*
*
* @param[in] GnbEnvConfigPtr Pointer to gnb env configuration params.
* @param[in] EnvParamsPtr Pointer to env configuration params.
*/
VOID
GnbInitDataStructAtEnvDef (
IN OUT GNB_ENV_CONFIGURATION *GnbEnvConfigPtr,
IN AMD_ENV_PARAMS *EnvParamsPtr
)
{
}
/*----------------------------------------------------------------------------------------*/
/**
* Init GNB at Env
*
*
*
* @param[in] EnvParamsPtr Pointer to env configuration params.
* @retval AGESA_SUCCESS Always succeeds
*/
AGESA_STATUS
GnbInitAtEnv (
IN AMD_ENV_PARAMS *EnvParamsPtr
)
{
return AGESA_SUCCESS;
}
/*----------------------------------------------------------------------------------------*/
/**
* Init GNB at Post
*
*
*
* @param[in,out] PostParamsPtr Pointer to Post configuration params.
* @retval AGESA_SUCCESS Always succeeds
*/
AGESA_STATUS
GnbInitAtPost (
IN OUT AMD_POST_PARAMS *PostParamsPtr
)
{
return AGESA_SUCCESS;
}
/*----------------------------------------------------------------------------------------*/
/**
* Init GNB at Mid post
*
*
*
* @param[in,out] MidParamsPtr Pointer to mid configuration params.
* @retval AGESA_SUCCESS Always succeeds
*/
AGESA_STATUS
GnbInitAtMid (
IN OUT AMD_MID_PARAMS *MidParamsPtr
)
{
return AGESA_SUCCESS;
}
/*----------------------------------------------------------------------------------------*/
/**
* Init GNB at Late post
*
*
*
* @param[in,out] LateParamsPtr Pointer to late configuration params.
* @retval AGESA_SUCCESS Always succeeds
*/
AGESA_STATUS
GnbInitAtLate (
IN OUT AMD_LATE_PARAMS *LateParamsPtr
)
{
return AGESA_SUCCESS;
}
/*----------------------------------------------------------------------------------------*/
/**
* AmdGnbRecovery
*
*
*
* @param[in] StdHeader Standard configuration header
* @retval AGESA_SUCCESS Always succeeds
*/
AGESA_STATUS
AmdGnbRecovery (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
return AGESA_SUCCESS;
}
/*----------------------------------------------------------------------------------------*/
/**
* Init GNB at Post after DRAM init
*
*
*
* @param[in] PostParamsPtr Pointer to post configuration parameters
* @retval AGESA_SUCCESS Always succeeds
*/
AGESA_STATUS
GnbInitAtPostAfterDram (
IN OUT AMD_POST_PARAMS *PostParamsPtr
)
{
return AGESA_SUCCESS;
}
/*----------------------------------------------------------------------------------------*/
/**
* Init GNB at Early Before CPU Stub
*
*
*
* @param[in,out] EarlyParamsPtr Pointer to early configuration params.
* @retval AGESA_SUCCESS Always succeeds
*/
AGESA_STATUS
GnbInitAtEarlier (
IN OUT AMD_EARLY_PARAMS *EarlyParamsPtr
)
{
return AGESA_SUCCESS;
}

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@ -1,122 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD IDS HyperTransport Definitions
*
* Contains AMD AGESA Integrated Debug HT related items.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: IDS
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _IDS_HT_H_
#define _IDS_HT_H_
// Frequency equates for call backs which take an actual frequency setting
#define HT_FREQUENCY_200M 0
#define HT_FREQUENCY_400M 2
#define HT_FREQUENCY_600M 4
#define HT_FREQUENCY_800M 5
#define HT_FREQUENCY_1000M 6
#define HT_FREQUENCY_1200M 7
#define HT_FREQUENCY_1400M 8
#define HT_FREQUENCY_1600M 9
#define HT_FREQUENCY_1800M 10
#define HT_FREQUENCY_2000M 11
#define HT_FREQUENCY_2200M 12
#define HT_FREQUENCY_2400M 13
#define HT_FREQUENCY_2600M 14
#define HT_FREQUENCY_2800M 17
#define HT_FREQUENCY_3000M 18
#define HT_FREQUENCY_3200M 19
#define HT_FREQUENCY_3600M 20
/**
* HT IDS: HT Link Port Override params.
*
* Provide an absolute override of HT Link Port settings. No checking is done that
* the settings obey limits or capabilities, this responsibility rests with the user.
*
* Rules for values of structure items:
* - Socket
* - HT_LIST_TERMINAL == end of port override list, rest of item is not accessed
* - HT_LIST_MATCH_ANY == Match Any Socket
* - 0 .. 7 == The matching socket
* - Link
* - HT_LIST_MATCH_ANY == Match Any package link (that is not the internal links)
* - HT_LIST_MATCH_INTERNAL_LINK == Match the internal links
* - 0 .. 7 == The matching package link. 0 .. 3 are the ganged links or sublink 0's, 4 .. 7 are the sublink1's.
* - Frequency
* - HT_LIST_TERMINAL == Do not override the frequency, AUTO setting
* - HT_FREQUENCY_200M .. HT_FREQUENCY_3600M = The frequency value to use
* - Widthin
* - HT_LIST_TERMINAL == Do not override the width, AUTO setting
* - 2, 4, 8, 16, 32 == The width value to use
* - Widthout
* - HT_LIST_TERMINAL == Do not override the width, AUTO setting
* - 2, 4, 8, 16, 32 == The width value to use
*/
typedef struct {
// Match Fields
UINT8 Socket; ///< The Socket which this port is on.
UINT8 Link; ///< The port for this package link on that socket.
// Override fields
UINT8 Frequency; ///< Absolutely override the port's frequency.
UINT8 WidthIn; ///< Absolutely override the port's width.
UINT8 WidthOut; ///< Absolutely override the port's width.
} HTIDS_PORT_OVERRIDE;
/**
* A list of port overrides to search.
*/
typedef HTIDS_PORT_OVERRIDE *HTIDS_PORT_OVERRIDE_LIST;
VOID
HtIdsGetPortOverride (
IN BOOLEAN IsSourcePort,
IN OUT PORT_DESCRIPTOR *Port0,
IN OUT PORT_DESCRIPTOR *Port1,
IN OUT HTIDS_PORT_OVERRIDE_LIST *PortOverrideList,
IN STATE_DATA *State
);
typedef
VOID
F_HtIdsGetPortOverride (
IN BOOLEAN IsSourcePort,
IN OUT PORT_DESCRIPTOR *Port0,
IN OUT PORT_DESCRIPTOR *Port1,
IN OUT HTIDS_PORT_OVERRIDE_LIST *PortOverrideList,
IN STATE_DATA *State
);
typedef F_HtIdsGetPortOverride* PF_HtIdsGetPortOverride;
#endif // _IDS_HT_H

116
src/vendorcode/amd/agesa/f15/Include/MaranelloInstall.h
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@ -1,116 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Install of build options for a Maranello platform solution
*
* This file generates the defaults tables for the "Maranello" platform solution
* set of processors. The documented build options are imported from a user
* controlled file for processing.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Core
* @e \$Revision: 59375 $ @e \$Date: 2011-09-21 13:24:35 -0600 (Wed, 21 Sep 2011) $
*/
/*****************************************************************************
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
***************************************************************************/
#include "cpuRegisters.h"
#include "cpuFamRegisters.h"
#include "cpuFamilyTranslation.h"
#include "AdvancedApi.h"
#include "heapManager.h"
#include "CreateStruct.h"
#include "cpuFeatures.h"
#include "Table.h"
#include "CommonReturns.h"
#include "cpuEarlyInit.h"
#include "cpuLateInit.h"
#include "GnbInterfaceStub.h"
/*****************************************************************************
* Define the RELEASE VERSION string
*
* The Release Version string should identify the next planned release.
* When a branch is made in preparation for a release, the release manager
* should change/confirm that the branch version of this file contains the
* string matching the desired version for the release. The trunk version of
* the file should always contain a trailing 'X'. This will make sure that a
* development build from trunk will not be confused for a released version.
* The release manager will need to remove the trailing 'X' and update the
* version string as appropriate for the release. The trunk copy of this file
* should also be updated/incremented for the next expected version, + trailing 'X'
****************************************************************************/
// This is the delivery package title, "MarG34PI"
// This string MUST be exactly 8 characters long
#define AGESA_PACKAGE_STRING {'O', 'r', 'o', 'c', 'h', 'i', 'P', 'I'}
// This is the release version number of the AGESA component
// This string MUST be exactly 12 characters long
#define AGESA_VERSION_STRING {'V', '1', '.', '2', '.', '0', '.', '0', ' ', ' ', ' ', ' '}
// The Maranello solution is defined to be families 0x10 and 0x15 models 0x0 - 0xF in the G34 socket.
#define INSTALL_G34_SOCKET_SUPPORT TRUE
#define INSTALL_FAMILY_10_SUPPORT TRUE
#define INSTALL_FAMILY_15_MODEL_0x_SUPPORT TRUE
#ifdef BLDOPT_REMOVE_FAMILY_10_SUPPORT
#if BLDOPT_REMOVE_FAMILY_10_SUPPORT == TRUE
#undef INSTALL_FAMILY_10_SUPPORT
#define INSTALL_FAMILY_10_SUPPORT FALSE
#endif
#endif
#ifdef BLDOPT_REMOVE_FAMILY_15_SUPPORT
#if BLDOPT_REMOVE_FAMILY_15_SUPPORT == TRUE
#undef INSTALL_FAMILY_15_MODEL_0x_SUPPORT
#define INSTALL_FAMILY_15_MODEL_0x_SUPPORT FALSE
#endif
#endif
// The following definitions specify the default values for various parameters in which there are
// no clearly defined defaults to be used in the common file. The values below are based on product
// and BKDG content, please consult the AGESA Memory team for consultation.
#define DFLT_SCRUB_DRAM_RATE (0xFF)
#define DFLT_SCRUB_L2_RATE (0x10)
#define DFLT_SCRUB_L3_RATE (0x10)
#define DFLT_SCRUB_IC_RATE (0)
#define DFLT_SCRUB_DC_RATE (0x12)
#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_REGISTERED
#define DFLT_VRM_SLEW_RATE (2500)
// Instantiate all solution relevant data.
#include "PlatformInstall.h"

88
src/vendorcode/amd/agesa/f15/Include/OptionDmi.h
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@ -1,88 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD DMI option API.
*
* Contains structures and values used to control the DMI option code.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: OPTION
*
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
#ifndef _OPTION_DMI_H_
#define _OPTION_DMI_H_
/*----------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*----------------------------------------------------------------------------------------
*/
typedef AGESA_STATUS OPTION_DMI_FEATURE (
IN OUT AMD_CONFIG_PARAMS *StdHeader,
IN OUT DMI_INFO **DmiPtr
);
typedef AGESA_STATUS OPTION_DMI_RELEASE_BUFFER (
IN OUT AMD_CONFIG_PARAMS *StdHeader
);
#define DMI_STRUCT_VERSION 0x01
/// DMI option configuration. Determine the item of structure when compiling.
typedef struct {
UINT16 OptDmiVersion; ///< Dmi version.
OPTION_DMI_FEATURE *DmiFeature; ///< Feature main routine, otherwise dummy.
OPTION_DMI_RELEASE_BUFFER *DmiReleaseBuffer; ///< Release buffer
UINT16 NumEntries; ///< Number of entry.
VOID *((*FamilyList)[]); ///< Family service.
} OPTION_DMI_CONFIGURATION;
/*----------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*----------------------------------------------------------------------------------------
*/
#endif // _OPTION_DMI_H_

231
src/vendorcode/amd/agesa/f15/Include/OptionFamily15hEarlySample.h
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@ -1,231 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Family 15h 'early sample' support
*
* This file defines the required structures for family 15h pre-production processors.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Core
* @e \$Revision: 53356 $ @e \$Date: 2011-05-18 14:14:18 -0600 (Wed, 18 May 2011) $
*/
/*****************************************************************************
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
***************************************************************************/
#ifndef _OPTION_FAMILY_15H_EARLY_SAMPLE_H_
#define _OPTION_FAMILY_15H_EARLY_SAMPLE_H_
/*---------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*---------------------------------------------------------------------------------------
*/
/*
* Install family 15h model 0x00 - 0x0F Early Sample support
*/
/**
* Early sample hook point during HTC initialization
*
* @param[in,out] HtcRegister Value of F3x64 to be written.
* @param[in] StdHeader Handle of Header for calling lib functions and services.
*
*/
typedef VOID F_F15_OR_ES_HTC_INIT_HOOK (
IN OUT UINT32 *HtcRegister,
IN AMD_CONFIG_PARAMS *StdHeader
);
/// Reference to a Method.
typedef F_F15_OR_ES_HTC_INIT_HOOK *PF_F15_OR_ES_HTC_INIT_HOOK;
/// Hook points in the core functionality necessary for
/// providing support for pre-production CPUs.
typedef struct {
PF_F15_OR_ES_HTC_INIT_HOOK F15OrHtcInitHook; ///< Allows for override of a certain processor register value during HTC init
} F15_OR_ES_CORE_SUPPORT;
/**
* Returns whether or not the processor should enable the CPB feature.
*
* @param[in,out] IsEnabled Whether or not to enable CPB
* @param[in] StdHeader Handle of Header for calling lib functions and services.
*
*/
typedef VOID F_F15_OR_ES_IS_CPB_SUPPORTED (
IN OUT BOOLEAN *IsEnabled,
IN AMD_CONFIG_PARAMS *StdHeader
);
/// Reference to a Method.
typedef F_F15_OR_ES_IS_CPB_SUPPORTED *PF_F15_OR_ES_IS_CPB_SUPPORTED;
/// Hook points in the CPB feature necessary for
/// providing support for pre-production CPUs.
typedef struct {
PF_F15_OR_ES_IS_CPB_SUPPORTED F15OrIsCpbSupportedHook; ///< CPB enablement override
} F15_OR_ES_CPB_SUPPORT;
/**
* Returns whether or not the processor should enable the C6 feature.
*
* @param[in,out] IsEnabled Whether or not to enable C6
* @param[in] StdHeader Handle of Header for calling lib functions and services.
*
*/
typedef VOID F_F15_OR_ES_IS_C6_SUPPORTED (
IN OUT BOOLEAN *IsEnabled,
IN AMD_CONFIG_PARAMS *StdHeader
);
/// Reference to a Method.
typedef F_F15_OR_ES_IS_C6_SUPPORTED *PF_F15_OR_ES_IS_C6_SUPPORTED;
/// Hook points in the C6 feature necessary for
/// providing support for pre-production CPUs.
typedef struct {
PF_F15_OR_ES_IS_C6_SUPPORTED F15OrIsC6SupportedHook; ///< C6 enablement override
} F15_OR_ES_C6_SUPPORT;
/**
* Workaround to avoid patch loading from causing NB cycles
*
* @param[in,out] StdHeader - Config handle for library and services.
* @param[in,out] SavedMsrValue - Saved a MSR value
*
*/
typedef VOID F_F15_OR_ES_AVOID_NB_CYCLES_START (
IN OUT AMD_CONFIG_PARAMS *StdHeader,
IN UINT64 *SavedMsrValue
);
/// Reference to a Method.
typedef F_F15_OR_ES_AVOID_NB_CYCLES_START *PF_F15_OR_ES_AVOID_NB_CYCLES_START;
/**
* Workaround to avoid patch loading from causing NB cycles
*
* @param[in,out] StdHeader - Config handle for library and services.
* @param[in] SavedMsrValue - Saved a MSR value
*
*
*/
typedef VOID F_F15_OR_ES_AVOID_NB_CYCLES_END (
IN OUT AMD_CONFIG_PARAMS *StdHeader,
IN UINT64 *SavedMsrValue
);
/// Reference to a Method.
typedef F_F15_OR_ES_AVOID_NB_CYCLES_END *PF_F15_OR_ES_AVOID_NB_CYCLES_END;
/**
* Workaround for Ax processors after patch is loaded.
*
* @param[in] StdHeader - Config handle for library and services.
* @param[in] IsPatchLoaded - Is patch loaded
*
*
*/
typedef VOID F_F15_OR_ES_AFTER_PATCH_LOADED (
IN OUT AMD_CONFIG_PARAMS *StdHeader,
IN BOOLEAN IsPatchLoaded
);
/// Reference to a Method.
typedef F_F15_OR_ES_AFTER_PATCH_LOADED *PF_F15_OR_ES_AFTER_PATCH_LOADED;
/**
* Update the CPU microcode.
*
* @param[in] StdHeader - Config handle for library and services.
*
* @retval TRUE - Patch Loaded Successfully.
* @retval FALSE - Patch Did Not Get Loaded.
*
*/
typedef BOOLEAN F_F15_OR_ES_LOAD_MCU_PATCH (
IN OUT AMD_CONFIG_PARAMS *StdHeader
);
/// Reference to a Method.
typedef F_F15_OR_ES_LOAD_MCU_PATCH *PF_F15_OR_ES_LOAD_MCU_PATCH;
/// Hook points in the Microcode Update feature necessary for
/// providing support for pre-production CPUs.
typedef struct {
PF_F15_OR_ES_AVOID_NB_CYCLES_START F15OrESAvoidNbCyclesStart; ///< Workaround to avoid patch loading from causing NB cycles
PF_F15_OR_ES_AVOID_NB_CYCLES_END F15OrESAvoidNbCyclesEnd; ///< Workaround to avoid patch loading from causing NB cycles
PF_F15_OR_ES_LOAD_MCU_PATCH F15OrUpdateMcuPatchHook; ///< Processor MCU Update override
PF_F15_OR_ES_AFTER_PATCH_LOADED F15OrESAfterPatchLoaded; ///< Workaround for Ax processors after patch is loaded
} F15_OR_ES_MCU_PATCH;
typedef BOOLEAN F_F15_TN_ES_LOAD_MCU_PATCH (
IN OUT AMD_CONFIG_PARAMS *StdHeader
);
/// Reference to a Method.
typedef F_F15_TN_ES_LOAD_MCU_PATCH *PF_F15_TN_ES_LOAD_MCU_PATCH;
/// Hook points in the Microcode Update feature necessary for
/// providing support for pre-production CPUs.
typedef struct {
PF_F15_TN_ES_LOAD_MCU_PATCH F15TnUpdateMcuPatchHook; ///< Processor MCU Update override
} F15_TN_ES_MCU_PATCH;
/*---------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*---------------------------------------------------------------------------------------
*/
#endif // _OPTION_FAMILY_15H_EARLY_SAMPLE_H_

80
src/vendorcode/amd/agesa/f15/Include/OptionGfxRecovery.h
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@ -1,80 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD GFX Recovery option API.
*
* Contains structures and values used to control the GfxRecovery option code.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: OPTION
*
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
#ifndef _OPTION_GFX_RECOVERY_H_
#define _OPTION_GFX_RECOVERY_H_
/*----------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*----------------------------------------------------------------------------------------
*/
typedef AGESA_STATUS OPTION_GFX_RECOVERY_FEATURE (
IN OUT AMD_CONFIG_PARAMS *StdHeader
);
#define GFX_RECOVERY_STRUCT_VERSION 0x01
/// The Option Configuration of GFX Recovery
typedef struct {
UINT16 OptGfxRecoveryVersion; ///< The version number of GFX Recovery
OPTION_GFX_RECOVERY_FEATURE *GfxRecoveryFeature; ///< The Option Feature of GFX Recovery
} OPTION_GFX_RECOVERY_CONFIGURATION;
/*----------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*----------------------------------------------------------------------------------------
*/
#endif // _OPTION_GFX_RECOVERY_H_

109
src/vendorcode/amd/agesa/f15/Include/OptionGnb.h
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@ -1,109 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD ALIB option API.
*
* Contains structures and values used to control the ALIB option code.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: OPTION
* @e \$Revision: 53099 $ @e \$Date: 2011-05-16 01:08:27 -0600 (Mon, 16 May 2011) $
*
*/
/*****************************************************************************
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef _OPTION_GNB_H_
#define _OPTION_GNB_H_
/*----------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*----------------------------------------------------------------------------------------
*/
typedef AGESA_STATUS OPTION_GNB_FEATURE (
IN AMD_CONFIG_PARAMS *StdHeader
);
/// The Option Configuration
typedef struct {
UINT64 Type; ///< Type
OPTION_GNB_FEATURE *GnbFeature; ///< The GNB Feature
} OPTION_GNB_CONFIGURATION;
/// The Build time options configuration
typedef struct {
BOOLEAN IgfxModeAsPcieEp; ///< Itegrated Gfx mode Pcie EP or Legacy
BOOLEAN LclkDeepSleepEn; ///< Default for LCLK deep sleep
BOOLEAN LclkDpmEn; ///< Default for LCLK DPM
BOOLEAN GmcPowerGateStutterOnly; ///< Force GMC power gate to stutter only
BOOLEAN SmuSclkClockGatingEnable; ///< Control SMU SCLK gating
BOOLEAN PcieAspmBlackListEnable; ///< Control Pcie Aspm Black List
BOOLEAN IvrsRelativeAddrNamesSupport; ///< Support for relative address names
BOOLEAN GnbLoadRealFuseTable; ///< Support for fuse table loading
UINT32 CfgGnbLinkReceiverDetectionPooling; ///< Receiver pooling detection time in us.
UINT32 CfgGnbLinkL0Pooling; ///< Pooling for link to get to L0 in us
UINT32 CfgGnbLinkGpioResetAssertionTime; ///< Gpio reset assertion time in us
UINT32 CfgGnbLinkResetToTrainingTime; ///< Time duration between deassert GPIO reset and release training in us
UINT8 CfgGnbTrainingAlgorithm; ///< distribution of training across interface calls
BOOLEAN CfgForceCableSafeOff; ///< Force cable safe off
BOOLEAN CfgOrbClockGatingEnable; ///< Control ORB clock gating
UINT8 CfgPciePowerGatingFlags; ///< Pcie Power gating flags
BOOLEAN CfgIocLclkClockGatingEnable; ///< Control IOC LCLK clock gating
BOOLEAN CfgIocSclkClockGatingEnable; ///< Control IOC SCLK clock gating
BOOLEAN CfgIommuL1ClockGatingEnable; ///< Control IOMMU L1 clock gating
BOOLEAN CfgIommuL2ClockGatingEnable; ///< Control IOMMU L2 clock gating
BOOLEAN CfgAltVddNb; ///< AltVDDNB support
BOOLEAN CfgBapmSupport; ///< BAPM support
BOOLEAN CfgUnusedSimdPowerGatingEnable; ///< Control unused SIMD power gate
BOOLEAN CfgUnusedRbPowerGatingEnable; ///< Control unused SIMD power gate
} GNB_BUILD_OPTIONS;
/*----------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*----------------------------------------------------------------------------------------
*/
#endif // _OPTION_GNB_H_

358
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@ -1,358 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Memory option API.
*
* Contains structures and values used to control the Memory option code.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: OPTION
* @e \$Revision: 55039 $ @e \$Date: 2011-06-15 23:31:36 -0600 (Wed, 15 Jun 2011) $
*
*/
/*****************************************************************************
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef _OPTION_MEMORY_H_
#define _OPTION_MEMORY_H_
/* Memory Includes */
#include "mm.h"
#include "mn.h"
#include "mt.h"
#include "ma.h"
#include "mp.h"
/*----------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
#define MAX_FF_TYPES 6 ///< Maximum number of DDR Form factors (UDIMMs, RDIMMMs, SODIMMS) supported
/*----------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*----------------------------------------------------------------------------------------
*/
/*
* STANDARD MEMORY FEATURE FUNCTION POINTER
*/
typedef BOOLEAN OPTION_MEM_FEATURE_NB (
IN OUT MEM_NB_BLOCK *NBPtr
);
typedef BOOLEAN MEM_TECH_FEAT (
IN OUT MEM_TECH_BLOCK *TechPtr
);
typedef UINT8 MEM_TABLE_FEAT (
IN OUT MEM_TABLE_ALIAS **MTPtr
);
#define MEM_FEAT_BLOCK_NB_STRUCT_VERSION 0x01
/**
* MEMORY FEATURE BLOCK - This structure serves as a vector table for standard
* memory feature implementation functions. It contains vectors for all of the
* features that are supported by the various Northbridge devices supported by
* AGESA.
*/
typedef struct _MEM_FEAT_BLOCK_NB {
UINT16 OptMemFeatVersion; ///< Version of memory feature block.
OPTION_MEM_FEATURE_NB *OnlineSpare; ///< Online spare support.
OPTION_MEM_FEATURE_NB *InterleaveBanks; ///< Bank (Chip select) interleaving support.
OPTION_MEM_FEATURE_NB *UndoInterleaveBanks; ///< Undo Bank (Chip Select) interleaving.
OPTION_MEM_FEATURE_NB *CheckInterleaveNodes; ///< Check for Node interleaving support.
OPTION_MEM_FEATURE_NB *InterleaveNodes; ///< Node interleaving support.
OPTION_MEM_FEATURE_NB *InterleaveChannels; ///< Channel interleaving support.
OPTION_MEM_FEATURE_NB *InterleaveRegion; ///< Interleave Region support.
OPTION_MEM_FEATURE_NB *CheckEcc; ///< Check for ECC support.
OPTION_MEM_FEATURE_NB *InitEcc; ///< ECC support.
OPTION_MEM_FEATURE_NB *Training; ///< Choose the type of training (Parallel, standard or hardcoded).
OPTION_MEM_FEATURE_NB *LvDdr3; ///< Low voltage DDR3 dimm support
OPTION_MEM_FEATURE_NB *OnDimmThermal; ///< On-Dimm thermal management
MEM_TECH_FEAT *DramInit; ///< Choose the type of Dram init (hardware based or software based).
OPTION_MEM_FEATURE_NB *ExcludeDIMM; ///< Exclude a dimm.
OPTION_MEM_FEATURE_NB *InitEarlySampleSupport; ///< Initialize early sample support.
OPTION_MEM_FEATURE_NB *InitCPG; ///< Continuous pattern generation.
OPTION_MEM_FEATURE_NB *InitHwRxEn; ///< Hardware Receiver Enable Training Initilization.
} MEM_FEAT_BLOCK_NB;
typedef AGESA_STATUS MEM_MAIN_FLOW_CONTROL (
IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr
);
typedef BOOLEAN OPTION_MEM_FEATURE_MAIN (
IN MEM_MAIN_DATA_BLOCK *MMPtr
);
typedef BOOLEAN MEM_NB_CONSTRUCTOR (
IN OUT MEM_NB_BLOCK *NBPtr,
IN OUT MEM_DATA_STRUCT *MemPtr,
IN MEM_FEAT_BLOCK_NB *FeatPtr,
IN MEM_SHARED_DATA *mmSharedPtr, ///< Pointer to Memory scratchpad
IN UINT8 NodeID
);
typedef BOOLEAN MEM_TECH_CONSTRUCTOR (
IN OUT MEM_TECH_BLOCK *TechPtr,
IN OUT MEM_NB_BLOCK *NBPtr
);
typedef VOID MEM_INITIALIZER (
IN OUT MEM_DATA_STRUCT *MemPtr
);
typedef AGESA_STATUS MEM_PLATFORM_CFG (
IN struct _MEM_DATA_STRUCT *MemData,
IN UINT8 SocketID,
IN CH_DEF_STRUCT *CurrentChannel
);
typedef BOOLEAN MEM_IDENDIMM_CONSTRUCTOR (
IN OUT MEM_NB_BLOCK *NBPtr,
IN OUT MEM_DATA_STRUCT *MemPtr,
IN UINT8 NodeID
);
typedef VOID MEM_TECH_TRAINING_FEAT (
IN OUT MEM_TECH_BLOCK *TechPtr,
IN UINT8 Pass
);
typedef BOOLEAN MEM_RESUME_CONSTRUCTOR (
IN OUT VOID *S3NBPtr,
IN OUT MEM_DATA_STRUCT *MemPtr,
IN UINT8 NodeID
);
typedef AGESA_STATUS MEM_PLAT_SPEC_CFG (
IN struct _MEM_DATA_STRUCT *MemData,
IN OUT CH_DEF_STRUCT *CurrentChannel,
IN OUT MEM_PS_BLOCK *PsPtr
);
typedef AGESA_STATUS MEM_FLOW_CFG (
IN OUT MEM_MAIN_DATA_BLOCK *MemData
);
#define MEM_FEAT_BLOCK_MAIN_STRUCT_VERSION 0x01
/**
* MAIN FEATURE BLOCK - This structure serves as vector table for memory features
* that shared between all northbridge devices.
*/
typedef struct _MEM_FEAT_BLOCK_MAIN {
UINT16 OptMemFeatVersion; ///< Version of main feature block.
OPTION_MEM_FEATURE_MAIN *Training; ///< Training features.
OPTION_MEM_FEATURE_MAIN *ExcludeDIMM; ///< Exclude a dimm.
OPTION_MEM_FEATURE_MAIN *OnlineSpare; ///< On-line spare.
OPTION_MEM_FEATURE_MAIN *InterleaveNodes; ///< Node interleave.
OPTION_MEM_FEATURE_MAIN *InitEcc; ///< Initialize ECC on all nodes if they all support it.
OPTION_MEM_FEATURE_MAIN *MemClr; ///< Memory Clear.
OPTION_MEM_FEATURE_MAIN *MemDmi; ///< Memory DMI Support.
OPTION_MEM_FEATURE_MAIN *LvDDR3; ///< Low voltage DDR3 support.
OPTION_MEM_FEATURE_MAIN *UmaAllocation; ///< Uma Allocation.
OPTION_MEM_FEATURE_MAIN *MemSave; ///< Memory Context Save
OPTION_MEM_FEATURE_MAIN *MemRestore; ///< Memory Context Restore
} MEM_FEAT_BLOCK_MAIN;
#define MEM_NB_SUPPORT_STRUCT_VERSION 0x01
#define MEM_TECH_FEAT_BLOCK_STRUCT_VERSION 0x01
#define MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION 0x01
#define MEM_TECH_LRDIMM_STRUCT_VERSION 0x01
/**
* MEMORY TECHNOLOGY FEATURE BLOCK - This structure serves as a vector table for standard
* memory feature implementation functions. It contains vectors for all of the
* features that are supported by the various Technology features supported by
* AGESA.
*/
typedef struct _MEM_TECH_FEAT_BLOCK {
UINT16 OptMemTechFeatVersion; ///< Version of memory Tech feature block.
MEM_TECH_FEAT *EnterHardwareTraining; ///<Enter HW WL Training
MEM_TECH_FEAT *SwWLTraining; ///<SW Write Levelization training
MEM_TECH_FEAT *HwBasedWLTrainingPart1; ///<HW based write levelization Training Part 1
MEM_TECH_FEAT *HwBasedDQSReceiverEnableTrainingPart1; ///<HW based DQS receiver Enabled Training Part 1
MEM_TECH_FEAT *HwBasedWLTrainingPart2; ///<HW based write levelization Training Part 2
MEM_TECH_FEAT *HwBasedDQSReceiverEnableTrainingPart2; ///<HW based DQS receiver Enabled Training Part 2
MEM_TECH_FEAT *TrainExitHwTrn; ///<Exit HW WL Training
MEM_TECH_FEAT *NonOptimizedSWDQSRecEnTrainingPart1; ///< Non-Optimized Software based receiver Enable Training part 1
MEM_TECH_FEAT *OptimizedSwDqsRecEnTrainingPart1; ///< Optimized Software based receiver Enable Training part 1
MEM_TECH_FEAT *NonOptimizedSRdWrPosTraining; ///< Non-Optimized Rd Wr Position training
MEM_TECH_FEAT *OptimizedSRdWrPosTraining; ///< Optimized Rd Wr Position training
MEM_TECH_FEAT *MaxRdLatencyTraining; ///< MaxReadLatency Training
MEM_TECH_FEAT *RdPosTraining; ///< HW Rx En Seed Training
MEM_TECH_FEAT *RdDqs__Training; ///< Read DQS Training
} MEM_TECH_FEAT_BLOCK;
/**
* MEMORY TECHNOLOGY LRDIMM BLOCK - This structure serves as a vector table for standard
* memory feature implementation functions. It contains vectors for all of the
* features that are supported by the various LRDIMM features supported by
* AGESA.
*/
typedef struct _MEM_TECH_LRDIMM {
UINT16 OptMemTechLrdimmVersion; ///< Version of memory Tech feature block.
MEM_TECH_FEAT *MemTInitializeLrdimm; ///< LRDIMM initialization
} MEM_TECH_LRDIMM;
/**
* MEMORY NORTHBRIDGE SUPPORT STRUCT - This structure groups the Northbridge dependent
* options together in a list to provide a single access point for all code to use
* and to ensure that everything corresponding to the same NB type is grouped together.
*
* The Technology Block pointers are not included in this structure because DRAM technology
* needs to be decoupled from the northbridge type.
*
*/
typedef struct _MEM_NB_SUPPORT {
UINT16 MemNBSupportVersion; ///< Version of northbridge support.
MEM_NB_CONSTRUCTOR *MemConstructNBBlock; ///< NorthBridge block constructor.
MEM_INITIALIZER *MemNInitDefaults; ///< Default value initialization for MEM_DATA_STRUCT.
MEM_FEAT_BLOCK_NB *MemFeatBlock; ///< Memory feature block.
MEM_RESUME_CONSTRUCTOR *MemS3ResumeConstructNBBlock; ///< S3 memory initialization northbridge block constructor.
MEM_IDENDIMM_CONSTRUCTOR *MemIdentifyDimmConstruct; ///< Constructor for address to dimm identification.
} MEM_NB_SUPPORT;
/*
* MEMORY Non-Training FEATURES - This structure serves as a vector table for standard
* memory non-training feature implementation functions. It contains vectors for all of the
* features that are supported by the various Technology devices supported by
* AGESA.
*/
/**
* MAIN TRAINING SEQUENCE LIST - This structure serves as vector table for memory features
* that shared between all northbridge devices.
*/
typedef struct _MEM_FEAT_TRAIN_SEQ {
UINT16 OptMemTrainingSequenceListVersion; ///< Version of main feature block.
OPTION_MEM_FEATURE_NB *TrainingSequence; ///< Training Sequence function.
OPTION_MEM_FEATURE_NB *TrainingSequenceEnabled; ///< Enable function.
MEM_TECH_FEAT_BLOCK *MemTechFeatBlock; ///< Memory feature block.
} MEM_FEAT_TRAIN_SEQ;
/**
* PLATFORM SPECIFIC CONFIGURATION BLOCK - This structure groups various PSC table
* entries which are used by PSC engine
*/
typedef struct _MEM_PSC_TABLE_BLOCK {
PSC_TBL_ENTRY **TblEntryOfMaxFreq; ///< Table entry of MaxFreq.
PSC_TBL_ENTRY **TblEntryOfDramTerm; ///< Table entry of Dram Term.
PSC_TBL_ENTRY **TblEntryOfODTPattern; ///< Table entry of ODT Pattern.
PSC_TBL_ENTRY **TblEntryOfSAO; ///< Table entry of Slow access mode, AddrTmg and ODC..
PSC_TBL_ENTRY **TblEntryOfMR0WR; ///< Table entry of MR0[WR].
PSC_TBL_ENTRY **TblEntryOfMR0CL; ///< Table entry of MR0[CL].
PSC_TBL_ENTRY **TblEntryOfRC2IBT; ///< Table entry of RC2 IBT.
PSC_TBL_ENTRY **TblEntryOfRC10OpSpeed; ///< Table entry of RC10[operating speed].
PSC_TBL_ENTRY **TblEntryOfLRIBT;///< Table entry of LRDIMM IBT
PSC_TBL_ENTRY **TblEntryOfLRNPR; ///< Table entry of LRDIMM F0RC13[NumPhysicalRanks].
PSC_TBL_ENTRY **TblEntryOfLRNLR; ///< Table entry of LRDIMM F0RC13[NumLogicalRanks].
PSC_TBL_ENTRY **TblEntryOfGen; ///< Table entry of CLKDis map and CKE, ODT as well as ChipSel tri-state map.
PSC_TBL_ENTRY **TblEntryOfS__; ///< Table entry of training configs
PSC_TBL_ENTRY **TblEntryOfWLSeed; ///< Table entry of WL seed
PSC_TBL_ENTRY **TblEntryOfHWRxENSeed; ///< Table entry of HW RxEN seed
} MEM_PSC_TABLE_BLOCK;
typedef BOOLEAN MEM_PSC_FLOW (
IN OUT MEM_NB_BLOCK *NBPtr,
IN MEM_PSC_TABLE_BLOCK *EntryOfTables
);
/**
* PLATFORM SPECIFIC CONFIGURATION FLOW BLOCK - Pointers to the sub-engines of platform
* specific configuration.
*/
typedef struct _MEM_PSC_FLOW_BLOCK {
MEM_PSC_TABLE_BLOCK *EntryOfTables; ///<Entry of NB specific MEM_PSC_TABLE_BLOCK
MEM_PSC_FLOW *MaxFrequency; ///< Sub-engine which performs "Max Frequency" value extraction.
MEM_PSC_FLOW *DramTerm; ///< Sub-engine which performs "Dram Term" value extraction.
MEM_PSC_FLOW *ODTPattern; ///< Sub-engine which performs "ODT Pattern" value extraction.
MEM_PSC_FLOW *SAO; ///< Sub-engine which performs "Slow access mode, AddrTmg and ODC" value extraction.
MEM_PSC_FLOW *MR0WrCL; ///< Sub-engine which performs "MR0[WR] and MR0[CL]" value extraction.
MEM_PSC_FLOW *RC2IBT; ///< Sub-engine "RC2 IBT" value extraction.
MEM_PSC_FLOW *RC10OpSpeed; ///< Sub-engine "RC10[operating speed]" value extraction.
MEM_PSC_FLOW *LRIBT; ///< Sub-engine "LRDIMM IBT" value extraction.
MEM_PSC_FLOW *LRNPR; ///< Sub-engine "LRDIMM F0RC13[NumPhysicalRanks]" value extraction.
MEM_PSC_FLOW *LRNLR; ///< Sub-engine "LRDIMM F0RC13[NumLogicalRanks]" value extraction.
MEM_PSC_FLOW *S__; ///< Sub-engine which performs training configuration checking
MEM_PSC_FLOW *TrainingSeedVal; ///< Sub-engine for WL and HW RxEn pass1 seed value extraction
} MEM_PSC_FLOW_BLOCK;
/*----------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*----------------------------------------------------------------------------------------
*/
/* Feature Default Return */
BOOLEAN MemFDefRet (
IN OUT MEM_NB_BLOCK *NBPtr
);
BOOLEAN MemMDefRet (
IN MEM_MAIN_DATA_BLOCK *MMPtr
);
BOOLEAN MemMDefRetFalse (
IN MEM_MAIN_DATA_BLOCK *MMPtr
);
/* Table Feature Default Return */
UINT8 MemFTableDefRet (
IN OUT MEM_TABLE_ALIAS **MTPtr
);
/* S3 Feature Default Return */
BOOLEAN MemFS3DefConstructorRet (
IN OUT VOID *S3NBPtr,
IN OUT MEM_DATA_STRUCT *MemPtr,
IN UINT8 NodeID
);
BOOLEAN MemNIdentifyDimmConstructorRetDef (
IN OUT MEM_NB_BLOCK *NBPtr,
IN OUT MEM_DATA_STRUCT *MemPtr,
IN UINT8 NodeID
);
BOOLEAN
MemProcessConditionalOverrides (
IN PSO_TABLE *PlatformMemoryConfiguration,
IN OUT MEM_NB_BLOCK *NBPtr,
IN UINT8 PsoAction,
IN UINT8 Dimm
);
#endif // _OPTION_MEMORY_H_

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src/vendorcode/amd/agesa/f15/Include/OptionMultiSocket.h
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@ -1,214 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Multi-socket option API.
*
* Contains structures and values used to control the multi-socket option code.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: OPTION
* @e \$Revision: 51891 $ @e \$Date: 2011-04-28 12:39:55 -0600 (Thu, 28 Apr 2011) $
*
*/
/*****************************************************************************
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef _OPTION_MULTISOCKET_H_
#define _OPTION_MULTISOCKET_H_
/*----------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*----------------------------------------------------------------------------------------
*/
/**
* This function loops through all possible socket locations, gathering the number
* of power management steps each populated socket requires, and returns the
* highest number.
*
* @param[out] NumSystemSteps Maximum number of system steps required
* @param[in] StdHeader Config handle for library and services
*
*/
typedef VOID OPTION_MULTISOCKET_PM_STEPS (
OUT UINT8 *NumSystemSteps,
IN AMD_CONFIG_PARAMS *StdHeader
);
/**
* This function loops through all possible socket locations, starting core 0 of
* each populated socket to perform the passed in AP_TASK. After starting all
* other core 0s, the BSC will perform the AP_TASK as well. This must be run by
* the system BSC only.
*
* @param[in] TaskPtr Function descriptor
* @param[in] StdHeader Config handle for library and services
* @param[in] ConfigParams AMD entry point's CPU parameter structure
*
*/
typedef VOID OPTION_MULTISOCKET_PM_CORE0_TASK (
IN VOID *TaskPtr,
IN AMD_CONFIG_PARAMS *StdHeader,
IN VOID *ConfigParams
);
/**
* This function loops through all possible socket locations, comparing the
* maximum NB frequencies to determine the slowest. This function also
* determines if all coherent NB frequencies are equivalent.
*
* @param[in] NbPstate NB P-state number to check (0 = fastest)
* @param[in] PlatformConfig Platform profile/build option config structure.
* @param[out] SystemNbCofNumerator NB frequency numerator for the system in MHz
* @param[out] SystemNbCofDenominator NB frequency denominator for the system
* @param[out] SystemNbCofsMatch Whether or not all NB frequencies are equivalent
* @param[out] NbPstateIsEnabledOnAllCPUs Whether or not NbPstate is valid on all CPUs
* @param[in] StdHeader Config handle for library and services
*
* @retval TRUE At least one processor has NbPstate enabled.
* @retval FALSE NbPstate is disabled on all CPUs
*/
typedef BOOLEAN OPTION_MULTISOCKET_PM_NB_COF (
IN UINT32 NbPstate,
IN PLATFORM_CONFIGURATION *PlatformConfig,
OUT UINT32 *SystemNbCofNumerator,
OUT UINT32 *SystemNbCofDenominator,
OUT BOOLEAN *SystemNbCofsMatch,
OUT BOOLEAN *NbPstateIsEnabledOnAllCPUs,
IN AMD_CONFIG_PARAMS *StdHeader
);
/**
* This function loops through all possible socket locations, checking whether
* any populated sockets require NB COF VID programming.
*
* @param[in] StdHeader Config handle for library and services
*
*/
typedef BOOLEAN OPTION_MULTISOCKET_PM_NB_COF_UPDATE (
IN AMD_CONFIG_PARAMS *StdHeader
);
/**
* This function loops through all possible socket locations, collecting any
* power management initialization errors that may have occurred. These errors
* are transferred from the core 0s of the socket in which the errors occurred
* to the BSC's heap. The BSC's heap is then searched for the most severe error
* that occurred, and returns it. This function must be called by the BSC only.
*
* @param[in] StdHeader Config handle for library and services
*
*/
typedef AGESA_STATUS OPTION_MULTISOCKET_PM_GET_EVENTS (
IN AMD_CONFIG_PARAMS *StdHeader
);
/**
* This function loops through all possible socket locations and Nb Pstates,
* comparing the NB frequencies to determine the slowest NB P0 and NB Pmin in
* the system.
*
* @param[in] PlatformConfig Platform profile/build option config structure.
* @param[out] MinSysNbFreq NB frequency numerator for the system in MHz
* @param[out] MinP0NbFreq NB frequency numerator for P0 in MHz
* @param[in] StdHeader Config handle for library and services
*/
typedef VOID OPTION_MULTISOCKET_PM_NB_MIN_COF (
IN PLATFORM_CONFIGURATION *PlatformConfig,
OUT UINT32 *MinSysNbFreq,
OUT UINT32 *MinP0NbFreq,
IN AMD_CONFIG_PARAMS *StdHeader
);
/**
* This function returns the current running core's PCI Config Space address.
*
* @param[out] PciAddress The Processor's PCI Config Space address (Function 0, Register 0)
* @param[in] StdHeader Header for library and services.
*/
typedef BOOLEAN OPTION_MULTISOCKET_GET_PCI_ADDRESS (
OUT PCI_ADDR *PciAddress,
IN AMD_CONFIG_PARAMS *StdHeader
);
/**
* This function writes to all nodes on the executing core's socket.
*
* @param[in] PciAddress The Function and Register to update
* @param[in] Mask The bitwise AND mask to apply to the current register value
* @param[in] Data The bitwise OR mask to apply to the current register value
* @param[in] StdHeader Header for library and services.
*
*/
typedef VOID OPTION_MULTISOCKET_MODIFY_CURR_SOCKET_PCI (
IN PCI_ADDR *PciAddress,
IN UINT32 Mask,
IN UINT32 Data,
IN AMD_CONFIG_PARAMS *StdHeader
);
#define MULTISOCKET_STRUCT_VERSION 0x01
/**
* Provide build configuration of cpu multi-socket or single socket support.
*
*/
typedef struct {
UINT16 OptMultiSocketVersion; ///< Table version
OPTION_MULTISOCKET_PM_STEPS *GetNumberOfSystemPmSteps; ///< Method: Get number of power mgt tasks
OPTION_MULTISOCKET_PM_CORE0_TASK *BscRunCodeOnAllSystemCore0s; ///< Method: Perform tasks on Core 0 of each processor
OPTION_MULTISOCKET_PM_NB_COF *GetSystemNbPstateSettings; ///< Method: Find the Northbridge frequency for the specified Nb Pstate in the system.
OPTION_MULTISOCKET_PM_NB_COF_UPDATE *GetSystemNbCofVidUpdate; ///< Method: Determine if any Northbridges in the system need to update their COF/VID.
OPTION_MULTISOCKET_PM_GET_EVENTS *BscRetrievePmEarlyInitErrors; ///< Method: Gathers error information from all Core 0s.
OPTION_MULTISOCKET_PM_NB_MIN_COF *GetMinNbCof; ///< Method: Get the minimum system and minimum P0 Northbridge frequency.
OPTION_MULTISOCKET_GET_PCI_ADDRESS *GetCurrPciAddr; ///< Method: Get PCI Config Space Address for the current running core.
OPTION_MULTISOCKET_MODIFY_CURR_SOCKET_PCI *ModifyCurrSocketPci; ///< Method: Writes to all nodes on the executing core's socket.
} OPTION_MULTISOCKET_CONFIGURATION;
/*----------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*----------------------------------------------------------------------------------------
*/
#endif // _OPTION_MULTISOCKET_H_

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/* $NoKeywords:$ */
/**
* @file
*
* AMD ACPI PState option API.
*
* Contains structures and values used to control the PStates option code.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: OPTION
*
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
#ifndef _OPTION_PSTATE_H_
#define _OPTION_PSTATE_H_
#include "cpuPstateTables.h"
/*----------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*----------------------------------------------------------------------------------------
*/
typedef AGESA_STATUS OPTION_SSDT_FEATURE (
IN AMD_CONFIG_PARAMS *StdHeader,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN OUT VOID **AcpiPstatePtr
);
typedef UINT32 OPTION_ACPI_FEATURE (
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN PSTATE_LEVELING *PStateLevelingBuffer,
IN OUT VOID **AcpiPStatePtr,
IN UINT8 LocalApicId,
IN AMD_CONFIG_PARAMS *StdHeader
);
typedef AGESA_STATUS OPTION_PSTATE_GATHER (
IN AMD_CONFIG_PARAMS *StdHeader,
IN OUT S_CPU_AMD_PSTATE *PStateStrucPtr
);
typedef AGESA_STATUS OPTION_PSTATE_LEVELING (
IN OUT S_CPU_AMD_PSTATE *PStateStrucPtr,
IN AMD_CONFIG_PARAMS *StdHeader
);
#define PSTATE_STRUCT_VERSION 0x01
/// Indirection vectors for POST/PEI PState code
typedef struct {
UINT16 OptPstateVersion; ///< revision of this structure
OPTION_PSTATE_GATHER *PstateGather; ///< vector for data gathering routine
OPTION_PSTATE_LEVELING *PstateLeveling; ///< vector for leveling routine
} OPTION_PSTATE_POST_CONFIGURATION;
/// Indirection vectors for LATE/DXE PState code
typedef struct {
UINT16 OptPstateVersion; ///< revision of this structure
OPTION_SSDT_FEATURE *SsdtFeature; ///< vector for routine to generate SSDT
OPTION_ACPI_FEATURE *PstateFeature; ///< vector for routine to generate ACPI PState Objects
OPTION_ACPI_FEATURE *CstateFeature; ///< vector for routine to generate ACPI CState Objects
BOOLEAN CfgPstatePpc; ///< boolean for creating _PPC method
BOOLEAN CfgPstatePct; ///< boolean for creating _PCT method
BOOLEAN CfgPstatePsd; ///< boolean for creating _PSD method
BOOLEAN CfgPstatePss; ///< boolean for creating _PSS method
BOOLEAN CfgPstateXpss; ///< boolean for creating _XPSS method
} OPTION_PSTATE_LATE_CONFIGURATION;
/*----------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*----------------------------------------------------------------------------------------
*/
#endif // _OPTION_PSTATE_H_

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/* $NoKeywords:$ */
/**
* @file
*
* AMD SLIT option API.
*
* Contains structures and values used to control the SLIT option code.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: OPTION
*
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
#ifndef _OPTION_SLIT_H_
#define _OPTION_SLIT_H_
/*----------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*----------------------------------------------------------------------------------------
*/
/**
* Create the ACPI System Locality Distance Information Table.
*
*/
typedef AGESA_STATUS OPTION_SLIT_FEATURE (
IN OUT AMD_CONFIG_PARAMS *StdHeader,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN OUT VOID **SlitPtr
);
/**
* Clean up DRAM used during SLIT creation.
*
*/
typedef AGESA_STATUS OPTION_SLIT_RELEASE_BUFFER (
IN OUT AMD_CONFIG_PARAMS *StdHeader
);
#define SLIT_STRUCT_VERSION 0x01
/// The Option Configuration of SLIT
typedef struct {
UINT16 OptSlitVersion; ///< The version number of SLIT
OPTION_SLIT_FEATURE *SlitFeature; ///< The Option Feature of SLIT
OPTION_SLIT_RELEASE_BUFFER *SlitReleaseBuffer; ///< Release buffer
} OPTION_SLIT_CONFIGURATION;
/*----------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*----------------------------------------------------------------------------------------
*/
#endif // _OPTION_SLIT_H_

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@ -1,81 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD SRAT option API.
*
* Contains structures and values used to control the SRAT option code.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: OPTION
*
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
#ifndef _OPTION_SRAT_H_
#define _OPTION_SRAT_H_
/*----------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*----------------------------------------------------------------------------------------
*/
typedef AGESA_STATUS OPTION_SRAT_FEATURE (
IN OUT AMD_CONFIG_PARAMS *StdHeader,
IN OUT VOID **SratPtr
);
#define SRAT_STRUCT_VERSION 0x01
/// The Option Configuration of SRAT
typedef struct {
UINT16 OptSratVersion; ///< The version number of SRAT
OPTION_SRAT_FEATURE *SratFeature; ///< The Option Feature of SRAT
} OPTION_SRAT_CONFIGURATION;
/*----------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*----------------------------------------------------------------------------------------
*/
#endif // _OPTION_SRAT_H_

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/* $NoKeywords:$ */
/**
* @file
*
* AMD WHEA option API.
*
* Contains structures and values used to control the WHEA option code.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: OPTION
*
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
#ifndef _OPTION_WHEA_H_
#define _OPTION_WHEA_H_
/*----------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*----------------------------------------------------------------------------------------
*/
typedef AGESA_STATUS OPTION_WHEA_FEATURE (
IN OUT AMD_CONFIG_PARAMS *StdHeader,
IN OUT VOID **WheaMcePtr,
IN OUT VOID **WheaCmcPtr
);
#define WHEA_STRUCT_VERSION 0x01
/// The Option Configuration of WHEA
typedef struct {
UINT16 OptWheaVersion; ///< The version number of WHEA
OPTION_WHEA_FEATURE *WheaFeature; ///< The Option Feature of WHEA
} OPTION_WHEA_CONFIGURATION;
/*----------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*----------------------------------------------------------------------------------------
*/
#endif // _OPTION_WHEA_H_

69
src/vendorcode/amd/agesa/f15/Include/Options.h
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@ -1,69 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AGESA options structures
*
* Contains options control structures for the AGESA build options
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Core
* @e \$Revision: 53142 $ @e \$Date: 2011-05-16 12:01:19 -0600 (Mon, 16 May 2011) $
*/
/*****************************************************************************
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
***************************************************************************/
#ifndef _OPTIONS_H_
#define _OPTIONS_H_
/**
* Provide topology limits for loops and runtime, based on supported families.
*/
typedef struct {
UINT32 PlatformNumberOfSockets; ///< The limit to the number of processors based on
///< supported families and other build options.
UINT32 PlatformNumberOfModules; ///< The limit to the number of modules in a processor, based
///< on supported families.
} OPTIONS_CONFIG_TOPOLOGY;
/**
* Dispatch Table.
*
* The push high dispatcher uses this table to find what entries are currently in the build image.
*/
typedef struct {
UINT32 FunctionId; ///< The function id specified.
IMAGE_ENTRY EntryPoint; ///< The corresponding entry point to call.
} DISPATCH_TABLE;
#endif // _OPTIONS_H_

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/* $NoKeywords:$ */
/**
* @file
*
* AMD HyperTransport option API.
*
* Contains option pre-compile logic. This file is used by the options
* installer and internally by the HT code initializers.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: OPTION
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $
*
*/
/*****************************************************************************
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef _OPTION_HT_H_
#define _OPTION_HT_H_
/*----------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*----------------------------------------------------------------------------------------
*/
/**
* Provide HT build option results
*/
typedef struct {
CONST BOOLEAN IsUsingRecoveryHt; ///< Manual BUID Swap List processing should assume that HT Recovery was used.
CONST BOOLEAN IsSetHtCrcFlood; ///< Enable setting of HT CRC Flood.
///< Build-time only customizable - @BldCfgItem{BLDCFG_SET_HTCRC_SYNC_FLOOD}
CONST BOOLEAN IsUsingUnitIdClumping; ///< Enable automatically HT Spec compliant Unit Id Clumping.
///< Build-time only customizable - @BldCfgItem{BLDCFG_USE_UNIT_ID_CLUMPING}
CONST AMD_HT_INTERFACE *HtOptionPlatformDefaults; ///< A set of build time options for HT constructor.
CONST VOID *HtOptionInternalInterface; ///< Use this internal interface initializer.
CONST VOID *HtOptionInternalFeatures; ///< Use this internal feature set initializer.
CONST VOID *HtOptionFamilyNorthbridgeList; ///< Use this list of northbridge initializers.
CONST UINT8 *CONST *HtOptionBuiltinTopologies; ///< Use this list of built-in topologies.
} OPTION_HT_CONFIGURATION;
typedef AGESA_STATUS
F_OPTION_HT_INIT_RESET (
IN AMD_CONFIG_PARAMS *StdHeader,
IN AMD_HT_RESET_INTERFACE *AmdHtResetInterface
);
typedef F_OPTION_HT_INIT_RESET *PF_OPTION_HT_INIT_RESET;
typedef AGESA_STATUS
F_OPTION_HT_RESET_CONSTRUCTOR (
IN AMD_CONFIG_PARAMS *StdHeader,
IN AMD_HT_RESET_INTERFACE *AmdHtResetInterface
);
typedef F_OPTION_HT_RESET_CONSTRUCTOR *PF_OPTION_HT_RESET_CONSTRUCTOR;
/**
* Provide HT reset initialization build option results
*/
typedef struct {
PF_OPTION_HT_INIT_RESET HtInitReset; ///< Method: HT reset initialization.
PF_OPTION_HT_RESET_CONSTRUCTOR HtResetConstructor; ///< Method: HT reset initialization.
} OPTION_HT_INIT_RESET;
/*----------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*----------------------------------------------------------------------------------------
*/
#endif // _OPTION_HT_H_

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src/vendorcode/amd/agesa/f15/Include/OptionsPage.h
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/* $NoKeywords:$ */
/**
* @file
*
* Create outline and references for Build Configuration and Options Component mainpage documentation.
*
* Design guides, maintenance guides, and general documentation, are
* collected using this file onto the documentation mainpage.
* This file contains doxygen comment blocks, only.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Documentation
* @e \$Revision: 52274 $ @e \$Date: 2011-05-04 01:00:15 -0600 (Wed, 04 May 2011) $
*
*/
/*
******************************************************************************
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/**
* @page optionmain Build Configuration and Options Documentation
*
* Additional documentation for the Build Configuration and Options component consists of
*
* - Introduction and Overview to Build Options
* - @subpage platforminstall "Platform Build Options"
* - @subpage bldcfg "Build Configuration Item Cross Reference"
* - @subpage examplecustomizations "Customization Examples"
* - Maintenance Guides:
* - For debug of the Options system, use compiler options
* @n <tt> /P /EP /C /FAs </tt> @n
* PreProcessor output is produced in an .i file in the directory where the project
* file is located.
* - Design Guides:
* - add here >>>
*
*/
/**
* @page platforminstall Platform Build Options.
*
* Build options are boolean constants. The purpose of build options is to remove code
* from the build to reduce the overall code size present in the ROM image. Unless
* otherwise specified, the default action is to include all options. If a build option is
* not specifically listed as disabled, then it is included into the build.
*
* The documented build options are imported from a user controlled file for
* processing. The build options for all platform solutions are listed below:
*
* @anchor BLDOPT_REMOVE_UDIMMS_SUPPORT
* @li @e BLDOPT_REMOVE_UDIMMS_SUPPORT @n
* If unbuffered DIMMs are NOT expected to be required in the system, the code that
* handles unbuffered DIMMs can be removed from the build.
*
* @anchor BLDOPT_REMOVE_RDIMMS_SUPPORT
* @li @e BLDOPT_REMOVE_RDIMMS_SUPPORT @n
* If registered DIMMs are NOT expected to be required in the system, the code
* that handles registered DIMMs can be removed from the build.
*
* @anchor BLDOPT_REMOVE_LRDIMMS_SUPPORT
* @li @e BLDOPT_REMOVE_LRDIMMS_SUPPORT @n
* If Load Reduced DIMMs are NOT expected to be required in the system, the code
* that handles Load Reduced DIMMs can be removed from the build.
*
* @note The above three options operate independently from each other; however, at
* least one of the unbuffered , registered or load reduced DIMM options must be present in the build.
*
* @anchor BLDOPT_REMOVE_ECC_SUPPORT
* @li @e BLDOPT_REMOVE_ECC_SUPPORT @n
* Use this option to remove the code for Error Checking & Correction.
*
* @anchor BLDOPT_REMOVE_BANK_INTERLEAVE
* @li @e BLDOPT_REMOVE_BANK_INTERLEAVE @n
* Interleaving is a mechanism to do performance fine tuning. This option
* interleaves memory between banks on a DIMM.
*
* @anchor BLDOPT_REMOVE_DCT_INTERLEAVE
* @li @e BLDOPT_REMOVE_DCT_INTERLEAVE @n
* Interleaving is a mechanism to do performance fine tuning. This option
* interleaves memory from two DRAM controllers.
*
* @anchor BLDOPT_REMOVE_NODE_INTERLEAVE
* @li @e BLDOPT_REMOVE_NODE_INTERLEAVE @n
* Interleaving is a mechanism to do performance fine tuning. This option
* interleaves memory from two HyperTransport nodes.
*
* @anchor BLDOPT_REMOVE_PARALLEL_TRAINING
* @li @e BLDOPT_REMOVE_PARALLEL_TRAINING @n
* For multi-socket systems, training memory in parallel can reduce the time
* needed to boot.
*
* @anchor BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT
* @li @e BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT @n
* Online Spare support is removed by this option.
*
* @anchor BLDOPT_REMOVE_MULTISOCKET_SUPPORT
* @li @e BLDOPT_REMOVE_MULTISOCKET_SUPPORT @n
* Many systems use only a single socket and may benefit in code space to remove
* this code. However, certain processors have multiple HyperTransport nodes
* within a single socket. For these processors, the multi-node support is
* required and this option has no effect.
*
* @anchor BLDOPT_REMOVE_ACPI_PSTATES
* @li @e BLDOPT_REMOVE_ACPI_PSTATES @n
* This option removes the code that generates the ACPI tables used in power
* management.
*
* @anchor BLDCFG_PSTATE_HPC_MODE
* @li @e BLDCFG_PSTATE_HPC_MODE @n
* This option enables PStates high performance computing mode (HPC mode)
*
* @anchor BLDOPT_REMOVE_SRAT
* @li @e BLDOPT_REMOVE_SRAT @n
* This option removes the code that generates the SRAT tables used in performance
* tuning.
*
* @anchor BLDOPT_REMOVE_SLIT
* @li @e BLDOPT_REMOVE_SLIT @n
* This option removes the code that generates the SLIT tables used in performance
* tuning.
*
* @anchor BLDOPT_REMOVE_WHEA
* @li @e BLDOPT_REMOVE_WHEA @n
* This option removes the code that generates the WHEA tables used in error
* handling and reporting.
*
* @anchor BLDOPT_REMOVE_DMI
* @li @e BLDOPT_REMOVE_DMI @n
* This option removes the code that generates the DMI tables used in system
* management.
*
* @anchor BLDOPT_REMOVE_DQS_TRAINING
* @li @e BLDOPT_REMOVE_DQS_TRAINING @n
* This option removes the code used in memory performance tuning.
*
* @anchor BLDOPT_REMOVE_EARLY_SAMPLES
* @li @e BLDOPT_REMOVE_EARLY_SAMPLES @n
* Special support for Early Samples is included. Default setting is FALSE.
*
* @anchor BLDOPT_REMOVE_HT_ASSIST
* @li @e BLDOPT_REMOVE_HT_ASSIST @n
* This option removes the code which implements the HT Assist feature.
*
* @anchor BLDOPT_REMOVE_ATM_MODE
* @li @e BLDOPT_REMOVE_ATM_MODE @n
* This option removes the code which implements the ATM feature.
*
* @anchor BLDOPT_REMOVE_MSG_BASED_C1E
* @li @e BLDOPT_REMOVE_MSG_BASED_C1E @n
* This option removes the code which implements the Message Based C1e feature.
*
* @anchor BLDOPT_REMOVE_C6_STATE
* @li @e BLDOPT_REMOVE_C6_STATE @n
* This option removes the code which implements the C6 C-state feature.
*
* @anchor BLDOPT_REMOVE_MEM_RESTORE_SUPPORT
* @li @e BLDOPT_REMOVE_MEM_RESTORE_SUPPORT @n
* This option removes the memory context restore feature.
*
* @anchor BLDOPT_REMOVE_FAMILY_10_SUPPORT
* @li @e BLDOPT_REMOVE_FAMILY_10_SUPPORT @n
* If the package contains support for family 10h processors, remove that support.
*
* @anchor BLDOPT_REMOVE_FAMILY_12_SUPPORT
* @li @e BLDOPT_REMOVE_FAMILY_12_SUPPORT @n
* If the package contains support for family 10h processors, remove that support.
*
* @anchor BLDOPT_REMOVE_FAMILY_14_SUPPORT
* @li @e BLDOPT_REMOVE_FAMILY_14_SUPPORT @n
* If the package contains support for family 14h processors, remove that support.
*
* @anchor BLDOPT_REMOVE_FAMILY_15_SUPPORT
* @li @e BLDOPT_REMOVE_FAMILY_15_SUPPORT @n
* If the package contains support for family 15h processors, remove that support.
*
* @anchor BLDOPT_REMOVE_AM3_SOCKET_SUPPORT
* @li @e BLDOPT_REMOVE_AM3_SOCKET_SUPPORT @n
* This option removes the code which implements support for processors packaged for AM3 sockets.
*
* @anchor BLDOPT_REMOVE_ASB2_SOCKET_SUPPORT
* @li @e BLDOPT_REMOVE_ASB2_SOCKET_SUPPORT @n
* This option removes the code which implements support for processors packaged for ASB2 sockets.
*
* @anchor BLDOPT_REMOVE_C32_SOCKET_SUPPORT
* @li @e BLDOPT_REMOVE_C32_SOCKET_SUPPORT @n
* This option removes the code which implements support for processors packaged for C32 sockets.
*
* @anchor BLDOPT_REMOVE_FM1_SOCKET_SUPPORT
* @li @e BLDOPT_REMOVE_FM1_SOCKET_SUPPORT @n
* This option removes the code which implements support for processors packaged for FM1 sockets.
*
* @anchor BLDOPT_REMOVE_FP1_SOCKET_SUPPORT
* @li @e BLDOPT_REMOVE_FP1_SOCKET_SUPPORT @n
* This option removes the code which implements support for processors packaged for FP1 sockets.
*
* @anchor BLDOPT_REMOVE_FS1_SOCKET_SUPPORT
* @li @e BLDOPT_REMOVE_FS1_SOCKET_SUPPORT @n
* This option removes the code which implements support for processors packaged for FS1 sockets.
*
* @anchor BLDOPT_REMOVE_FT1_SOCKET_SUPPORT
* @li @e BLDOPT_REMOVE_FT1_SOCKET_SUPPORT @n
* This option removes the code which implements support for processors packaged for FT1 sockets.
*
* @anchor BLDOPT_REMOVE_G34_SOCKET_SUPPORT
* @li @e BLDOPT_REMOVE_G34_SOCKET_SUPPORT @n
* This option removes the code which implements support for processors packaged for G34 sockets.
*
* @anchor BLDOPT_REMOVE_S1G3_SOCKET_SUPPORT
* @li @e BLDOPT_REMOVE_S1G3_SOCKET_SUPPORT @n
* This option removes the code which implements support for processors packaged for S1G3 sockets.
*
* @anchor BLDOPT_REMOVE_S1G4_SOCKET_SUPPORT
* @li @e BLDOPT_REMOVE_S1G4_SOCKET_SUPPORT @n
* This option removes the code which implements support for processors packaged for S1G4 sockets.
*/
/**
* @page examplecustomizations Customization Examples
*
* The Addendum \<plat\>Options.c file for each platform contains the minimum required
* customizations for that platform. That is, it contains settings which would be needed
* to boot a SimNow! bsd for that platform.
* However, each individual product based on that platform will have customizations necessary for
* that hardware. Since the actual customizations needed vary so much, they are not included in
* the \<plat\>Options.c. This section provides examples of useful customizations that you can use or
* modify to suit your needs.
*
* @par
*
* Source for the examples shown can be found at Addendum\\Examples. @n
*
* - @ref DeemphasisExamples "Deemphasis List Examples"
* - @ref FrequencyLimitExamples "Frequency Limit Examples"
* - @ref PerfPerWattHt "A performance-per-watt optimization Example"
*
* @anchor DeemphasisExamples
* @par Deemphasis List Examples
*
* These examples customize PLATFORM_CONFIGURATION.PlatformDeemphasisList.
* Source for the deemphasis list examples can be found in DeemphasisExamples.c. @n
* @dontinclude DeemphasisExamples.c
* <ul>
* <li>
* The following deemphasis list provides an example for a 2P MCM Max Performance configuration.
* High Speed HT frequencies are supported. There is only one non-coherent chain. Note the technique of
* putting specified link matches before all uses of match any. It often works well to specify the non-coherent links
* and use match any for the coherent links.
* @skip DinarDeemphasisList
* @until {
* The non-coherent chain can run up to 2600 MHz. The chain is located on Socket 0, package Link 2.
* @until {
* @line }
* @line {
* @line }
* The coherent links can run up to 3200 MHz.
* @until HT_FREQUENCY_MAX
* @line }
* end of list:
* @until }
* Make this list the build time customized deemphasis list.
* @line define
*
* </li><li>
*
* The following deemphasis list provides an example for a 4P MCM Max Performance configuration.
* This system has a backplane with connectors for CPU cards and an IO board. So trace lengths are long.
* There can be one to four IO Chains, depending on the IO board.
* @skipline DoubloonDeemphasisList
* @until DoubloonDeemphasisList
*
* </li><li>
*
* The following deemphasis list further illustrates complex coherent system deemphasis. This is the same
* Dinar system as in an earlier example, but this time all the coherent links are explicitly customized (as
* might be needed if each link has unique characterization). For this example, we skip the non-coherent chains.
* (A real system would have to include them, see example above.)
* @skip DinarPerLinkDeemphasisList
* @until {
* Provide deemphasis settings for the 16 bit, ganged, links, Socket 0 links 0, 1 and Socket 1 links 1 and 2.
* Provide entries to customize all HT3 frequencies at which the links may run. This example covers all HT3 speeds.
* @until {
* @until DcvLevelMinus6
* @until DcvLevelMinus6
* @until DcvLevelMinus6
* @until DcvLevelMinus6
* Link 3 on both sockets connects different internal die: sublink 0 connects the internal node zeroes, and
* sublink 1 connects the internal node ones. So the link is unganged and both sublinks must be specifically
* customized.
* @until {
* @until DcvLevelMinus6
* @until DcvLevelMinus6
* @until DcvLevelMinus6
* @until DcvLevelMinus6
* end of list:
* @until define
*
* </ul>
*
* @anchor FrequencyLimitExamples
* @par Frequency Limit Examples
*
* These examples customize AMD_HT_INTERFACE.CpuToCpuPcbLimitsList and AMD_HT_INTERFACE.IoPcbLimitsList.
* Source for the frequency limit examples can be found in FrequencyLimitExamples.c. @n
* @dontinclude FrequencyLimitExamples.c
* <ul>
* <li>
* The following list provides an example for limiting all coherent links to non-extended frequencies,
* that is, to 2600 MHz or less.
* @skipline NonExtendedCpuToCpuLimitList
* @until {
* Provide the limit customization. Match links from any socket, any package link, to any socket, any package link. Width is not limited.
* @until HT_FREQUENCY_LIMIT_2600M
* End of list:
* @until ;
* Customize the build to use this cpu to cpu frequency limit.
* @until NonExtendedCpuToCpuLimitList
* @n </li>
* <li>
* The following list provides an example for limiting all coherent links to HT 1 frequencies,
* that is, to 1000 MHz or less. This is sometimes useful for test and debug.
* @skipline Ht1CpuToCpuLimitList
* @until Ht1CpuToCpuLimitList
* @n </li>
* <li>
* The following list provides an example for limiting all non-coherent links to 2400 MHz or less.
* The chain is matched by host processor Socket and package Link. The depth can be used to select a particular device
* to device link on the chain. In this example, the chain consists of a single cave device and depth can be set to match any.
* @skipline No2600MhzIoLimitList
* @until No2600MhzIoLimitList
* @n </li>
* <li>
* The following list provides an example for limiting all non-coherent links to the minimum HT 3 frequency,
* that is, to 1200 MHz or less. This can be useful for test and debug.
* @skipline MinHt3IoLimitList
* @until MinHt3IoLimitList
* @n </li>
*
* </ul>
*
* @anchor PerfPerWattHt
* @par Performance-per-Watt Optimization Example
*
* This example customizes AMD_HT_INTERFACE.SkipRegangList.
* Source for the Performance-per-watt Optimization example can be found in PerfPerWatt.c. @n
* @dontinclude PerfPerWatt.c
* To implement a performance-per-watt optimization for MCM processors, use the skip regang structure shown. @n
* @skipline PerfPerWatt
* @until PerfPerWatt
*
*/

499
src/vendorcode/amd/agesa/f15/Include/PlatformMemoryConfiguration.h
View File

@ -1,499 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Platform Specific Memory Configuration
*
* Contains Definitions and Macros for control of AGESA Memory code on a per platform basis
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: OPTION
* @e \$Revision: 52513 $ @e \$Date: 2011-05-08 21:50:58 -0600 (Sun, 08 May 2011) $
*
*/
/*****************************************************************************
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef _PLATFORM_MEMORY_CONFIGURATION_H_
#define _PLATFORM_MEMORY_CONFIGURATION_H_
/*----------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*----------------------------------------------------------------------------------------
*/
#ifndef PSO_ENTRY
#define PSO_ENTRY UINT8
#endif
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* PLATFORM SPECIFIC MEMORY DEFINITIONS
*----------------------------------------------------------------------------------------
*/
///
/// Memory Speed and DIMM Population Masks
///
///< DDR Speed Masks
///< Specifies the DDR Speed on a memory channel
///
#define ANY_SPEED 0xFFFFFFFF
#define DDR400 ((UINT32) 1 << (DDR400_FREQUENCY / 66))
#define DDR533 ((UINT32) 1 << (DDR533_FREQUENCY / 66))
#define DDR667 ((UINT32) 1 << (DDR667_FREQUENCY / 66))
#define DDR800 ((UINT32) 1 << (DDR800_FREQUENCY / 66))
#define DDR1066 ((UINT32) 1 << (DDR1066_FREQUENCY / 66))
#define DDR1333 ((UINT32) 1 << (DDR1333_FREQUENCY / 66))
#define DDR1600 ((UINT32) 1 << (DDR1600_FREQUENCY / 66))
#define DDR1866 ((UINT32) 1 << (DDR1866_FREQUENCY / 66))
#define DDR2133 ((UINT32) 1 << (DDR2133_FREQUENCY / 66))
#define DDR2400 ((UINT32) 1 << (DDR2400_FREQUENCY / 66))
///
///< DIMM POPULATION MASKS
///< Specifies the DIMM Population on a channel (can be added together to specify configuration).
///< ex. SR_DIMM0 + SR_DIMM1 : Single Rank Dimm in slot 0 AND Slot 1
///< SR_DIMM0 + DR_DIMM0 + SR_DIMM1 +DR_DIMM1 : Single OR Dual rank in Slot 0 AND Single OR Dual rank in Slot 1
///
#define ANY_ 0xFF ///< Any dimm configuration the current channel
#define SR_DIMM0 0x0001 ///< Single rank dimm in slot 0 on the current channel
#define SR_DIMM1 0x0010 ///< Single rank dimm in slot 1 on the current channel
#define SR_DIMM2 0x0100 ///< Single rank dimm in slot 2 on the current channel
#define SR_DIMM3 0x1000 ///< Single rank dimm in slot 3 on the current channel
#define DR_DIMM0 0x0002 ///< Dual rank dimm in slot 0 on the current channel
#define DR_DIMM1 0x0020 ///< Dual rank dimm in slot 1 on the current channel
#define DR_DIMM2 0x0200 ///< Dual rank dimm in slot 2 on the current channel
#define DR_DIMM3 0x2000 ///< Dual rank dimm in slot 3 on the current channel
#define QR_DIMM0 0x0004 ///< Quad rank dimm in slot 0 on the current channel
#define QR_DIMM1 0x0040 ///< Quad rank dimm in slot 1 on the current channel
#define QR_DIMM2 0x0400 ///< Quad rank dimm in slot 2 on the current channel
#define QR_DIMM3 0x4000 ///< Quad rank dimm in slot 3 on the current channel
#define LR_DIMM0 0x0001 ///< Lrdimm in slot 0 on the current channel
#define LR_DIMM1 0x0010 ///< Lrdimm in slot 1 on the current channel
#define LR_DIMM2 0x0100 ///< Lrdimm in slot 2 on the current channel
#define LR_DIMM3 0x1000 ///< Lrdimm in slot 3 on the current channel
#define ANY_DIMM0 0x000F ///< Any Dimm combination in slot 0 on the current channel
#define ANY_DIMM1 0x00F0 ///< Any Dimm combination in slot 1 on the current channel
#define ANY_DIMM2 0x0F00 ///< Any Dimm combination in slot 2 on the current channel
#define ANY_DIMM3 0xF000 ///< Any Dimm combination in slot 3 on the current channel
///
///< CS POPULATION MASKS
///< Specifies the CS Population on a channel (can be added together to specify configuration).
///< ex. CS0 + CS1 : CS0 and CS1 apply to the setting
///
#define CS_ANY_ 0xFF ///< Any CS configuration
#define CS0_ 0x01 ///< CS0 bit map mask
#define CS1_ 0x02 ///< CS1 bit map mask
#define CS2_ 0x04 ///< CS2 bit map mask
#define CS3_ 0x08 ///< CS3 bit map mask
#define CS4_ 0x10 ///< CS4 bit map mask
#define CS5_ 0x20 ///< CS5 bit map mask
#define CS6_ 0x40 ///< CS6 bit map mask
#define CS7_ 0x80 ///< CS7 bit map mask
///
///< Number of Dimms on the current channel
///< This is a mask used to indicate the number of dimms in a channel
///< They can be added to indicate multiple conditions (i.e 1 OR 2 Dimms)
///
#define ANY_NUM 0xFF ///< Any number of Dimms
#define NO_DIMM 0x00 ///< No Dimms present
#define ONE_DIMM 0x01 ///< One dimm Poulated on the current channel
#define TWO_DIMM 0x02 ///< Two dimms Poulated on the current channel
#define THREE_DIMM 0x04 ///< Three dimms Poulated on the current channel
#define FOUR_DIMM 0x08 ///< Four dimms Poulated on the current channel
///
///< DIMM VOLTAGE MASKS
///
#define VOLT_ANY_ 0xFF ///< Any voltage configuration
#define VOLT1_5_ 0x01 ///< Voltage 1.5V bit map mask
#define VOLT1_35_ 0x02 ///< Voltage 1.35V bit map mask
#define VOLT1_25_ 0x04 ///< Voltage 1.25V bit map mask
//
// < Not applicable
//
#define NA_ 0 ///< Not applicable
/*----------------------------------------------------------------------------------------
*
* Platform Specific Override Definitions for Socket, Channel and Dimm
* This indicates where a platform override will be applied.
*
*----------------------------------------------------------------------------------------
*/
///
///< SOCKET MASKS
///< Indicates associated processor sockets to apply override settings
///
#define ANY_SOCKET 0xFF ///< Apply to all sockets
#define SOCKET0 0x01 ///< Apply to socket 0
#define SOCKET1 0x02 ///< Apply to socket 1
#define SOCKET2 0x04 ///< Apply to socket 2
#define SOCKET3 0x08 ///< Apply to socket 3
#define SOCKET4 0x10 ///< Apply to socket 4
#define SOCKET5 0x20 ///< Apply to socket 5
#define SOCKET6 0x40 ///< Apply to socket 6
#define SOCKET7 0x80 ///< Apply to socket 7
///
///< CHANNEL MASKS
///< Indicates Memory channels where override should be applied
///
#define ANY_CHANNEL 0xFF ///< Apply to all Memory channels
#define CHANNEL_A 0x01 ///< Apply to Channel A
#define CHANNEL_B 0x02 ///< Apply to Channel B
#define CHANNEL_C 0x04 ///< Apply to Channel C
#define CHANNEL_D 0x08 ///< Apply to Channel D
///
/// DIMM MASKS
/// Indicates Dimm Slots where override should be applied
///
#define ALL_DIMMS 0xFF ///< Apply to all dimm slots
#define DIMM0 0x01 ///< Apply to Dimm Slot 0
#define DIMM1 0x02 ///< Apply to Dimm Slot 1
#define DIMM2 0x04 ///< Apply to Dimm Slot 2
#define DIMM3 0x08 ///< Apply to Dimm Slot 3
///
/// REGISTER ACCESS MASKS
/// Not supported as an at this time
///
#define ACCESS_NB0 0x0
#define ACCESS_NB1 0x1
#define ACCESS_NB2 0x2
#define ACCESS_NB3 0x3
#define ACCESS_NB4 0x4
#define ACCESS_PHY 0x5
#define ACCESS_DCT_XT 0x6
/*----------------------------------------------------------------------------------------
*
* Platform Specific Overriding Table Definitions
*
*----------------------------------------------------------------------------------------
*/
#define PSO_END 0 ///< Table End
#define PSO_CKE_TRI 1 ///< CKE Tristate Map
#define PSO_ODT_TRI 2 ///< ODT Tristate Map
#define PSO_CS_TRI 3 ///< CS Tristate Map
#define PSO_MAX_DIMMS 4 ///< Max Dimms per channel
#define PSO_CLK_SPEED 5 ///< Clock Speed
#define PSO_DIMM_TYPE 6 ///< Dimm Type
#define PSO_MEMCLK_DIS 7 ///< MEMCLK Disable Map
#define PSO_MAX_CHNLS 8 ///< Max Channels per Socket
#define PSO_BUS_SPEED 9 ///< Max Memory Bus Speed
#define PSO_MAX_CHIPSELS 10 ///< Max Chipsel per Channel
#define PSO_MEM_TECH 11 ///< Channel Memory Type
#define PSO_WL_SEED 12 ///< DDR3 Write Levelization Seed delay
#define PSO_RXEN_SEED 13 ///< Hardwared based RxEn seed
#define PSO_NO_LRDIMM_CS67_ROUTING 14 ///< CS6 and CS7 are not Routed to all Memoy slots on a channel for LRDIMMs
#define PSO_SOLDERED_DOWN_SODIMM_TYPE 15 ///< Soldered down SODIMM type
#define PSO_LVDIMM_VOLT1_5_SUPPORT 16 ///< Force LvDimm voltage to 1.5V
#define PSO_MIN_RD_WR_DATAEYE_WIDTH 17 ///< Min RD/WR dataeye width
#define PSO_CPU_FAMILY_TO_OVERRIDE 18 ///< CPU family signature to tell following PSO macros are CPU family dependent
/*----------------------------------
* CONDITIONAL PSO SPECIFIC ENTRIES
*---------------------------------*/
// Condition Types
#define CONDITIONAL_PSO_MIN 100 ///< Start of Conditional Entry Types
#define PSO_CONDITION_AND 100 ///< And Block - Start of Conditional block
#define PSO_CONDITION_LOC 101 ///< Location - Specify Socket, Channel, Dimms to be affected
#define PSO_CONDITION_SPD 102 ///< SPD - Specify a specific SPD value on a Dimm on the channel
#define PSO_CONDITION_REG 103 // Reserved
#define PSO_CONDITION_MAX 103 ///< End Of Condition Entry Types
// Action Types
#define PSO_ACTION_MIN 120 ///< Start of Action Entry Types
#define PSO_ACTION_ODT 120 ///< ODT values to override
#define PSO_ACTION_ADDRTMG 121 ///< Address/Timing values to override
#define PSO_ACTION_ODCCONTROL 122 ///< ODC Control values to override
#define PSO_ACTION_SLEWRATE 123 ///< Slew Rate value to override
#define PSO_ACTION_REG 124 // Reserved
#define PSO_ACTION_SPEEDLIMIT 125 ///< Memory Bus speed Limit based on configuration
#define PSO_ACTION_MAX 125 ///< End of Action Entry Types
#define CONDITIONAL_PSO_MAX 139 ///< End of Conditional Entry Types
/*----------------------------------
* TABLE DRIVEN PSO SPECIFIC ENTRIES
*---------------------------------*/
// Condition descriptor
#define PSO_TBLDRV_CONFIG 200 ///< Configuration Descriptor
// Overriding entry types
#define PSO_TBLDRV_START 210 ///< Start of Table Driven Overriding Entry Types
#define PSO_TBLDRV_SPEEDLIMIT 210 ///< Speed Limit
#define PSO_TBLDRV_ODT_RTTNOM 211 ///< RttNom
#define PSO_TBLDRV_ODT_RTTWR 212 ///< RttWr
#define PSO_TBLDRV_ODTPATTERN 213 ///< Odt Patterns
#define PSO_TBLDRV_ADDRTMG 214 ///< Address/Timing values
#define PSO_TBLDRV_ODCCTRL 215 ///< ODC Control values
#define PSO_TBLDRV_SLOWACCMODE 216 ///< Slow Access Mode
#define PSO_TBLDRV_MR0_CL 217 ///< MR0[CL]
#define PSO_TBLDRV_MR0_WR 218 ///< MR0[WR]
#define PSO_TBLDRV_RC2_IBT 219 ///< RC2[IBT]
#define PSO_TBLDRV_RC10_OPSPEED 220 ///< RC10[Opearting Speed]
#define PSO_TBLDRV_LRDIMM_IBT 221 ///< LrDIMM IBT
#define PSO_TBLDRV____TRAINING 222 ///< training
#define PSO_TBLDRV_INVALID_TYPE 223 ///< Invalid Type
#define PSO_TBLDRV_END 223 ///< End of Table Driven Overriding Entry Types
/*----------------------------------------------------------------------------------------
* CONDITIONAL OVERRIDE TABLE MACROS
*----------------------------------------------------------------------------------------
*/
#define CPU_FAMILY_TO_OVERRIDE(CpuFamilyRevision) \
PSO_CPU_FAMILY_TO_OVERRIDE, 4, \
((CpuFamilyRevision) & 0x0FF), (((CpuFamilyRevision) >> 8)& 0x0FF), (((CpuFamilyRevision) >> 16)& 0x0FF), (((CpuFamilyRevision) >> 24)& 0x0FF)
#define MEMCLK_DIS_MAP(SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map, Bit4Map, Bit5Map, Bit6Map, Bit7Map) \
PSO_MEMCLK_DIS, 11, SocketID, ChannelID, ALL_DIMMS, Bit0Map, Bit1Map, Bit2Map, Bit3Map, Bit4Map, Bit5Map, Bit6Map \
, Bit7Map
#define CKE_TRI_MAP(SocketID, ChannelID, Bit0Map, Bit1Map) \
PSO_CKE_TRI, 5, SocketID, ChannelID, ALL_DIMMS, Bit0Map, Bit1Map
#define ODT_TRI_MAP(SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map) \
PSO_ODT_TRI, 7, SocketID, ChannelID, ALL_DIMMS, Bit0Map, Bit1Map, Bit2Map, Bit3Map
#define CS_TRI_MAP(SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map, Bit4Map, Bit5Map, Bit6Map, Bit7Map) \
PSO_CS_TRI, 11, SocketID, ChannelID, ALL_DIMMS, Bit0Map, Bit1Map, Bit2Map, Bit3Map, Bit4Map, Bit5Map, Bit6Map, Bit7Map
#define NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel) \
PSO_MAX_DIMMS, 4, SocketID, ChannelID, ALL_DIMMS, NumberOfDimmSlotsPerChannel
#define NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel) \
PSO_MAX_CHIPSELS, 4, SocketID, ChannelID, ALL_DIMMS, NumberOfChipSelectsPerChannel
#define NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket) \
PSO_MAX_CHNLS, 4, SocketID, ANY_CHANNEL, ALL_DIMMS, NumberOfChannelsPerSocket
#define OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, TimingMode, BusSpeed) \
PSO_BUS_SPEED, 11, SocketID, ChannelID, ALL_DIMMS, TimingMode, (TimingMode >> 8), (TimingMode >> 16), (TimingMode >> 24), \
BusSpeed, (BusSpeed >> 8), (BusSpeed >> 16), (BusSpeed >> 24)
#define DRAM_TECHNOLOGY(SocketID, MemTechType) \
PSO_MEM_TECH, 7, SocketID, ANY_CHANNEL, ALL_DIMMS, MemTechType, (MemTechType >> 8), (MemTechType >> 16), (MemTechType >> 24)
#define WRITE_LEVELING_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, \
Byte6Seed, Byte7Seed, ByteEccSeed) \
PSO_WL_SEED, 12, SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, \
Byte6Seed, Byte7Seed, ByteEccSeed
#define HW_RXEN_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, \
Byte6Seed, Byte7Seed, ByteEccSeed) \
PSO_RXEN_SEED, 21, SocketID, ChannelID, DimmID, Byte0Seed, (Byte0Seed >> 8), Byte1Seed, (Byte1Seed >> 8), Byte2Seed, (Byte2Seed >> 8), \
Byte3Seed, (Byte3Seed >> 8), Byte4Seed, (Byte4Seed >> 8), Byte5Seed, (Byte5Seed >> 8), Byte6Seed, (Byte6Seed >> 8), \
Byte7Seed, (Byte7Seed >> 8), ByteEccSeed, (ByteEccSeed >> 8)
#define NO_LRDIMM_CS67_ROUTING(SocketID, ChannelID) \
PSO_NO_LRDIMM_CS67_ROUTING, 4, SocketID, ChannelID, ALL_DIMMS, TRUE
#define SOLDERED_DOWN_SODIMM_TYPE(SocketID, ChannelID) \
PSO_SOLDERED_DOWN_SODIMM_TYPE, 4, SocketID, ChannelID, ALL_DIMMS, TRUE
#define LVDIMM_FORCE_VOLT1_5_FOR_D0 \
PSO_LVDIMM_VOLT1_5_SUPPORT, 4, ANY_SOCKET, ANY_CHANNEL, ALL_DIMMS, TRUE
#define MIN_RD_WR_DATAEYE_WIDTH(SocketID, ChannelID, MinRdDataeyeWidth, MinWrDataeyeWidth) \
PSO_MIN_RD_WR_DATAEYE_WIDTH, 5, SocketID, ChannelID, ALL_DIMMS, MinRdDataeyeWidth, MinWrDataeyeWidth
/*----------------------------------------------------------------------------------------
* CONDITIONAL OVERRIDE TABLE MACROS
*----------------------------------------------------------------------------------------
*/
#define CONDITION_AND \
PSO_CONDITION_AND, 0
#define COND_LOC(SocketMsk, ChannelMsk, DimmMsk) \
PSO_CONDITION_LOC, 3, SocketMsk, ChannelMsk, DimmMsk
#define COND_SPD(Byte, Mask, Value) \
PSO_CONDITION_SPD, 3, Byte, Mask, Value
#define COND_REG(Access, Offset, Mask, Value) \
PSO_CONDITION_REG, 11, Access, (Offset & 0x0FF), (Offset >> 8), \
((Mask) & 0x0FF), (((Mask) >> 8) & 0x0FF), (((Mask) >> 16) & 0x0FF), (((Mask) >> 24) & 0x0FF), \
((Value) & 0x0FF), (((Value) >> 8) & 0x0FF), (((Value) >> 16) & 0x0FF), (((Value) >> 24) & 0x0FF)
#define ACTION_ODT(Frequency, Dimms, QrDimms, DramOdt, QrDramOdt, DramDynOdt) \
PSO_ACTION_ODT, 9, \
((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), ((Frequency >> 24)& 0x0FF), \
Dimms, QrDimms, DramOdt, QrDramOdt, DramDynOdt
#define ACTION_ADDRTMG(Frequency, DimmConfig, AddrTmg) \
PSO_ACTION_ADDRTMG, 10, \
((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \
((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), \
(AddrTmg & 0x0FF), ((AddrTmg >> 8)& 0x0FF), ((AddrTmg >> 16)& 0x0FF), ((AddrTmg >> 24)& 0x0FF)
#define ACTION_ODCCTRL(Frequency, DimmConfig, OdcCtrl) \
PSO_ACTION_ODCCONTROL, 10, \
((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \
((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), \
(OdcCtrl & 0x0FF), ((OdcCtrl >> 8)& 0x0FF), ((OdcCtrl >> 16)& 0x0FF), ((OdcCtrl >> 24)& 0x0FF)
#define ACTION_SLEWRATE(Frequency, DimmConfig, SlewRate) \
PSO_ACTION_SLEWRATE, 10, \
((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \
((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), \
(SlewRate & 0x0FF), ((SlewRate >> 8)& 0x0FF), ((SlewRate >> 16)& 0x0FF), ((SlewRate >> 24)& 0x0FF)
#define ACTION_SPEEDLIMIT(DimmConfig, Dimms, SpeedLimit15, SpeedLimit135, SpeedLimit125) \
PSO_ACTION_SPEEDLIMIT, 9, \
((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), Dimms, \
(SpeedLimit15 & 0x0FF), ((SpeedLimit15 >> 8)& 0x0FF), \
(SpeedLimit135 & 0x0FF), ((SpeedLimit135 >> 8)& 0x0FF), \
(SpeedLimit125 & 0x0FF), ((SpeedLimit125 >> 8)& 0x0FF)
/*----------------------------------------------------------------------------------------
* END OF CONDITIONAL OVERRIDE TABLE MACROS
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* TABLE DRIVEN OVERRIDE MACROS
*----------------------------------------------------------------------------------------
*/
/// Configuration sub-descriptors
typedef enum {
CONFIG_GENERAL, ///< CONFIG_GENERAL
CONFIG_SPEEDLIMIT, ///< CONFIG_SPEEDLIMIT
CONFIG_RC2IBT, ///< CONFIG_RC2IBT
CONFIG_DONT_CARE, ///< CONFIG_DONT_CARE
} Config_Type;
// ====================
// Configuration Macros
// ====================
#define TBLDRV_CONFIG_TO_OVERRIDE(DimmPerCH, Frequency, DimmVolt, DimmConfig) \
PSO_TBLDRV_CONFIG, 9, \
CONFIG_GENERAL, \
DimmPerCH, DimmVolt, \
((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \
((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF)
#define TBLDRV_SPEEDLIMIT_CONFIG_TO_OVERRIDE(DimmPerCH, Dimms, NumOfSR, NumOfDR, NumOfQR, NumOfLRDimm) \
PSO_TBLDRV_CONFIG, 7, \
CONFIG_SPEEDLIMIT, \
DimmPerCH, Dimms, NumOfSR, NumOfDR, NumOfQR, NumOfLRDimm
#define TBLDRV_RC2IBT_CONFIG_TO_OVERRIDE(DimmPerCH, Frequency, DimmVolt, DimmConfig, NumOfReg) \
PSO_TBLDRV_CONFIG, 10, \
CONFIG_RC2IBT, \
DimmPerCH, DimmVolt, \
((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \
((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), \
NumOfReg
//==================
// Overriding Macros
//==================
#define TBLDRV_CONFIG_ENTRY_SPEEDLIMIT(SpeedLimit1_5, SpeedLimit1_35, SpeedLimit1_25) \
PSO_TBLDRV_SPEEDLIMIT, 6, \
(SpeedLimit1_5 & 0x0FF), ((SpeedLimit1_5 >> 8)& 0x0FF), \
(SpeedLimit1_35 & 0x0FF), ((SpeedLimit1_35 >> 8)& 0x0FF), \
(SpeedLimit1_25 & 0x0FF), ((SpeedLimit1_25 >> 8)& 0x0FF)
#define TBLDRV_CONFIG_ENTRY_ODT_RTTNOM(TgtCS, RttNom) \
PSO_TBLDRV_ODT_RTTNOM, 2, \
TgtCS, RttNom
#define TBLDRV_CONFIG_ENTRY_ODT_RTTWR(TgtCS, RttWr) \
PSO_TBLDRV_ODT_RTTWR, 2, \
TgtCS, RttWr
#define TBLDRV_CONFIG_ENTRY_ODTPATTERN(RdODTCSHigh, RdODTCSLow, WrODTCSHigh, WrODTCSLow) \
PSO_TBLDRV_ODTPATTERN, 16, \
((RdODTCSHigh) & 0x0FF), (((RdODTCSHigh) >> 8)& 0x0FF), (((RdODTCSHigh) >> 16)& 0x0FF), (((RdODTCSHigh) >> 24)& 0x0FF), \
((RdODTCSLow) & 0x0FF), (((RdODTCSLow) >> 8)& 0x0FF), (((RdODTCSLow) >> 16)& 0x0FF), (((RdODTCSLow) >> 24)& 0x0FF), \
((WrODTCSHigh) & 0x0FF), (((WrODTCSHigh) >> 8)& 0x0FF), (((WrODTCSHigh) >> 16)& 0x0FF), (((WrODTCSHigh) >> 24)& 0x0FF), \
((WrODTCSLow) & 0x0FF), (((WrODTCSLow) >> 8)& 0x0FF), (((WrODTCSLow) >> 16)& 0x0FF), (((WrODTCSLow) >> 24)& 0x0FF)
#define TBLDRV_CONFIG_ENTRY_ADDRTMG(AddrTmg) \
PSO_TBLDRV_ADDRTMG, 4, \
((AddrTmg) & 0x0FF), (((AddrTmg) >> 8)& 0x0FF), (((AddrTmg) >> 16)& 0x0FF), (((AddrTmg) >> 24)& 0x0FF)
#define TBLDRV_CONFIG_ENTRY_ODCCTRL(OdcCtrl) \
PSO_TBLDRV_ODCCTRL, 4, \
((OdcCtrl) & 0x0FF), (((OdcCtrl) >> 8)& 0x0FF), (((OdcCtrl) >> 16)& 0x0FF), (((OdcCtrl) >> 24)& 0x0FF)
#define TBLDRV_CONFIG_ENTRY_SLOWACCMODE(SlowAccMode) \
PSO_TBLDRV_SLOWACCMODE, 1, \
SlowAccMode
#define TBLDRV_CONFIG_ENTRY_RC2_IBT(TgtDimm, IBT) \
PSO_TBLDRV_RC2_IBT, 2, \
TgtDimm, IBT
#define TBLDRV_OVERRIDE_MR0_CL(RegValOfTcl, MR0CL13, MR0CL0) \
PSO_TBLDRV_CONFIG, 1, \
CONFIG_DONT_CARE, \
PSO_TBLDRV_MR0_CL, 3, \
RegValOfTcl, MR0CL13, MR0CL0
#define TBLDRV_OVERRIDE_MR0_WR(RegValOfTwr, MR0WR) \
PSO_TBLDRV_CONFIG, 1, \
CONFIG_DONT_CARE, \
PSO_TBLDRV_MR0_WR, 2, \
RegValOfTwr, MR0WR
#define TBLDRV_OVERRIDE_RC10_OPSPEED(Frequency, MR10OPSPEED) \
PSO_TBLDRV_CONFIG, 1, \
CONFIG_DONT_CARE, \
PSO_TBLDRV_RC10_OPSPEED, 5, \
((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \
MR10OPSPEED
#define TBLDRV_CONFIG_ENTRY_LRDMM_IBT(F0RC8, F1RC0, F1RC1, F1RC2) \
PSO_TBLDRV_LRDIMM_IBT, 4, \
F0RC8, F1RC0, F1RC1, F1RC2
#define TBLDRV_CONFIG_ENTRY____TRAINING(Training__Mode) \
PSO_TBLDRV____TRAINING, 1, \
Training__Mode
//============================
// Macros for removing entries
//============================
#define INVALID_CONFIG_FLAG 0x8000
#define TBLDRV_INVALID_CONFIG \
PSO_TBLDRV_INVALID_TYPE, 0
/*----------------------------------------------------------------------------------------
* END OF TABLE DRIVEN OVERRIDE MACROS
*----------------------------------------------------------------------------------------
*/
#endif // _PLATFORM_MEMORY_CONFIGURATION_H_

116
src/vendorcode/amd/agesa/f15/Include/SanMarinoInstall.h
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@ -1,116 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Install of build options for a SanMarino platform solution
*
* This file generates the defaults tables for the "San Marino" platform solution
* set of processors. The documented build options are imported from a user
* controlled file for processing.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Core
* @e \$Revision: 59375 $ @e \$Date: 2011-09-21 13:24:35 -0600 (Wed, 21 Sep 2011) $
*/
/*****************************************************************************
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
***************************************************************************/
#include "AGESA.h"
#include "cpuRegisters.h"
#include "cpuFamRegisters.h"
#include "cpuFamilyTranslation.h"
#include "AdvancedApi.h"
#include "heapManager.h"
#include "CreateStruct.h"
#include "cpuFeatures.h"
#include "Table.h"
#include "CommonReturns.h"
#include "cpuEarlyInit.h"
#include "cpuLateInit.h"
#include "GnbInterfaceStub.h"
/*****************************************************************************
* Define the RELEASE VERSION string
*
* The Release Version string should identify the next planned release.
* When a branch is made in preparation for a release, the release manager
* should change/confirm that the branch version of this file contains the
* string matching the desired version for the release. The trunk version of
* the file should always contain a trailing 'X'. This will make sure that a
* development build from trunk will not be confused for a released version.
* The release manager will need to remove the trailing 'X' and update the
* version string as appropriate for the release. The trunk copy of this file
* should also be updated/incremented for the next expected version, + trailing 'X'
****************************************************************************/
// This is the delivery package title, "OrochiPI"
// This string MUST be exactly 8 characters long
#define AGESA_PACKAGE_STRING {'O', 'r', 'o', 'c', 'h', 'i', 'P', 'I'}
// This is the release version number of the AGESA component
// This string MUST be exactly 12 characters long
#define AGESA_VERSION_STRING {'V', '1', '.', '2', '.', '0', '.', '0', ' ', ' ', ' ', ' '}
// The San Marino solution is defined to be families 0x10 and 0x15 models 0x0 - 0xF in the C32 socket.
#define INSTALL_C32_SOCKET_SUPPORT TRUE
#define INSTALL_FAMILY_10_SUPPORT TRUE
#define INSTALL_FAMILY_15_MODEL_0x_SUPPORT TRUE
#ifdef BLDOPT_REMOVE_FAMILY_10_SUPPORT
#if BLDOPT_REMOVE_FAMILY_10_SUPPORT == TRUE
#undef INSTALL_FAMILY_10_SUPPORT
#define INSTALL_FAMILY_10_SUPPORT FALSE
#endif
#endif
#ifdef BLDOPT_REMOVE_FAMILY_15_SUPPORT
#if BLDOPT_REMOVE_FAMILY_15_SUPPORT == TRUE
#undef INSTALL_FAMILY_15_MODEL_0x_SUPPORT
#define INSTALL_FAMILY_15_MODEL_0x_SUPPORT FALSE
#endif
#endif
// The following definitions specify the default values for various parameters in which there are
// no clearly defined defaults to be used in the common file. The values below are based on product
// and BKDG content, please consult the AGESA Memory team for consultation.
#define DFLT_SCRUB_DRAM_RATE (0xFF)
#define DFLT_SCRUB_L2_RATE (0x10)
#define DFLT_SCRUB_L3_RATE (0x10)
#define DFLT_SCRUB_IC_RATE (0)
#define DFLT_SCRUB_DC_RATE (0x12)
#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_REGISTERED
#define DFLT_VRM_SLEW_RATE (2500)
// Instantiate all solution relevant data.
#include "PlatformInstall.h"

161
src/vendorcode/amd/agesa/f15/Include/Topology.h
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@ -1,161 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Topology interface definitions.
*
* Contains AMD AGESA internal interface for topology related data which
* is consumed by code other than HyperTransport init (and produced by
* HyperTransport init.)
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Core
*/
/*****************************************************************************
*
* Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _TOPOLOGY_H_
#define _TOPOLOGY_H_
// Defines for limiting data structure maximum allocation and limit checking.
#define MAX_NODES 8
#define MAX_SOCKETS MAX_NODES
#define MAX_DIES 2
// Defines useful with package link
#define HT_LIST_MATCH_INTERNAL_LINK_0 0xFA
#define HT_LIST_MATCH_INTERNAL_LINK_1 0xFB
#define HT_LIST_MATCH_INTERNAL_LINK_2 0xFC
/**
* Hop Count Table.
* This is a heap data structure. The Hops array is filled as a size x size matrix.
* The unused space, if any, is all at the end.
*/
typedef struct {
UINT8 Size; ///< The row and column size of actual hop count data */
UINT8 Hops[MAX_NODES * MAX_NODES]; ///< Room for a dynamic two dimensional array of [size][size] */
} HOP_COUNT_TABLE;
/**
* Socket and Module to Node Map Item.
* Provide the Node Id and core id range for each module in each processor.
*/
typedef struct {
UINT8 Node; ///< The module's Node id.
UINT8 LowCore; ///< The lowest processor core id for this module.
UINT8 HighCore; ///< The highest processor core id for this module.
UINT8 EnabledComputeUnits; ///< The value of Enabled for this processor module.
UINT8 DualCoreComputeUnits; ///< The value of DualCore for this processor module.
} SOCKET_DIE_TO_NODE_ITEM;
/**
* Socket and Module to Node Map.
* This type is a pointer to the actual map, it can be used for a struct item or
* for typecasting a heap buffer pointer.
*/
typedef SOCKET_DIE_TO_NODE_ITEM (*SOCKET_DIE_TO_NODE_MAP)[MAX_SOCKETS][MAX_DIES];
/**
* Node id to Socket Die Map Item.
*/
typedef struct {
UINT8 Socket; ///< socket of the processor containing the Node.
UINT8 Die; ///< the module in the processor which is Node.
} NODE_TO_SOCKET_DIE_ITEM;
/**
* Node id to Socket Die Map.
*/
typedef NODE_TO_SOCKET_DIE_ITEM (*NODE_TO_SOCKET_DIE_MAP)[MAX_NODES];
/**
* Provide AP core with socket and node context at start up.
* This information is posted to the AP cores using a register as a mailbox.
*/
typedef struct {
UINT32 Node:4; ///< The node id of Core's node.
UINT32 Socket:4; ///< The socket of this Core's node.
UINT32 Module:2; ///< The internal module number for Core's node.
UINT32 ModuleType:2; ///< Single Module = 0, Multi-module = 1.
UINT32 :20; ///< Reserved
} AP_MAIL_INFO_FIELDS;
/**
* AP info fields can be written and read to a register.
*/
typedef union {
UINT32 Info; ///< Just a number for register access, or opaque passing.
AP_MAIL_INFO_FIELDS Fields; ///< access to the info fields.
} AP_MAIL_INFO;
/**
* Provide AP core with system degree and system core number at start up.
* This information is posted to the AP cores using a register as a mailbox.
*/
typedef struct {
UINT32 SystemDegree:3; ///< The number of connected links
UINT32 :3; ///< Reserved
UINT32 HeapIndex:6; ///< The zero-based system core number
UINT32 :20; ///< Reserved
} AP_MAIL_EXT_INFO_FIELDS;
/**
* AP info fields can be written and read to a register.
*/
typedef union {
UINT32 Info; ///< Just a number for register access, or opaque passing.
AP_MAIL_EXT_INFO_FIELDS Fields; ///< access to the info fields.
} AP_MAIL_EXT_INFO;
/**
* AP Info mailbox set.
*/
typedef struct {
AP_MAIL_INFO ApMailInfo; ///< The AP mail info
AP_MAIL_EXT_INFO ApMailExtInfo; ///< The extended AP mail info
} AP_MAILBOXES;
/**
* Provide a northbridge to package mapping for link assignments.
*
*/
typedef struct {
UINT8 Link; ///< The Node's link
UINT8 Module; ///< The internal module position of Node
UINT8 PackageLink; ///< The corresponding package link
} PACKAGE_HTLINK_MAP_ITEM;
/**
* A Processor's complete set of link assignments
*/
typedef PACKAGE_HTLINK_MAP_ITEM (*PACKAGE_HTLINK_MAP)[];
#endif // _TOPOLOGY_H_

136
src/vendorcode/amd/agesa/f15/Legacy/Proc/Dispatcher.c
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@ -1,136 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD binary block interface
*
* Contains the block entry function dispatcher
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Legacy
* @e \$Revision: 56322 $ @e \$Date: 2011-07-11 16:51:42 -0600 (Mon, 11 Jul 2011) $
*
*/
/*****************************************************************************
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "amdlib.h"
#include "Dispatcher.h"
#include "Options.h"
#include "Filecode.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G2_PEI)
#define FILECODE LEGACY_PROC_DISPATCHER_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
extern CONST DISPATCH_TABLE DispatchTable[];
extern AMD_MODULE_HEADER mCpuModuleID;
/*---------------------------------------------------------------------------------------*/
/**
* The Dispatcher is the entry point into the AGESA software. It takes a function
* number as entry parameter in order to invoke the published function
*
* @param[in,out] ConfigPtr
*
* @return AGESA Status.
*
*/
AGESA_STATUS
CALLCONV
AmdAgesaDispatcher (
IN OUT VOID *ConfigPtr
)
{
AGESA_STATUS Status;
MODULE_ENTRY ModuleEntry;
DISPATCH_TABLE *Entry;
Status = AGESA_UNSUPPORTED;
ModuleEntry = NULL;
Entry = (DISPATCH_TABLE *) DispatchTable;
while (Entry->FunctionId != 0) {
if ((((AMD_CONFIG_PARAMS *) ConfigPtr)->Func) == Entry->FunctionId) {
Status = Entry->EntryPoint (ConfigPtr);
break;
}
Entry++;
}
// 2. Try next dispatcher if possible, and we have not already got status back
if ((mCpuModuleID.NextBlock != NULL) && (Status == AGESA_UNSUPPORTED)) {
ModuleEntry = (MODULE_ENTRY) (mCpuModuleID.NextBlock->ModuleDispatcher);
if (ModuleEntry != NULL) {
Status = (*ModuleEntry) (ConfigPtr);
}
}
return (Status);
}
/*---------------------------------------------------------------------------------------*/
/**
* The host environment interface of callout.
*
* @param[in] Func
* @param[in] Data
* @param[in,out] ConfigPtr
*
* @return The AGESA Status returned from the callout.
*
*/
AGESA_STATUS
CALLCONV
AmdAgesaCallout (
IN UINT32 Func,
IN UINTN Data,
IN OUT VOID *ConfigPtr
)
{
UINT32 Result;
Result = AGESA_UNSUPPORTED;
if (((AMD_CONFIG_PARAMS *) ConfigPtr)->CalloutPtr == NULL) {
return Result;
}
Result = (((AMD_CONFIG_PARAMS *) ConfigPtr)->CalloutPtr) (Func, Data, ConfigPtr);
return (Result);
}

3
src/vendorcode/amd/agesa/f15/Legacy/Proc/Makefile.inc
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@ -1,3 +0,0 @@
libagesa-y += Dispatcher.c
libagesa-y += agesaCallouts.c
libagesa-y += hobTransfer.c

441
src/vendorcode/amd/agesa/f15/Legacy/Proc/agesaCallouts.c
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@ -1,441 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD CPU AGESA Callout Functions
*
* Contains code to set / get useful platform information.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Common
* @e \$Revision: 50871 $ @e \$Date: 2011-04-14 15:39:51 -0600 (Thu, 14 Apr 2011) $
*
*/
/*****************************************************************************
* AMD Generic Encapsulated Software Architecture
*
* Description: agesaCallouts.c - AGESA Call out functions
*
******************************************************************************
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "cpuRegisters.h"
#include "Dispatcher.h"
#include "cpuServices.h"
#include "Ids.h"
#include "Filecode.h"
#define FILECODE LEGACY_PROC_AGESACALLOUTS_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S - (AGESA ONLY)
*----------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------*/
/**
*
* Call the host environment interface to do the warm or cold reset.
*
* @param[in] ResetType Warm or Cold Reset is requested
* @param[in,out] StdHeader Config header
*
*/
VOID
AgesaDoReset (
IN UINTN ResetType,
IN OUT AMD_CONFIG_PARAMS *StdHeader
)
{
AGESA_STATUS Status;
WARM_RESET_REQUEST Request;
// Clear warm request bit and set state bits to the current post stage
GetWarmResetFlag (StdHeader, &Request);
Request.RequestBit = FALSE;
Request.StateBits = Request.PostStage;
SetWarmResetFlag (StdHeader, &Request);
Status = AmdAgesaCallout (AGESA_DO_RESET, (UINT32)ResetType, (VOID *) StdHeader);
}
/*---------------------------------------------------------------------------------------*/
/**
*
* Call the host environment interface to allocate buffer in main system memory.
*
* @param[in] FcnData
* @param[in,out] AllocParams Heap manager parameters
*
* @return The AGESA Status returned from the callout.
*
*/
AGESA_STATUS
AgesaAllocateBuffer (
IN UINTN FcnData,
IN OUT AGESA_BUFFER_PARAMS *AllocParams
)
{
AGESA_STATUS Status;
Status = AmdAgesaCallout (AGESA_ALLOCATE_BUFFER, (UINT32)FcnData, (VOID *) AllocParams);
return Status;
}
/*---------------------------------------------------------------------------------------*/
/**
* Call the host environment interface to deallocate buffer in main system memory.
*
* @param[in] FcnData
* @param[in,out] DeallocParams Heap Manager parameters
*
* @return The AGESA Status returned from the callout.
*/
AGESA_STATUS
AgesaDeallocateBuffer (
IN UINTN FcnData,
IN OUT AGESA_BUFFER_PARAMS *DeallocParams
)
{
AGESA_STATUS Status;
Status = AmdAgesaCallout (AGESA_DEALLOCATE_BUFFER, (UINT32)FcnData, (VOID *) DeallocParams);
return Status;
}
/*---------------------------------------------------------------------------------------*/
/**
*
* Call the host environment interface to Locate buffer Pointer in main system memory
*
* @param[in] FcnData
* @param[in,out] LocateParams Heap manager parameters
*
* @return The AGESA Status returned from the callout.
*
*/
AGESA_STATUS
AgesaLocateBuffer (
IN UINTN FcnData,
IN OUT AGESA_BUFFER_PARAMS *LocateParams
)
{
AGESA_STATUS Status;
Status = AmdAgesaCallout (AGESA_LOCATE_BUFFER, (UINT32)FcnData, (VOID *) LocateParams);
return Status;
}
/*---------------------------------------------------------------------------------------*/
/**
* Call the host environment interface to launch APs
*
* @param[in] ApicIdOfCore
* @param[in,out] LaunchApParams
*
* @return The AGESA Status returned from the callout.
*
*/
AGESA_STATUS
AgesaRunFcnOnAp (
IN UINTN ApicIdOfCore,
IN AP_EXE_PARAMS *LaunchApParams
)
{
AGESA_STATUS Status;
Status = AmdAgesaCallout (AGESA_RUNFUNC_ONAP, (UINT32)ApicIdOfCore, (VOID *) LaunchApParams);
return Status;
}
/*---------------------------------------------------------------------------------------*/
/**
* Call the host environment interface to read an SPD's content.
*
* @param[in] FcnData
* @param[in,out] ReadSpd
*
* @return The AGESA Status returned from the callout.
*
*/
AGESA_STATUS
AgesaReadSpd (
IN UINTN FcnData,
IN OUT AGESA_READ_SPD_PARAMS *ReadSpd
)
{
AGESA_STATUS Status;
Status = AmdAgesaCallout (AGESA_READ_SPD, (UINT32)FcnData, ReadSpd);
return Status;
}
/*---------------------------------------------------------------------------------------*/
/**
* Call the host environment interface to read an SPD's content.
*
* @param[in] FcnData
* @param[in,out] ReadSpd
*
* @return The AGESA Status returned from the callout.
*
*/
AGESA_STATUS
AgesaReadSpdRecovery (
IN UINTN FcnData,
IN OUT AGESA_READ_SPD_PARAMS *ReadSpd
)
{
AGESA_STATUS Status;
Status = AmdAgesaCallout (AGESA_READ_SPD_RECOVERY, (UINT32)FcnData, ReadSpd);
return Status;
}
/*---------------------------------------------------------------------------------------*/
/**
* Call the host environment interface to provide a user hook opportunity.
*
* @param[in] FcnData
* @param[in,out] MemData
*
* @return The AGESA Status returned from the callout.
*
*/
AGESA_STATUS
AgesaHookBeforeDramInitRecovery (
IN UINTN FcnData,
IN OUT MEM_DATA_STRUCT *MemData
)
{
AGESA_STATUS Status;
Status = AmdAgesaCallout (AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY, (UINT32)FcnData, MemData);
return Status;
}
/*---------------------------------------------------------------------------------------*/
/**
* Call the host environment interface to provide a user hook opportunity.
*
* @param[in] SocketIdModuleId - (SocketID << 8) | ModuleId
* @param[in,out] MemData
*
* @return The AGESA Status returned from the callout.
*
*/
AGESA_STATUS
AgesaHookBeforeDramInit (
IN UINTN SocketIdModuleId,
IN OUT MEM_DATA_STRUCT *MemData
)
{
AGESA_STATUS Status;
Status = AmdAgesaCallout (AGESA_HOOKBEFORE_DRAM_INIT, (UINT32)SocketIdModuleId, MemData);
return Status;
}
/*---------------------------------------------------------------------------------------*/
/**
* Call the host environment interface to provide a user hook opportunity.
*
* @param[in] SocketIdModuleId - (SocketID << 8) | ModuleId
* @param[in,out] MemData
*
* @return The AGESA Status returned from the callout.
*
*/
AGESA_STATUS
AgesaHookBeforeDQSTraining (
IN UINTN SocketIdModuleId,
IN OUT MEM_DATA_STRUCT *MemData
)
{
AGESA_STATUS Status;
Status = AmdAgesaCallout (AGESA_HOOKBEFORE_DQS_TRAINING, (UINT32)SocketIdModuleId, MemData);
return Status;
}
/*---------------------------------------------------------------------------------------*/
/**
* Call the host environment interface to provide a user hook opportunity.
*
* @param[in] FcnData
* @param[in,out] MemData
*
* @return The AGESA Status returned from the callout.
*
*/
AGESA_STATUS
AgesaHookBeforeExitSelfRefresh (
IN UINTN FcnData,
IN OUT MEM_DATA_STRUCT *MemData
)
{
AGESA_STATUS Status;
Status = AmdAgesaCallout (AGESA_HOOKBEFORE_EXIT_SELF_REF, (UINT32)FcnData, MemData);
return Status;
}
/*---------------------------------------------------------------------------------------*/
/**
* Call the host environment interface to provide a user hook opportunity.
*
* @param[in] Data
* @param[in,out] IdsCalloutData
*
* @return The AGESA Status returned from the callout.
*
*/
AGESA_STATUS
AgesaGetIdsData (
IN UINTN Data,
IN OUT IDS_CALLOUT_STRUCT *IdsCalloutData
)
{
AGESA_STATUS Status;
Status = AmdAgesaCallout (AGESA_GET_IDS_INIT_DATA, (UINT32)Data, IdsCalloutData);
return Status;
}
/*----------------------------------------------------------------------------------------*/
/**
* PCIE slot reset control
*
*
*
* @param[in] FcnData Function data
* @param[in] ResetInfo Reset information
* @retval Status Agesa status
*/
AGESA_STATUS
AgesaPcieSlotResetControl (
IN UINTN FcnData,
IN PCIe_SLOT_RESET_INFO *ResetInfo
)
{
AGESA_STATUS Status;
Status = AmdAgesaCallout (AGESA_GNB_PCIE_SLOT_RESET, (UINT32) FcnData, ResetInfo);
return Status;
}
/*----------------------------------------------------------------------------------------*/
/**
* OEM callout function for FCH data override
*
*
* @param[in] FchData FCH data pointer
* @retval Status This feature is not supported
*/
AGESA_STATUS
AgesaFchOemCallout (
IN VOID *FchData
)
{
return AGESA_UNSUPPORTED;
}
/*---------------------------------------------------------------------------------------*/
/**
* Optional call to the host environment interface to change the external Vref for training.
*
* @param[in] SocketIdModuleId - (SocketID << 8) | ModuleId
* @param[in,out] MemData
*
* @return The AGESA Status returned from the callout.
*
*/
AGESA_STATUS
AgesaExternal__TrainVrefChange (
IN UINTN SocketIdModuleId,
IN OUT MEM_DATA_STRUCT *MemData
)
{
AGESA_STATUS Status;
Status = AmdAgesaCallout (AGESA_EXTERNAL____TRAIN_VREF_CHANGE, (UINT32)SocketIdModuleId, MemData);
return Status;
}

393
src/vendorcode/amd/agesa/f15/Legacy/Proc/hobTransfer.c
View File

@ -1,393 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Hob Transfer functions.
*
* Contains code that copy Heap to temp memory or main memory.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU
* @e \$Revision: 56322 $ @e \$Date: 2011-07-11 16:51:42 -0600 (Mon, 11 Jul 2011) $
*
*/
/*
******************************************************************************
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "amdlib.h"
#include "Ids.h"
#include "cpuRegisters.h"
#include "GeneralServices.h"
#include "cpuServices.h"
#include "cpuCacheInit.h"
#include "cpuFamilyTranslation.h"
#include "heapManager.h"
#include "cpuLateInit.h"
#include "Filecode.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G2_PEI)
#define FILECODE LEGACY_PROC_HOBTRANSFER_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P U B L I C F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
extern BUILD_OPT_CFG UserOptions;
/* -----------------------------------------------------------------------------*/
/**
*
* CopyHeapToTempRamAtPost
*
* This function copies BSP heap content to RAM
*
* @param[in,out] StdHeader - Pointer to AMD_CONFIG_PARAMS struct.
*
* @retval AGESA_STATUS
*
*/
AGESA_STATUS
CopyHeapToTempRamAtPost (
IN OUT AMD_CONFIG_PARAMS *StdHeader
)
{
UINT8 *BaseAddressInCache;
UINT8 *BaseAddressInTempMem;
UINT8 *Source;
UINT8 *Destination;
UINT8 AlignTo16ByteInCache;
UINT8 AlignTo16ByteInTempMem;
UINT8 Ignored;
UINT32 SizeOfNodeData;
UINT32 TotalSize;
UINT32 HeapRamFixMtrr;
UINT32 HeapRamVariableMtrr;
UINT32 HeapInCacheOffset;
UINT64 MsrData;
UINT64 VariableMtrrBase;
UINT64 VariableMtrrMask;
UINTN AmdHeapRamAddress;
AGESA_STATUS IgnoredStatus;
BUFFER_NODE *HeapInCache;
BUFFER_NODE *HeapInTempMem;
HEAP_MANAGER *HeapManagerInCache;
HEAP_MANAGER *HeapManagerInTempMem;
CACHE_INFO *CacheInfoPtr;
CPU_SPECIFIC_SERVICES *FamilySpecificServices;
AmdHeapRamAddress = (UINTN) UserOptions.CfgHeapDramAddress;
//
//If the user define address above 1M, Mem Init has already set
//whole available memory as WB cacheable.
//
if (AmdHeapRamAddress < 0x100000) {
// Region below 1MB
// Fixed MTRR region
// turn on modification bit
LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader);
MsrData |= 0x80000;
LibAmdMsrWrite (MSR_SYS_CFG, &MsrData, StdHeader);
if (AmdHeapRamAddress >= 0xC0000) {
//
// 0xC0000 ~ 0xFFFFF
//
HeapRamFixMtrr = (UINT32) (AMD_MTRR_FIX4k_C0000 + ((((UINTN)AmdHeapRamAddress >> 16) & 0x3) * 2));
MsrData = AMD_MTRR_FIX4K_UC_DRAM;
LibAmdMsrWrite (HeapRamFixMtrr, &MsrData, StdHeader);
LibAmdMsrWrite ((HeapRamFixMtrr + 1), &MsrData, StdHeader);
} else if (AmdHeapRamAddress >= 0x80000) {
//
// 0x80000~0xBFFFF
//
HeapRamFixMtrr = (UINT32) (AMD_MTRR_FIX16k_80000 + (((UINTN)AmdHeapRamAddress >> 17) & 0x1));
MsrData = AMD_MTRR_FIX16K_UC_DRAM;
LibAmdMsrWrite (HeapRamFixMtrr, &MsrData, StdHeader);
} else {
//
// 0x0 ~ 0x7FFFF
//
LibAmdMsrRead (AMD_MTRR_FIX64k_00000, &MsrData, StdHeader);
MsrData = MsrData & (~(0xFF << (8 * ((AmdHeapRamAddress >> 16) & 0x7))));
MsrData = MsrData | (AMD_MTRR_FIX64K_UC_DRAM << (8 * (((UINTN)AmdHeapRamAddress >> 16) & 0x7)));
LibAmdMsrWrite (AMD_MTRR_FIX64k_00000, &MsrData, StdHeader);
}
// Turn on MTRR enable bit and turn off modification bit
LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader);
MsrData |= 0x40000;
MsrData &= 0xFFFFFFFFFFF7FFFF;
LibAmdMsrWrite (MSR_SYS_CFG, &MsrData, StdHeader);
} else {
// Region above 1MB
// Variable MTRR region
// Get family specific cache Info
GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (CONST VOID **) &CacheInfoPtr, &Ignored, StdHeader);
// Find an empty MTRRphysBase/MTRRphysMask
for (HeapRamVariableMtrr = AMD_MTRR_VARIABLE_HEAP_BASE;
HeapRamVariableMtrr >= AMD_MTRR_VARIABLE_BASE0;
HeapRamVariableMtrr--) {
LibAmdMsrRead (HeapRamVariableMtrr, &VariableMtrrBase, StdHeader);
LibAmdMsrRead ((HeapRamVariableMtrr + 1), &VariableMtrrMask, StdHeader);
if ((VariableMtrrBase == 0) && (VariableMtrrMask == 0)) {
break;
}
}
if (HeapRamVariableMtrr < AMD_MTRR_VARIABLE_BASE0) {
// All variable MTRR is used.
ASSERT (FALSE);
}
// Set variable MTRR base and mask
// If the address ranges of two or more MTRRs overlap
// and if at least one of the memory types is UC, the UC memory type is used.
VariableMtrrBase = (UINT64) (AmdHeapRamAddress & CacheInfoPtr->HeapBaseMask);
VariableMtrrMask = CacheInfoPtr->VariableMtrrHeapMask & AMD_HEAP_MTRR_MASK;
LibAmdMsrWrite (HeapRamVariableMtrr, &VariableMtrrBase, StdHeader);
LibAmdMsrWrite ((HeapRamVariableMtrr + 1), &VariableMtrrMask, StdHeader);
}
// Copying Heap content
if (IsBsp (StdHeader, &IgnoredStatus)) {
TotalSize = sizeof (HEAP_MANAGER);
SizeOfNodeData = 0;
AlignTo16ByteInTempMem = 0;
BaseAddressInCache = (UINT8 *) (UINTN)StdHeader->HeapBasePtr;
HeapManagerInCache = (HEAP_MANAGER *) BaseAddressInCache;
HeapInCacheOffset = HeapManagerInCache->FirstActiveBufferOffset;
HeapInCache = (BUFFER_NODE *) (BaseAddressInCache + HeapInCacheOffset);
BaseAddressInTempMem = (UINT8 *) (UINTN) UserOptions.CfgHeapDramAddress;
HeapManagerInTempMem = (HEAP_MANAGER *) BaseAddressInTempMem;
HeapInTempMem = (BUFFER_NODE *) (BaseAddressInTempMem + TotalSize);
// copy heap from cache to temp memory.
// only heap with persist great than HEAP_LOCAL_CACHE will be copied.
// Note: Only copy heap with persist greater than HEAP_LOCAL_CACHE.
while (HeapInCacheOffset != AMD_HEAP_INVALID_HEAP_OFFSET) {
if (HeapInCache->Persist > HEAP_LOCAL_CACHE) {
AlignTo16ByteInCache = HeapInCache->PadSize;
AlignTo16ByteInTempMem = (UINT8) ((0x10 - (((UINTN) (VOID *) HeapInTempMem + sizeof (BUFFER_NODE) + SIZE_OF_SENTINEL) & 0xF)) & 0xF);
SizeOfNodeData = HeapInCache->BufferSize - AlignTo16ByteInCache;
TotalSize = (UINT32) (TotalSize + sizeof (BUFFER_NODE) + SizeOfNodeData + AlignTo16ByteInTempMem);
Source = (UINT8 *) HeapInCache + sizeof (BUFFER_NODE) + AlignTo16ByteInCache;
Destination = (UINT8 *) HeapInTempMem + sizeof (BUFFER_NODE) + AlignTo16ByteInTempMem;
LibAmdMemCopy (HeapInTempMem, HeapInCache, sizeof (BUFFER_NODE), StdHeader);
LibAmdMemCopy (Destination, Source, SizeOfNodeData, StdHeader);
HeapInTempMem->OffsetOfNextNode = TotalSize;
HeapInTempMem->BufferSize = SizeOfNodeData + AlignTo16ByteInTempMem;
HeapInTempMem->PadSize = AlignTo16ByteInTempMem;
HeapInTempMem = (BUFFER_NODE *) (BaseAddressInTempMem + TotalSize);
}
HeapInCacheOffset = HeapInCache->OffsetOfNextNode;
HeapInCache = (BUFFER_NODE *) (BaseAddressInCache + HeapInCacheOffset);
}
// initialize heap manager
if (TotalSize == sizeof (HEAP_MANAGER)) {
// heap is empty
HeapManagerInTempMem->UsedSize = sizeof (HEAP_MANAGER);
HeapManagerInTempMem->FirstActiveBufferOffset = AMD_HEAP_INVALID_HEAP_OFFSET;
HeapManagerInTempMem->FirstFreeSpaceOffset = sizeof (HEAP_MANAGER);
} else {
// heap is NOT empty
HeapManagerInTempMem->UsedSize = TotalSize;
HeapManagerInTempMem->FirstActiveBufferOffset = sizeof (HEAP_MANAGER);
HeapManagerInTempMem->FirstFreeSpaceOffset = TotalSize;
HeapInTempMem = (BUFFER_NODE *) (BaseAddressInTempMem + TotalSize - SizeOfNodeData - AlignTo16ByteInTempMem - sizeof (BUFFER_NODE));
HeapInTempMem->OffsetOfNextNode = AMD_HEAP_INVALID_HEAP_OFFSET;
HeapInTempMem = (BUFFER_NODE *) (BaseAddressInTempMem + TotalSize);
}
// heap signature
HeapManagerInCache->Signature = 0x00000000;
HeapManagerInTempMem->Signature = HEAP_SIGNATURE_VALID;
// Free space node
HeapInTempMem->BufferSize = (UINT32) (AMD_HEAP_SIZE_PER_CORE - TotalSize);
HeapInTempMem->OffsetOfNextNode = AMD_HEAP_INVALID_HEAP_OFFSET;
}
return AGESA_SUCCESS;
}
/* -----------------------------------------------------------------------------*/
/**
*
* CopyHeapToMainRamAtPost
*
* This function copies Temp Ram heap content to Main Ram
*
* @param[in,out] StdHeader - Pointer to AMD_CONFIG_PARAMS struct.
*
* @retval AGESA_STATUS
*
*/
AGESA_STATUS
CopyHeapToMainRamAtPost (
IN OUT AMD_CONFIG_PARAMS *StdHeader
)
{
UINT8 *BaseAddressInTempMem;
UINT8 *BaseAddressInMainMem;
UINT8 *Source;
UINT8 *Destination;
UINT8 AlignTo16ByteInTempMem;
UINT8 AlignTo16ByteInMainMem;
UINT8 Ignored;
UINT32 SizeOfNodeData;
UINT32 TotalSize;
UINT32 HeapInTempMemOffset;
UINT32 HeapRamVariableMtrr;
UINT64 VariableMtrrBase;
UINT64 VariableMtrrMask;
AGESA_STATUS IgnoredStatus;
BUFFER_NODE *HeapInTempMem;
BUFFER_NODE *HeapInMainMem;
HEAP_MANAGER *HeapManagerInTempMem;
HEAP_MANAGER *HeapManagerInMainMem;
AGESA_BUFFER_PARAMS AgesaBuffer;
CACHE_INFO *CacheInfoPtr;
CPU_SPECIFIC_SERVICES *FamilySpecificServices;
if (IsBsp (StdHeader, &IgnoredStatus)) {
TotalSize = sizeof (HEAP_MANAGER);
SizeOfNodeData = 0;
AlignTo16ByteInMainMem = 0;
BaseAddressInTempMem = (UINT8 *)(UINTN) StdHeader->HeapBasePtr;
HeapManagerInTempMem = (HEAP_MANAGER *)(UINTN) StdHeader->HeapBasePtr;
HeapInTempMemOffset = HeapManagerInTempMem->FirstActiveBufferOffset;
HeapInTempMem = (BUFFER_NODE *) (BaseAddressInTempMem + HeapInTempMemOffset);
AgesaBuffer.StdHeader = *StdHeader;
AgesaBuffer.BufferHandle = AMD_HEAP_IN_MAIN_MEMORY_HANDLE;
AgesaBuffer.BufferLength = AMD_HEAP_SIZE_PER_CORE;
if (AgesaAllocateBuffer (0, &AgesaBuffer) != AGESA_SUCCESS) {
return AGESA_ERROR;
}
BaseAddressInMainMem = (UINT8 *) AgesaBuffer.BufferPointer;
HeapManagerInMainMem = (HEAP_MANAGER *) BaseAddressInMainMem;
HeapInMainMem = (BUFFER_NODE *) (BaseAddressInMainMem + TotalSize);
LibAmdMemFill (BaseAddressInMainMem, 0x00, AMD_HEAP_SIZE_PER_CORE, StdHeader);
// copy heap from temp memory to main memory.
// only heap with persist great than HEAP_TEMP_MEM will be copied.
// Note: Only copy heap buffers with persist greater than HEAP_TEMP_MEM.
while (HeapInTempMemOffset != AMD_HEAP_INVALID_HEAP_OFFSET) {
if (HeapInTempMem->Persist > HEAP_TEMP_MEM) {
AlignTo16ByteInTempMem = HeapInTempMem->PadSize;
AlignTo16ByteInMainMem = (UINT8) ((0x10 - (((UINTN) (VOID *) HeapInMainMem + sizeof (BUFFER_NODE) + SIZE_OF_SENTINEL) & 0xF)) & 0xF);
SizeOfNodeData = HeapInTempMem->BufferSize - AlignTo16ByteInTempMem;
TotalSize = (UINT32) (TotalSize + sizeof (BUFFER_NODE) + SizeOfNodeData + AlignTo16ByteInMainMem);
Source = (UINT8 *) HeapInTempMem + sizeof (BUFFER_NODE) + AlignTo16ByteInTempMem;
Destination = (UINT8 *) HeapInMainMem + sizeof (BUFFER_NODE) + AlignTo16ByteInMainMem;
LibAmdMemCopy (HeapInMainMem, HeapInTempMem, sizeof (BUFFER_NODE), StdHeader);
LibAmdMemCopy (Destination, Source, SizeOfNodeData, StdHeader);
HeapInMainMem->OffsetOfNextNode = TotalSize;
HeapInMainMem->BufferSize = SizeOfNodeData + AlignTo16ByteInMainMem;
HeapInMainMem->PadSize = AlignTo16ByteInMainMem;
HeapInMainMem = (BUFFER_NODE *) (BaseAddressInMainMem + TotalSize);
}
HeapInTempMemOffset = HeapInTempMem->OffsetOfNextNode;
HeapInTempMem = (BUFFER_NODE *) (BaseAddressInTempMem + HeapInTempMemOffset);
}
// initialize heap manager
if (TotalSize == sizeof (HEAP_MANAGER)) {
// heap is empty
HeapManagerInMainMem->UsedSize = sizeof (HEAP_MANAGER);
HeapManagerInMainMem->FirstActiveBufferOffset = AMD_HEAP_INVALID_HEAP_OFFSET;
HeapManagerInMainMem->FirstFreeSpaceOffset = sizeof (HEAP_MANAGER);
} else {
// heap is NOT empty
HeapManagerInMainMem->UsedSize = TotalSize;
HeapManagerInMainMem->FirstActiveBufferOffset = sizeof (HEAP_MANAGER);
HeapManagerInMainMem->FirstFreeSpaceOffset = TotalSize;
HeapInMainMem = (BUFFER_NODE *) (BaseAddressInMainMem + TotalSize - SizeOfNodeData - AlignTo16ByteInMainMem - sizeof (BUFFER_NODE));
HeapInMainMem->OffsetOfNextNode = AMD_HEAP_INVALID_HEAP_OFFSET;
HeapInMainMem = (BUFFER_NODE *) (BaseAddressInMainMem + TotalSize);
}
// heap signature
HeapManagerInTempMem->Signature = 0x00000000;
HeapManagerInMainMem->Signature = HEAP_SIGNATURE_VALID;
// Free space node
HeapInMainMem->BufferSize = AMD_HEAP_SIZE_PER_CORE - TotalSize;
HeapInMainMem->OffsetOfNextNode = AMD_HEAP_INVALID_HEAP_OFFSET;
}
// if address of heap in temp memory is above 1M, then we must used one variable MTRR.
if ( (UINTN) StdHeader->HeapBasePtr >= 0x100000) {
// Find out which variable MTRR was used in CopyHeapToTempRamAtPost.
GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (CONST VOID **) &CacheInfoPtr, &Ignored, StdHeader);
for (HeapRamVariableMtrr = AMD_MTRR_VARIABLE_HEAP_BASE;
HeapRamVariableMtrr >= AMD_MTRR_VARIABLE_BASE0;
HeapRamVariableMtrr--) {
LibAmdMsrRead (HeapRamVariableMtrr, &VariableMtrrBase, StdHeader);
LibAmdMsrRead ((HeapRamVariableMtrr + 1), &VariableMtrrMask, StdHeader);
if ((VariableMtrrBase == (UINT64) (UINTN) (StdHeader->HeapBasePtr & CacheInfoPtr->HeapBaseMask)) &&
(VariableMtrrMask == (UINT64) (CacheInfoPtr->VariableMtrrHeapMask & AMD_HEAP_MTRR_MASK))) {
break;
}
}
if (HeapRamVariableMtrr >= AMD_MTRR_VARIABLE_BASE0) {
// Clear variable MTRR which set in CopyHeapToTempRamAtPost.
VariableMtrrBase = 0;
VariableMtrrMask = 0;
LibAmdMsrWrite (HeapRamVariableMtrr, &VariableMtrrBase, StdHeader);
LibAmdMsrWrite ((HeapRamVariableMtrr + 1), &VariableMtrrMask, StdHeader);
}
}
return AGESA_SUCCESS;
}

120
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@ -1,120 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Create outline and references for mainpage documentation.
*
* Design guides, maintenance guides, and general documentation, are
* collected using this file onto the documentation mainpage.
* This file contains doxygen comment blocks, only.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Documentation
*
*/
/*
******************************************************************************
*
* Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
/**
* @mainpage
*
* The design and maintenance documentation for AGESA Sample Code is organized as
* follows. On this page, you can reference design guides, maintenance guides, and
* general documentation. Detailed Data Structure, Function, and Interface documentation
* may be found using the Data Structures or Files tabs. See Related Pages for a
* Release content summary, and, if this is not a production release, lists of To Do's,
* Deprecated items, etc.
*
* @subpage starthere "Start Here - Initial Porting and Integration."
*
* @subpage optionmain "Build Configuration and Options Guides and Documentation."
*
* @subpage commonmain "Processor Common Component Guides and Documentation."
*
* @subpage cpumain "CPU Component Guides and Documentation."
*
* @subpage htmain "HT Component Guides and Documentation."
*
* @subpage memmain "MEM Component Guides and Documentation."
*
* @subpage gnbmain "GNB Component Documentation."
*
* @subpage fchmain "FCH Component Documentation."
*
* @subpage idsmain "IDS Component Guides and Documentation."
*
* @subpage recoverymain "Recovery Component Guides and Documentation."
*
*/
/**
* @page starthere Initial Porting and Integration
*
* @par Basic Check List
*
* <ul>
* <li> Copy the \<plat\>Options.c file from the Addendum directory to the platform tip build directory.
* AMD recommends the use of a sub-directory named AGESA to contain these files and the build output files.
* <li> Copy the OptionsIds.h content in the spec to OptionsIds.h in the platform build tip directory
* and make changes to enable the IDS support desired. It is highly recommended to set the following for
* initial integration and development:@n
* @code
* #define IDSOPT_IDS_ENABLED TRUE
* #define IDSOPT_ERROR_TRAP_ENABLED TRUE
* #define IDSOPT_ASSERT_ENABLED TRUE
* @endcode
* <li> Edit and modify the option selections in those two files to meet the needs of the specific platform.
* <li> Set the environment variable AGESA_ROOT to the root folder of the AGESA code.
* <li> Set the environment variable AGESA_OptsDir the platform build tip AGESA directory.
* <li> Generate the doxygen documentation or locate the file arch2008.chm within your AGESA release package.
* </ul>
*
* @par Debugging Using ASSERT and IDS_ERROR_TRAP
*
* While AGESA code uses ::ASSERT and ::IDS_ERROR_TRAP to check for internal errors, these macros can also
* catch and assist debug of wrapper and platform BIOS issues.
*
* When an ::ASSERT fails or an ::IDS_ERROR_TRAP is executed, the AGESA code will enter a halt loop and display a
* Stop Code. A Stop Code is eight hex digits. The first (most significant) four are the FILECODE.
* FILECODEs can be looked up in Filecode.h to determine which file contains the stop macro. Each file has a
* unique code value.
* The least significant digits are the line number in that file.
* For example, 0210 means the macro is on line two hundred ten.
* (see ::IdsErrorStop for more details on stop code display.)
*
* Enabling ::ASSERT and ::IDS_ERROR_TRAP ensure errors are caught and also provide a useful debug assist.
* Comments near each macro use will describe the nature of the error and typical wrapper errors or other
* root causes.
*
* After your wrapper consistently executes ::ASSERT and ::IDS_ERROR_TRAP stop free, you can disable them in
* OptionsIds.h, except for regression testing. IDS is not expected to be enabled in production BIOS builds.
*
*/

55
src/vendorcode/amd/agesa/f15/Makefile.inc
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@ -1,55 +0,0 @@
#
# This file is part of the coreboot project.
#
# Copyright (C) 2012 Advanced Micro Devices, Inc.
# Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com>
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; version 2 of the License.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
## ABSOLUTE AGESA V5 ROOT PATH ##
AGESA_ROOT ?= $(PWD)
AGESA_ROOT = src/vendorcode/amd/agesa/f15
AGESA_AUTOINCLUDES := $(shell find $(AGESA_ROOT)/Proc -type d -exec echo -n "-I"{}" " \;)
AGESA_INC = -I$(src)/vendorcode/amd/include
AGESA_INC += -I$(AGESA_ROOT)
AGESA_INC += -I$(AGESA_ROOT)/../common
AGESA_INC += -I$(AGESA_ROOT)/Include
AGESA_INC += -I$(src)/mainboard/$(MAINBOARDDIR) # OptionsIds.h
BUILDOPTS_INCLUDES = -I$(AGESA_ROOT)/Config $(AGESA_INC) $(AGESA_AUTOINCLUDES)
## AGESA need sse feature ##
CFLAGS_x86_32 += -msse3 -fno-zero-initialized-in-bss -fno-strict-aliasing
CFLAGS_x86_64 += -msse3 -fno-zero-initialized-in-bss -fno-strict-aliasing
# These are invalid, coreboot proper should not require
# use of AGESA internal header files.
CPPFLAGS_x86_ANY =
CPPFLAGS_x86_ANY += -I$(AGESA_ROOT)/Proc/CPU # heapManager.h
CPPFLAGS_x86_ANY += -I$(AGESA_ROOT)/Proc/CPU/Family
CPPFLAGS_x86_32 += $(AGESA_INC) $(CPPFLAGS_x86_ANY)
CPPFLAGS_x86_64 += $(AGESA_INC) $(CPPFLAGS_x86_ANY)
#######################################################################
subdirs-y += Legacy/Proc
subdirs-y += $(dir $(shell cd $(dir); find Proc -name Makefile.inc))
$(obj)/libagesa.fam15.a: $$(libagesa-objs)
@printf " AGESA $(subst $(obj)/,,$(@))\n"
$(AR_libagesa) rcs $@ $+
romstage-libs += $(obj)/libagesa.fam15.a
ramstage-libs += $(obj)/libagesa.fam15.a

126
src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10InitEarlyTable.c
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@ -1,126 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Initialize the Family 10h specific way of running early initialization.
*
* Returns the table of initialization steps to perform at
* AmdInitEarly.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/FAMILY/0x10
* @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
*
*/
/*
******************************************************************************
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "cpuFamilyTranslation.h"
#include "Filecode.h"
#include "cpuEarlyInit.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G2_PEI)
#define FILECODE PROC_CPU_FAMILY_0X10_F10INITEARLYTABLE_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
VOID
GetF10EarlyInitOnCoreTable (
IN CPU_SPECIFIC_SERVICES *FamilyServices,
OUT CONST S_PERFORM_EARLY_INIT_ON_CORE **Table,
IN AMD_CPU_EARLY_PARAMS *EarlyParams,
IN AMD_CONFIG_PARAMS *StdHeader
);
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
extern F_PERFORM_EARLY_INIT_ON_CORE McaInitializationAtEarly;
extern F_PERFORM_EARLY_INIT_ON_CORE SetRegistersFromTablesAtEarly;
extern F_PERFORM_EARLY_INIT_ON_CORE SetBrandIdRegistersAtEarly;
extern F_PERFORM_EARLY_INIT_ON_CORE LocalApicInitializationAtEarly;
extern F_PERFORM_EARLY_INIT_ON_CORE LoadMicrocodePatchAtEarly;
CONST S_PERFORM_EARLY_INIT_ON_CORE ROMDATA F10EarlyInitOnCoreTable[] =
{
{McaInitializationAtEarly, PERFORM_EARLY_ANY_CONDITION},
{SetRegistersFromTablesAtEarly, PERFORM_EARLY_ANY_CONDITION},
{SetBrandIdRegistersAtEarly, PERFORM_EARLY_ANY_CONDITION},
{LocalApicInitializationAtEarly, PERFORM_EARLY_ANY_CONDITION},
{LoadMicrocodePatchAtEarly, PERFORM_EARLY_WARM_RESET},
{NULL, 0}
};
/*------------------------------------------------------------------------------------*/
/**
* Initializer routine that may be invoked at AmdCpuEarly to return the steps that a
* processor that uses the standard initialization steps should take.
*
* @CpuServiceMethod{::F_GET_EARLY_INIT_TABLE}.
*
* @param[in] FamilyServices The current Family Specific Services.
* @param[out] Table Table of appropriate init steps for the executing core.
* @param[in] EarlyParams Service Interface structure to initialize.
* @param[in] StdHeader Opaque handle to standard config header.
*
*/
VOID
GetF10EarlyInitOnCoreTable (
IN CPU_SPECIFIC_SERVICES *FamilyServices,
OUT CONST S_PERFORM_EARLY_INIT_ON_CORE **Table,
IN AMD_CPU_EARLY_PARAMS *EarlyParams,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
*Table = F10EarlyInitOnCoreTable;
}

300
src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10IoCstate.c
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@ -1,300 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_10 IO C-state feature support functions.
*
* Provides the functions necessary to initialize the IO C-state feature.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/F10
* @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
*
*/
/*
******************************************************************************
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "amdlib.h"
#include "Ids.h"
#include "cpuFeatures.h"
#include "cpuIoCstate.h"
#include "cpuF10PowerMgmt.h"
#include "cpuLateInit.h"
#include "cpuRegisters.h"
#include "cpuServices.h"
#include "cpuApicUtilities.h"
#include "cpuFamilyTranslation.h"
#include "CommonReturns.h"
#include "Filecode.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G2_PEI)
#define FILECODE PROC_CPU_FAMILY_0X10_F10IOCSTATE_FILECODE
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
VOID
STATIC
F10InitializeIoCstateOnCore (
IN VOID *CstateBaseMsr,
IN AMD_CONFIG_PARAMS *StdHeader
);
BOOLEAN
F10IsIoCstateFeatureSupported (
IN IO_CSTATE_FAMILY_SERVICES *IoCstateServices,
IN UINT32 Socket,
IN AMD_CONFIG_PARAMS *StdHeader
);
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
extern CPU_FAMILY_SUPPORT_TABLE IoCstateFamilyServiceTable;
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------*/
/**
* Enable IO Cstate on a family 10h CPU.
*
* @param[in] IoCstateServices Pointer to this CPU's IO Cstate family services.
* @param[in] EntryPoint Timepoint designator.
* @param[in] PlatformConfig Contains the runtime modifiable feature input data.
* @param[in] StdHeader Config Handle for library, services.
*
* @return AGESA_SUCCESS Always succeeds.
*
*/
AGESA_STATUS
STATIC
F10InitializeIoCstate (
IN IO_CSTATE_FAMILY_SERVICES *IoCstateServices,
IN UINT64 EntryPoint,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT64 LocalMsrRegister;
AP_TASK TaskPtr;
if ((EntryPoint & CPU_FEAT_AFTER_PM_INIT) != 0) {
// Initialize MSRC001_0073[CstateAddr] on each core to a region of
// the IO address map with 8 consecutive available addresses.
LocalMsrRegister = 0;
((CSTATE_ADDRESS_MSR *) &LocalMsrRegister)->CstateAddr = PlatformConfig->CStateIoBaseAddress;
TaskPtr.FuncAddress.PfApTaskI = F10InitializeIoCstateOnCore;
TaskPtr.DataTransfer.DataSizeInDwords = 2;
TaskPtr.DataTransfer.DataPtr = &LocalMsrRegister;
TaskPtr.DataTransfer.DataTransferFlags = 0;
TaskPtr.ExeFlags = WAIT_FOR_CORE;
ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, NULL);
}
return AGESA_SUCCESS;
}
/*---------------------------------------------------------------------------------------*/
/**
* Enable CState on a family 10h core.
*
* @param[in] CstateBaseMsr MSR value to write to C001_0073 as determined by core 0.
* @param[in] StdHeader Config Handle for library, services.
*
*/
VOID
STATIC
F10InitializeIoCstateOnCore (
IN VOID *CstateBaseMsr,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
// Initialize MSRC001_0073[CstateAddr] on each core
LibAmdMsrWrite (MSR_CSTATE_ADDRESS, (UINT64 *) CstateBaseMsr, StdHeader);
}
/*---------------------------------------------------------------------------------------*/
/**
* Returns the size of CST object
*
* @param[in] IoCstateServices IO Cstate services.
* @param[in] PlatformConfig Contains the runtime modifiable feature input data
* @param[in] StdHeader Config Handle for library, services.
*
* @retval CstObjSize Size of CST Object
*
*/
UINT32
STATIC
F10GetAcpiCstObj (
IN IO_CSTATE_FAMILY_SERVICES *IoCstateServices,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
return (CST_HEADER_SIZE + CST_BODY_SIZE);
}
/*---------------------------------------------------------------------------------------*/
/**
* Routine to generate the C-State ACPI objects
*
* @param[in] IoCstateServices IO Cstate services.
* @param[in] LocalApicId Local Apic Id for each core.
* @param[in, out] **PstateAcpiBufferPtr Pointer to the Acpi Buffer Pointer.
* @param[in] StdHeader Config Handle for library, services.
*
*/
VOID
STATIC
F10CreateAcpiCstObj (
IN IO_CSTATE_FAMILY_SERVICES *IoCstateServices,
IN UINT8 LocalApicId,
IN OUT VOID **PstateAcpiBufferPtr,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT64 MsrData;
CST_HEADER_STRUCT *CstHeaderPtr;
CST_BODY_STRUCT *CstBodyPtr;
// Read from MSR C0010073 to obtain CstateAddr
LibAmdMsrRead (MSR_CSTATE_ADDRESS, &MsrData, StdHeader);
ASSERT ((((CSTATE_ADDRESS_MSR *) &MsrData)->CstateAddr != 0) &&
(((CSTATE_ADDRESS_MSR *) &MsrData)->CstateAddr <= 0xFFF8));
// Typecast the pointer
CstHeaderPtr = (CST_HEADER_STRUCT *) *PstateAcpiBufferPtr;
// Set CST Header
CstHeaderPtr->NameOpcode = NAME_OPCODE;
CstHeaderPtr->CstName_a__ = CST_NAME__;
CstHeaderPtr->CstName_a_C = CST_NAME_C;
CstHeaderPtr->CstName_a_S = CST_NAME_S;
CstHeaderPtr->CstName_a_T = CST_NAME_T;
// Typecast the pointer
CstHeaderPtr++;
CstBodyPtr = (CST_BODY_STRUCT *) CstHeaderPtr;
// Set CST Body
CstBodyPtr->PkgOpcode = PACKAGE_OPCODE;
CstBodyPtr->PkgLength = CST_LENGTH;
CstBodyPtr->PkgElements = CST_NUM_OF_ELEMENTS;
CstBodyPtr->BytePrefix = BYTE_PREFIX_OPCODE;
CstBodyPtr->Count = CST_COUNT;
CstBodyPtr->PkgOpcode2 = PACKAGE_OPCODE;
CstBodyPtr->PkgLength2 = CST_PKG_LENGTH;
CstBodyPtr->PkgElements2 = CST_PKG_ELEMENTS;
CstBodyPtr->BufferOpcode = BUFFER_OPCODE;
CstBodyPtr->BufferLength = CST_SUBPKG_LENGTH;
CstBodyPtr->BufferElements = CST_SUBPKG_ELEMENTS;
CstBodyPtr->BufferOpcode2 = BUFFER_OPCODE;
CstBodyPtr->GdrOpcode = GENERIC_REG_DESCRIPTION;
CstBodyPtr->GdrLength = CST_GDR_LENGTH;
CstBodyPtr->AddrSpaceId = GDR_ASI_SYSTEM_IO;
CstBodyPtr->RegBitWidth = 0x08;
CstBodyPtr->RegBitOffset = 0x00;
CstBodyPtr->AddressSize = GDR_ASZ_BYTE_ACCESS;
CstBodyPtr->RegisterAddr = ((CSTATE_ADDRESS_MSR *) &MsrData)->CstateAddr;
CstBodyPtr->EndTag = 0x0079;
CstBodyPtr->BytePrefix2 = BYTE_PREFIX_OPCODE;
CstBodyPtr->Type = CST_C2_TYPE;
CstBodyPtr->WordPrefix = WORD_PREFIX_OPCODE;
CstBodyPtr->Latency = 0x4B;
CstBodyPtr->DWordPrefix = DWORD_PREFIX_OPCODE;
CstBodyPtr->Power = 0;
CstBodyPtr++;
//Update the pointer
*PstateAcpiBufferPtr = CstBodyPtr;
}
/*---------------------------------------------------------------------------------------*/
/**
* Routine to check whether IO Cstate should be supported.
*
* @param[in] IoCstateServices IO Cstate services.
* @param[in] Socket Zero-based socket number.
* @param[in] StdHeader Config Handle for library, services.
*
* @retval TRUE Support IO Cstate.
* @retval FALSE Do not support IO Cstate.
*
*/
BOOLEAN
F10IsIoCstateFeatureSupported (
IN IO_CSTATE_FAMILY_SERVICES *IoCstateServices,
IN UINT32 Socket,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT64 LocalMsrRegister;
CPUID_DATA CpuId;
CPU_LOGICAL_ID LogicalId;
GetLogicalIdOfCurrentCore (&LogicalId, StdHeader);
// Only Rev.E processor with CPB enabled and ucode 010000BF or later loaded
// MSR_C001_0073 can be programmed
if ((LogicalId.Revision & AMD_F10_Ex) != 0) {
LibAmdCpuidRead (AMD_CPUID_APM, &CpuId, StdHeader);
if (((CpuId.EDX_Reg & 0x00000200) >> 9) == 1) {
LibAmdMsrRead (MSR_PATCH_LEVEL, &LocalMsrRegister, StdHeader);
if ((LocalMsrRegister & 0xffffffff) >= 0x010000BF) {
return TRUE;
}
}
}
return FALSE;
}
CONST IO_CSTATE_FAMILY_SERVICES ROMDATA F10IoCstateSupport =
{
0,
F10IsIoCstateFeatureSupported,
F10InitializeIoCstate,
F10GetAcpiCstObj,
F10CreateAcpiCstObj,
(PF_IO_CSTATE_IS_CSD_GENERATED) CommonReturnFalse
};

1537
src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10MultiLinkPciTables.c
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src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10PackageType.h
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@ -1,84 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_10 Package Type Definitions
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/F10
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $
*
*/
/*
******************************************************************************
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef _F10_PACKAGE_TYPE_H_
#define _F10_PACKAGE_TYPE_H_
/*---------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*---------------------------------------------------------------------------------------
*/
// Below equates are defined to cooperate with LibAmdGetPackageType.
#define PACKAGE_TYPE_FR2_FR5_FR6 (1 << 0)
#define PACKAGE_TYPE_AM2R2_AM3 (1 << 1)
#define PACKAGE_TYPE_S1G3_S1G4 (1 << 2)
#define PACKAGE_TYPE_G34 (1 << 3)
#define PACKAGE_TYPE_ASB2 (1 << 4)
#define PACKAGE_TYPE_C32 (1 << 5)
#define PACKAGE_TYPE_FR2 PACKAGE_TYPE_FR2_FR5_FR6
#define PACKAGE_TYPE_FR5 PACKAGE_TYPE_FR2_FR5_FR6
#define PACKAGE_TYPE_FR6 PACKAGE_TYPE_FR2_FR5_FR6
#define PACKAGE_TYPE_S1G3 PACKAGE_TYPE_S1G3_S1G4
#define PACKAGE_TYPE_S1G4 PACKAGE_TYPE_S1G3_S1G4
/*---------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*---------------------------------------------------------------------------------------
*/
#endif // _F10_PACKAGE_TYPE_H_

176
src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10PmAsymBoostInit.c
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@ -1,176 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_10 Asymmetric Boost Initialization
*
* Performs the "BIOS Configuration for Asymmetric Boost" as
* described in the BKDG.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/F10
* @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
*
*/
/*
******************************************************************************
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "amdlib.h"
#include "cpuRegisters.h"
#include "cpuApicUtilities.h"
#include "cpuServices.h"
#include "GeneralServices.h"
#include "cpuFamilyTranslation.h"
#include "cpuF10PowerMgmt.h"
#include "F10PmAsymBoostInit.h"
#include "OptionMultiSocket.h"
#include "Filecode.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G2_PEI)
#define FILECODE PROC_CPU_FAMILY_0X10_F10PMASYMBOOSTINIT_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
VOID
STATIC
SetAsymBoost (
IN VOID *AsymBoostRegister,
IN AMD_CONFIG_PARAMS *StdHeader
);
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------*/
/**
* Family 10h core 0 entry point for performing the "Asymmetric Boost
* Configuration" algorithm.
*
* The algorithm is as follows:
* // Determine whether the processor support boost
* if (CPUID CPUID Fn8000_0007[CPB]==1)&& CPUID Fn8000_0008[NC]==5) {
* Core0 MSRC001_0064[CpuFid] += F3x10C[AsymmetricBoostCore0]
* Core1 MSRC001_0064[CpuFid] += F3x10C[AsymmetricBoostCore1]
* Core2 MSRC001_0064[CpuFid] += F3x10C[AsymmetricBoostCore2]
* Core3 MSRC001_0064[CpuFid] += F3x10C[AsymmetricBoostCore3]
* Core4 MSRC001_0064[CpuFid] += F3x10C[AsymmetricBoostCore4]
* Core5 MSRC001_0064[CpuFid] += F3x10C[AsymmetricBoostCore5]
* }
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[in] CpuEarlyParamsPtr Service related parameters (unused).
* @param[in] StdHeader Config handle for library and services.
*
*/
VOID
F10PmAsymBoostInit (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
AP_TASK TaskPtr;
UINT32 LocalPciRegister;
PCI_ADDR PciAddress;
CPUID_DATA CpuidData;
// Check if CPB is supported. if yes, skip boosted p-state.
LibAmdCpuidRead (AMD_CPUID_APM, &CpuidData, StdHeader);
if (((CpuidData.EDX_Reg & 0x00000200) >> 9) == 1) {
LibAmdCpuidRead (CPUID_LONG_MODE_ADDR, &CpuidData, StdHeader);
if ((CpuidData.ECX_Reg & 0x000000FF) == 5) {
OptionMultiSocketConfiguration.GetCurrPciAddr (&PciAddress, StdHeader);
// Read F3x10C [Boost Offset]
PciAddress.AddressValue = F3x10C_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
TaskPtr.FuncAddress.PfApTaskI = SetAsymBoost;
TaskPtr.ExeFlags = WAIT_FOR_CORE;
TaskPtr.DataTransfer.DataTransferFlags = 0;
TaskPtr.DataTransfer.DataSizeInDwords = 1;
TaskPtr.DataTransfer.DataPtr = &LocalPciRegister;
ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, CpuEarlyParamsPtr);
}
}
}
/*---------------------------------------------------------------------------------------*/
/**
* Set Asymmetric Boost.
*
* This function set Asymmetric Boost.
*
* @param[in] AsymBoostRegister Contains the value of Asymmetric Boost register
* @param[in] StdHeader Config handle for library and services
*
*/
VOID
STATIC
SetAsymBoost (
IN VOID *AsymBoostRegister,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT8 ControlByte;
UINT32 Core;
UINT32 Ignored;
UINT64 MsrValue;
AGESA_STATUS IgnoredSts;
IdentifyCore (StdHeader, &Ignored, &Ignored, &Core, &IgnoredSts);
ControlByte = (UINT8) ((Core & 0xFF) * 2);
LibAmdMsrRead (MSR_PSTATE_0, &MsrValue, StdHeader);
// Bits 5:0
((PSTATE_MSR *) &MsrValue)->CpuFid += ((*(UINT32*) AsymBoostRegister >> ControlByte) & 0x3);
LibAmdMsrWrite (MSR_PSTATE_0, &MsrValue, StdHeader);
}

78
src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10PmAsymBoostInit.h
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@ -1,78 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_10 Asymmetric Boost Initialization
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/F10
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $
*
*/
/*
******************************************************************************
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef _CPU_F10_ASYM_BOOST_H_
#define _CPU_F10_ASYM_BOOST_H_
/*---------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*---------------------------------------------------------------------------------------
*/
VOID
F10PmAsymBoostInit (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr,
IN AMD_CONFIG_PARAMS *StdHeader
);
#endif // _CPU_F10_ASYM_BOOST_H_

243
src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10PmDualPlaneOnlySupport.c
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@ -1,243 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_10 Dual-plane Only Support
*
* Performs the "BIOS Configuration for Dual-plane Only Support" as
* described in the BKDG.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/F10
* @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
*
*/
/*
******************************************************************************
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "amdlib.h"
#include "cpuRegisters.h"
#include "cpuApicUtilities.h"
#include "cpuServices.h"
#include "GeneralServices.h"
#include "cpuFamilyTranslation.h"
#include "cpuF10PowerMgmt.h"
#include "F10PmDualPlaneOnlySupport.h"
#include "F10PackageType.h"
#include "OptionMultiSocket.h"
#include "Filecode.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G2_PEI)
#define FILECODE PROC_CPU_FAMILY_0X10_F10PMDUALPLANEONLYSUPPORT_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
UINT32
STATIC
SetPstateMSR (
IN VOID *CPB,
IN AMD_CONFIG_PARAMS *StdHeader
);
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------*/
/**
* Family 10h core 0 entry point for performing the "Dual-plane Only Support" algorithm.
*
* The algorithm is as follows:
* // Determine whether algorithm applies to this processor
* if (CPUID Fn8000_0001_EBX[PkgType] == 0001b && (revision C or E) {
* // Determine whether processor is supported in this infrastructure
* if (((F3x1FC[DualPlaneOnly] == 1) && (this is a dual-plane platform))
* || ((F3x1FC[AM3r2Only] == 1) && (this is an AM3r2 platform))) {
* // Fixup the P-state MSRs
* for (each core in the system) {
* if (CPUID Fn8000_0007[CPB]) {
* Copy MSRC001_0065 as MinPstate;
* Copy MSRC001_0068 to MSRC001_0065;
* Copy MinPstate to MSRC001_0068;
* } else {
* Copy MSRC001_0068 to MSRC001_0064;
* Program MSRC001_0068 = 0;
* } // endif
* for (each MSR in MSRC001_00[68:64]) {
* if (value in MSRC001_00[68:64][IddValue] != 0) {
* Set PstateEn in current MSR to 1;
* } // endif
* } // endfor
* } // endfor
* Set F3xDC[PstateMaxVal] = lowest-performance enabled P-state;
* Set F3xA8[PopDownPstate] = lowest-performance enabled P-state;
* Set F3x64[HtcPstateLimit] = lowest-performance enabled P-state;
* } // endif
* } // endif
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[in] CpuEarlyParamsPtr Service related parameters (unused).
* @param[in] StdHeader Config handle for library and services.
*
*/
VOID
F10PmDualPlaneOnlySupport (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
AP_TASK TaskPtr;
UINT32 CPB;
UINT32 Core;
UINT32 Pvimode;
UINT32 LowestPsEn;
UINT32 LocalPciRegister;
UINT32 ActiveCores;
UINT32 ProcessorPackageType;
PCI_ADDR PciAddress;
CPUID_DATA CpuidData;
CPU_LOGICAL_ID LogicalId;
OptionMultiSocketConfiguration.GetCurrPciAddr (&PciAddress, StdHeader);
// get the package type
ProcessorPackageType = LibAmdGetPackageType (StdHeader);
GetLogicalIdOfCurrentCore (&LogicalId, StdHeader);
if (((LogicalId.Revision & (AMD_F10_Cx | AMD_F10_Ex)) != 0) && ((ProcessorPackageType & PACKAGE_TYPE_AM2R2_AM3) != 0)) {
PciAddress.AddressValue = PRCT_INFO_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
PciAddress.AddressValue = PW_CTL_MISC_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &Pvimode, StdHeader);
if ((((LocalPciRegister & 0x80000000) != 0) && (((POWER_CTRL_MISC_REGISTER *) &Pvimode)->PviMode == 0))
|| ((LocalPciRegister & 0x04000000) != 0)) {
CPB = 0;
LibAmdCpuidRead (AMD_CPUID_APM, &CpuidData, StdHeader);
if (((CpuidData.EDX_Reg & 0x00000200) >> 9) == 1) {
CPB = 1;
}
TaskPtr.FuncAddress.PfApTaskIO = SetPstateMSR;
TaskPtr.ExeFlags = TASK_HAS_OUTPUT | WAIT_FOR_CORE;
TaskPtr.DataTransfer.DataTransferFlags = 0;
TaskPtr.DataTransfer.DataSizeInDwords = 1;
TaskPtr.DataTransfer.DataPtr = &CPB;
GetActiveCoresInCurrentSocket (&ActiveCores, StdHeader);
for (Core = 1; Core < (UINT8) ActiveCores; ++Core) {
ApUtilRunCodeOnSocketCore ((UINT8)0, (UINT8)Core, &TaskPtr, StdHeader);
}
LowestPsEn = ApUtilTaskOnExecutingCore (&TaskPtr, StdHeader, (VOID *) CpuEarlyParamsPtr);
PciAddress.AddressValue = CPTC2_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
((CLK_PWR_TIMING_CTRL2_REGISTER *) &LocalPciRegister)->PstateMaxVal = LowestPsEn;
LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
PciAddress.AddressValue = POPUP_PSTATE_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
((POPUP_PSTATE_REGISTER *) &LocalPciRegister)->PopDownPstate = LowestPsEn;
LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
PciAddress.AddressValue = HTC_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
((HTC_REGISTER *) &LocalPciRegister)->HtcPstateLimit = LowestPsEn;
LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
}
}
}
/*---------------------------------------------------------------------------------------*/
/**
* Set P-State MSR.
*
* This function set the P-state MSRs per each core in the system.
*
* @param[in] CPB Contains the value of Asymmetric Boost register
* @param[in] StdHeader Config handle for library and services
*
* @return Return the lowest-performance enabled P-state
*/
UINT32
STATIC
SetPstateMSR (
IN VOID *CPB,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 dtemp;
UINT32 LowestPsEn;
UINT64 MsrValue;
UINT64 MinMsrValue;
if (*(UINT32*) CPB != 0) {
LibAmdMsrRead (MSR_PSTATE_1, &MinMsrValue, StdHeader);
LibAmdMsrRead (MSR_PSTATE_4, &MsrValue, StdHeader);
LibAmdMsrWrite (MSR_PSTATE_1, &MsrValue, StdHeader);
LibAmdMsrWrite (MSR_PSTATE_4, &MinMsrValue, StdHeader);
} else {
LibAmdMsrRead (MSR_PSTATE_4, &MsrValue, StdHeader);
LibAmdMsrWrite (MSR_PSTATE_0, &MsrValue, StdHeader);
MsrValue = 0;
LibAmdMsrWrite (MSR_PSTATE_4, &MsrValue, StdHeader);
}
LowestPsEn = 0;
for (dtemp = MSR_PSTATE_0; dtemp <= MSR_PSTATE_4; dtemp++) {
LibAmdMsrRead (dtemp, &MsrValue, StdHeader);
if (((PSTATE_MSR *) &MsrValue)->IddValue != 0) {
MsrValue = MsrValue | BIT63;
LibAmdMsrWrite (dtemp, &MsrValue, StdHeader);
LowestPsEn = dtemp - MSR_PSTATE_0;
}
}
return (LowestPsEn);
}

78
src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10PmDualPlaneOnlySupport.h
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@ -1,78 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_10 BIOS Configuration for Dual-plane Only Support
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/F10
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $
*
*/
/*
******************************************************************************
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef _CPU_F10_DUAL_PLANE_ONLY_SUPPORT_H_
#define _CPU_F10_DUAL_PLANE_ONLY_SUPPORT_H_
/*---------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*---------------------------------------------------------------------------------------
*/
VOID
F10PmDualPlaneOnlySupport (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr,
IN AMD_CONFIG_PARAMS *StdHeader
);
#endif // _CPU_F10_DUAL_PLANE_ONLY_SUPPORT_H_

296
src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10PmNbCofVidInit.c
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@ -1,296 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_10 NB COF VID Initialization
*
* Performs the "BIOS Northbridge COF and VID Configuration" as
* described in the BKDG.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/F10
* @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
*
*/
/*
******************************************************************************
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "amdlib.h"
#include "cpuRegisters.h"
#include "cpuF10PowerMgmt.h"
#include "cpuApicUtilities.h"
#include "OptionMultiSocket.h"
#include "cpuServices.h"
#include "GeneralServices.h"
#include "cpuFamilyTranslation.h"
#include "cpuF10Utilities.h"
#include "F10PmNbCofVidInit.h"
#include "Filecode.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G2_PEI)
#define FILECODE PROC_CPU_FAMILY_0X10_F10PMNBCOFVIDINIT_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/// Structure used for performing the steps outlined in
/// the NB COFVID configuration sequence
typedef struct {
UINT8 NewNbVid; ///< Destination NB VID code
BOOLEAN NbVidUpdateAll; ///< Status of NbVidUpdateAll
} NB_COF_VID_INIT_WARM;
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
VOID
STATIC
PmNbCofVidInitP0P1Core (
IN VOID *NewNbVid,
IN AMD_CONFIG_PARAMS *StdHeader
);
VOID
STATIC
PmNbCofVidInitWarmCore (
IN VOID *FunctionData,
IN AMD_CONFIG_PARAMS *StdHeader
);
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
/*---------------------------------------------------------------------------------------*/
/**
* Family 10h core 0 entry point for performing the "Northbridge COF and
* VID Configuration" algorithm.
*
* The steps are as follows:
* 1. Determine if the algorithm is necessary by checking if all NB FIDs
* match in the coherent fabric. If so, check to see if NbCofVidUpdate
* is zero for all CPUs. If that is also true, no further steps are
* necessary. If not + cold reset, proceed to step 2. If not + warm
* reset, proceed to step 8.
* 2. Determine NewNbVid & NewNbFid.
* 3. Copy Startup Pstate settings to P0/P1 MSRs on all local cores.
* 4. Copy NewNbVid to P0 NbVid on all local cores.
* 5. Transition to P1 on all local cores.
* 6. Transition to P0 on local core 0 only.
* 7. Copy NewNbFid to F3xD4[NbFid], set NbFidEn, and issue a warm reset.
* 8. Update all enabled Pstate MSRs' NbVids according to NbVidUpdateAll
* on all local cores.
* 9. Transition to Startup Pstate on all local cores.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[in] CpuEarlyParamsPtr Service related parameters (unused).
* @param[in] StdHeader Config handle for library and services.
*
*/
VOID
F10PmNbCofVidInit (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
BOOLEAN PerformNbCofVidCfg;
BOOLEAN NotUsed;
BOOLEAN SystemNbCofsMatch;
UINT8 NewNbFid;
UINT8 NewNbVid;
UINT32 Core;
UINT32 SystemNbCof;
UINT32 AndMask;
UINT32 OrMask;
UINT32 Ignored;
UINT32 NewNbVoltage;
UINT32 FrequencyDivisor;
WARM_RESET_REQUEST Request;
AP_TASK TaskPtr;
PCI_ADDR PciAddress;
NB_COF_VID_INIT_WARM FunctionData;
PerformNbCofVidCfg = TRUE;
OptionMultiSocketConfiguration.GetSystemNbPstateSettings ((UINT32) 0, &CpuEarlyParamsPtr->PlatformConfig, &SystemNbCof, &FrequencyDivisor, &SystemNbCofsMatch, &NotUsed, StdHeader);
if (SystemNbCofsMatch) {
if (!OptionMultiSocketConfiguration.GetSystemNbCofVidUpdate (StdHeader)) {
PerformNbCofVidCfg = FALSE;
}
}
if (PerformNbCofVidCfg) {
OptionMultiSocketConfiguration.GetCurrPciAddr (&PciAddress, StdHeader);
GetCurrentCore (&Core, StdHeader);
ASSERT (Core == 0);
// get NewNbVid
FamilySpecificServices->GetNbPstateInfo (FamilySpecificServices,
&CpuEarlyParamsPtr->PlatformConfig,
&PciAddress,
(UINT32) 0,
&Ignored,
&Ignored,
&NewNbVoltage,
StdHeader);
ASSERT (((1550000 - NewNbVoltage) % 12500) == 0);
NewNbVid = (UINT8) ((1550000 - NewNbVoltage) / 12500);
ASSERT (NewNbVid < 0x80);
if (!(IsWarmReset (StdHeader))) {
// determine NewNbFid
NewNbFid = (UINT8) ((SystemNbCof / 200) - 4);
TaskPtr.FuncAddress.PfApTaskI = PmNbCofVidInitP0P1Core;
TaskPtr.DataTransfer.DataSizeInDwords = 1;
TaskPtr.DataTransfer.DataPtr = &NewNbVid;
TaskPtr.DataTransfer.DataTransferFlags = 0;
TaskPtr.ExeFlags = 0;
ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, CpuEarlyParamsPtr);
// Transition core 0 to P0 and wait for change to complete
FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) 0, (BOOLEAN) TRUE, StdHeader);
PciAddress.Address.Register = CPTC0_REG;
AndMask = 0xFFFFFFFF;
((CLK_PWR_TIMING_CTRL_REGISTER *) &AndMask)->NbFid = 0;
OrMask = 0x00000000;
((CLK_PWR_TIMING_CTRL_REGISTER *) &OrMask)->NbFid = NewNbFid;
((CLK_PWR_TIMING_CTRL_REGISTER *) &OrMask)->NbFidEn = 1;
OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader);
// warm reset request
GetWarmResetFlag (StdHeader, &Request);
Request.RequestBit = TRUE;
Request.StateBits = Request.PostStage - 1;
SetWarmResetFlag (StdHeader, &Request);
} else {
// warm reset path
FunctionData.NewNbVid = NewNbVid;
FamilySpecificServices->IsNbCofInitNeeded (FamilySpecificServices, &PciAddress, &FunctionData.NbVidUpdateAll, StdHeader);
TaskPtr.FuncAddress.PfApTaskI = PmNbCofVidInitWarmCore;
TaskPtr.DataTransfer.DataSizeInDwords = SIZE_IN_DWORDS (NB_COF_VID_INIT_WARM);
TaskPtr.DataTransfer.DataPtr = &FunctionData;
TaskPtr.DataTransfer.DataTransferFlags = 0;
TaskPtr.ExeFlags = WAIT_FOR_CORE;
ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, CpuEarlyParamsPtr);
}
} // skip whole algorithm
}
/*---------------------------------------------------------------------------------------*/
/**
* Cold reset support routine for F10PmNbCofVidInit.
*
* This function implements steps 3, 4, & 5 on each core.
*
* @param[in] NewNbVid NewNbVid determined by core 0 in step 2.
* @param[in] StdHeader Config handle for library and services.
*
*/
VOID
STATIC
PmNbCofVidInitP0P1Core (
IN VOID *NewNbVid,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT8 NumBoostStates;
UINT32 MsrAddress;
UINT64 LocalMsrRegister;
CPU_SPECIFIC_SERVICES *FamilySpecificServices;
NumBoostStates = F10GetNumberOfBoostedPstatesOnCore (StdHeader);
GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
LibAmdMsrRead (MSR_COFVID_STS, &LocalMsrRegister, StdHeader);
MsrAddress = (UINT32) ((((COFVID_STS_MSR *) &LocalMsrRegister)->StartupPstate) + PS_REG_BASE);
LibAmdMsrRead (MsrAddress, &LocalMsrRegister, StdHeader);
LibAmdMsrWrite ((UINT32) (PS_REG_BASE + 1 + NumBoostStates), &LocalMsrRegister, StdHeader);
((PSTATE_MSR *) &LocalMsrRegister)->NbVid = *(UINT8 *) NewNbVid;
LibAmdMsrWrite (PS_REG_BASE + NumBoostStates, &LocalMsrRegister, StdHeader);
FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) 1, (BOOLEAN) FALSE, StdHeader);
}
/*---------------------------------------------------------------------------------------*/
/**
* Warm reset support routine for F10PmNbCofVidInit.
*
* This function implements steps 8 & 9 on each core.
*
* @param[in] FunctionData Contains NewNbVid determined by core 0 in step
* 2, and NbVidUpdateAll.
* @param[in] StdHeader Config handle for library and services.
*
*/
VOID
STATIC
PmNbCofVidInitWarmCore (
IN VOID *FunctionData,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 MsrAddress;
UINT64 LocalMsrRegister;
CPU_SPECIFIC_SERVICES *FamilySpecificServices;
GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
for (MsrAddress = PS_REG_BASE; MsrAddress <= PS_MAX_REG; MsrAddress++) {
LibAmdMsrRead (MsrAddress, &LocalMsrRegister, StdHeader);
if (((PSTATE_MSR *) &LocalMsrRegister)->IddValue != 0) {
if ((((PSTATE_MSR *) &LocalMsrRegister)->NbDid == 0) || ((NB_COF_VID_INIT_WARM *) FunctionData)->NbVidUpdateAll) {
((PSTATE_MSR *) &LocalMsrRegister)->NbVid = ((NB_COF_VID_INIT_WARM *) FunctionData)->NewNbVid;
LibAmdMsrWrite (MsrAddress, &LocalMsrRegister, StdHeader);
}
}
}
}

77
src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10PmNbCofVidInit.h
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@ -1,77 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_10 NB COF VID Initialization
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/F10
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $
*
*/
/*
******************************************************************************
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef _CPU_F10_PM_NB_COF_VID_INIT_H_
#define _CPU_F10_PM_NB_COF_VID_INIT_H_
/*---------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*---------------------------------------------------------------------------------------
*/
VOID
F10PmNbCofVidInit (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr,
IN AMD_CONFIG_PARAMS *StdHeader
);
#endif // _CPU_F10_PM_NB_COF_VID_INIT_H_

185
src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10PmNbPstateInit.c
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@ -1,185 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_10 NB Pstate Initialization
*
* Performs the action described in F3x1F0[NbPstate] as
* described in the BKDG.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/F10
* @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
*
*/
/*
******************************************************************************
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "amdlib.h"
#include "cpuRegisters.h"
#include "cpuF10PowerMgmt.h"
#include "cpuApicUtilities.h"
#include "GeneralServices.h"
#include "cpuFamilyTranslation.h"
#include "F10PmNbPstateInit.h"
#include "OptionMultiSocket.h"
#include "Filecode.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G2_PEI)
#define FILECODE PROC_CPU_FAMILY_0X10_F10PMNBPSTATEINIT_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/// Structure used for modifying the P-state
/// MSRs on fuse enable CPUs.
typedef struct {
UINT8 NbVid1; ///< Destination NB VID code
UINT8 NbPstate; ///< Status of NbVidUpdateAll
} NB_PSTATE_INIT;
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
VOID
STATIC
PmNbPstateInitCore (
IN VOID *NbPstateParams,
IN AMD_CONFIG_PARAMS *StdHeader
);
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------*/
/**
* Family 10h core 0 entry point for performing the actions described in the
* description of F3x1F0[NbPstate].
*
* If F3x1F0[NbPstate] is non zero, it specifies the highest performance
* P-state in which to enable NbDid. Each core must loop through their
* P-state MSRs, enabling NbDid and changing NbVid to a lower voltage.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[in] CpuEarlyParamsPtr Service related parameters (unused).
* @param[in] StdHeader Config handle for library and services.
*
*/
VOID
F10PmNbPstateInit (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 Core;
UINT32 LocalPciRegister;
AP_TASK TaskPtr;
PCI_ADDR PciAddress;
NB_PSTATE_INIT ApParams;
if (FamilySpecificServices->IsNbPstateEnabled (FamilySpecificServices, &CpuEarlyParamsPtr->PlatformConfig, StdHeader)) {
if (CpuEarlyParamsPtr->PlatformConfig.PlatformProfile.PlatformPowerPolicy == BatteryLife) {
OptionMultiSocketConfiguration.GetCurrPciAddr (&PciAddress, StdHeader);
GetCurrentCore (&Core, StdHeader);
ASSERT (Core == 0);
PciAddress.Address.Function = FUNC_3;
PciAddress.Address.Register = 0x1F0;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
if ((LocalPciRegister & 0x00070000) != 0) {
ApParams.NbPstate = (UINT8) ((LocalPciRegister & 0x00070000) >> 16);
ASSERT (ApParams.NbPstate < NM_PS_REG);
PciAddress.Address.Function = FUNC_4;
PciAddress.Address.Register = 0x1F4;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
ApParams.NbVid1 = (UINT8) ((LocalPciRegister & 0x00003F80) >> 7);
TaskPtr.FuncAddress.PfApTaskI = PmNbPstateInitCore;
TaskPtr.DataTransfer.DataSizeInDwords = SIZE_IN_DWORDS (NB_PSTATE_INIT);
TaskPtr.DataTransfer.DataPtr = &ApParams;
TaskPtr.DataTransfer.DataTransferFlags = 0;
TaskPtr.ExeFlags = WAIT_FOR_CORE;
ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, CpuEarlyParamsPtr);
}
}
}
}
/*---------------------------------------------------------------------------------------*/
/**
* Support routine for F10PmNbPstateInit.
*
* This function modifies NbVid and NbDid on each core.
*
* @param[in] NbPstateParams Appropriate NbVid1 and NbPstate as determined by core 0.
* @param[in] StdHeader Config handle for library and services.
*
*/
VOID
STATIC
PmNbPstateInitCore (
IN VOID *NbPstateParams,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 MsrAddress;
UINT64 LocalMsrRegister;
for (MsrAddress = (PS_REG_BASE + ((NB_PSTATE_INIT *) NbPstateParams)->NbPstate); MsrAddress <= PS_MAX_REG; MsrAddress++) {
LibAmdMsrRead (MsrAddress, &LocalMsrRegister, StdHeader);
if (((PSTATE_MSR *) &LocalMsrRegister)->PsEnable == 1) {
((PSTATE_MSR *) &LocalMsrRegister)->NbDid = 1;
((PSTATE_MSR *) &LocalMsrRegister)->NbVid = ((NB_PSTATE_INIT *) NbPstateParams)->NbVid1;
LibAmdMsrWrite (MsrAddress, &LocalMsrRegister, StdHeader);
}
}
}

77
src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10PmNbPstateInit.h
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@ -1,77 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_10 NB P-State Initialization
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/F10
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $
*
*/
/*
******************************************************************************
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef _CPU_F10_PM_NB_PSTATE_INIT_H_
#define _CPU_F10_PM_NB_PSTATE_INIT_H_
/*---------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*---------------------------------------------------------------------------------------
*/
VOID
F10PmNbPstateInit (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr,
IN AMD_CONFIG_PARAMS *StdHeader
);
#endif // _CPU_F10_PM_NB_PSTATE_INIT_H_

2251
src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10SingleLinkPciTables.c
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34
src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/Makefile.inc
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@ -1,34 +0,0 @@
libagesa-y += F10InitEarlyTable.c
libagesa-y += F10IoCstate.c
libagesa-y += F10MultiLinkPciTables.c
libagesa-y += F10PmAsymBoostInit.c
libagesa-y += F10PmDualPlaneOnlySupport.c
libagesa-y += F10PmNbCofVidInit.c
libagesa-y += F10PmNbPstateInit.c
libagesa-y += F10SingleLinkPciTables.c
libagesa-y += cpuCommonF10Utilities.c
libagesa-y += cpuF10BrandId.c
libagesa-y += cpuF10BrandIdAm3.c
libagesa-y += cpuF10BrandIdAsb2.c
libagesa-y += cpuF10BrandIdC32.c
libagesa-y += cpuF10BrandIdFr1207.c
libagesa-y += cpuF10BrandIdG34.c
libagesa-y += cpuF10BrandIdS1g3.c
libagesa-y += cpuF10BrandIdS1g4.c
libagesa-y += cpuF10CacheDefaults.c
libagesa-y += cpuF10CacheFlushOnHalt.c
libagesa-y += cpuF10Cpb.c
libagesa-y += cpuF10Dmi.c
libagesa-y += cpuF10EarlyInit.c
libagesa-y += cpuF10FeatureLeveling.c
libagesa-y += cpuF10HtPhyTables.c
libagesa-y += cpuF10MsrTables.c
libagesa-y += cpuF10PciTables.c
libagesa-y += cpuF10PowerCheck.c
libagesa-y += cpuF10PowerMgmtSystemTables.c
libagesa-y += cpuF10PowerPlane.c
libagesa-y += cpuF10Pstate.c
libagesa-y += cpuF10SoftwareThermal.c
libagesa-y += cpuF10Utilities.c
libagesa-y += cpuF10WheaInitDataTables.c
libagesa-y += cpuF10WorkaroundsTable.c

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src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000c5.c
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src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000d9.c
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516
src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/F10RevDL3Features.c
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@ -1,516 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_10 RevD L3 dependent feature support functions.
*
* Provides the functions necessary to initialize L3 dependent feature.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/F10
* @e \$Revision: 60552 $ @e \$Date: 2011-10-17 18:50:55 -0600 (Mon, 17 Oct 2011) $
*
*/
/*
******************************************************************************
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/*
*----------------------------------------------------------------------------
* MODULES USED
*
*----------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "amdlib.h"
#include "Ids.h"
#include "CommonReturns.h"
#include "cpuRegisters.h"
#include "cpuF10PowerMgmt.h"
#include "cpuLateInit.h"
#include "cpuServices.h"
#include "GeneralServices.h"
#include "cpuFamilyTranslation.h"
#include "cpuL3Features.h"
#include "F10PackageType.h"
#include "Filecode.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G2_PEI)
#define FILECODE PROC_CPU_FAMILY_0X10_REVD_F10REVDL3FEATURES_FILECODE
/*----------------------------------------------------------------------------
* DEFINITIONS AND MACROS
*
*----------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------
* TYPEDEFS AND STRUCTURES
*
*----------------------------------------------------------------------------
*/
/**
* The family 10h background scrubber context structure.
*
* These fields need to be saved, modified, then restored
* per die as part of HT Assist initialization.
*/
typedef struct {
UINT32 DramScrub:5; ///< DRAM scrub rate
UINT32 :3; ///< Reserved
UINT32 L3Scrub:5; ///< L3 scrub rate
UINT32 :3; ///< Reserved
UINT32 Redirect:1; ///< DRAM scrubber redirect enable
UINT32 :15; ///< Reserved
} F10_SCRUB_CONTEXT;
/*----------------------------------------------------------------------------
* PROTOTYPES OF LOCAL FUNCTIONS
*
*----------------------------------------------------------------------------
*/
BOOLEAN
F10IsNonOptimalConfig (
IN L3_FEATURE_FAMILY_SERVICES *L3FeatureServices,
IN UINT32 Socket,
IN AMD_CONFIG_PARAMS *StdHeader
);
/*----------------------------------------------------------------------------
* EXPORTED FUNCTIONS
*
*----------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------*/
/**
* Check to see if the input CPU supports L3 dependent features.
*
* @param[in] L3FeatureServices L3 Feature family services.
* @param[in] Socket Processor socket to check.
* @param[in] StdHeader Config Handle for library, services.
* @param[in] PlatformConfig Contains the runtime modifiable feature input data.
*
* @retval TRUE L3 dependent features are supported.
* @retval FALSE L3 dependent features are not supported.
*
*/
BOOLEAN
STATIC
F10IsL3FeatureSupported (
IN L3_FEATURE_FAMILY_SERVICES *L3FeatureServices,
IN UINT32 Socket,
IN AMD_CONFIG_PARAMS *StdHeader,
IN PLATFORM_CONFIGURATION *PlatformConfig
)
{
UINT32 Module;
UINT32 LocalPciRegister;
BOOLEAN IsSupported;
PCI_ADDR PciAddress;
AGESA_STATUS IgnoredStatus;
IsSupported = FALSE;
if (PlatformConfig->PlatformProfile.UseHtAssist) {
for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredStatus)) {
PciAddress.Address.Function = FUNC_3;
PciAddress.Address.Register = NB_CAPS_REG;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
if (((NB_CAPS_REGISTER *) &LocalPciRegister)->L3Capable == 1) {
IsSupported = TRUE;
}
break;
}
}
}
return IsSupported;
}
/*---------------------------------------------------------------------------------------*/
/**
* Check to see if the input CPU supports HT Assist.
*
* @param[in] L3FeatureServices L3 Feature family services.
* @param[in] PlatformConfig Contains the runtime modifiable feature input data.
* @param[in] StdHeader Config Handle for library, services.
*
* @retval TRUE HT Assist is supported.
* @retval FALSE HT Assist cannot be enabled.
*
*/
BOOLEAN
STATIC
F10IsHtAssistSupported (
IN L3_FEATURE_FAMILY_SERVICES *L3FeatureServices,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
BOOLEAN IsSupported;
UINT32 CpuCount;
AP_MAILBOXES ApMailboxes;
IsSupported = FALSE;
if (PlatformConfig->PlatformProfile.UseHtAssist) {
CpuCount = GetNumberOfProcessors (StdHeader);
ASSERT (CpuCount != 0);
if (CpuCount == 1) {
GetApMailbox (&ApMailboxes.ApMailInfo.Info, StdHeader);
if (ApMailboxes.ApMailInfo.Fields.ModuleType != 0) {
IsSupported = TRUE;
}
} else if (CpuCount > 1) {
IsSupported = TRUE;
}
}
return IsSupported;
}
/*---------------------------------------------------------------------------------------*/
/**
* Enable the Probe filter feature.
*
* @param[in] L3FeatureServices L3 Feature family services.
* @param[in] Socket Processor socket to check.
* @param[in] StdHeader Config Handle for library, services.
*
*/
VOID
STATIC
F10HtAssistInit (
IN L3_FEATURE_FAMILY_SERVICES *L3FeatureServices,
IN UINT32 Socket,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 Module;
UINT32 LocalPciRegister;
PCI_ADDR PciAddress;
AGESA_STATUS IgnoredStatus;
for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredStatus)) {
PciAddress.Address.Function = FUNC_3;
PciAddress.Address.Register = L3_CACHE_PARAM_REG;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
((L3_CACHE_PARAM_REGISTER *) &LocalPciRegister)->L3TagInit = 1;
LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
do {
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
} while (((L3_CACHE_PARAM_REGISTER *) &LocalPciRegister)->L3TagInit != 0);
PciAddress.Address.Register = PROBE_FILTER_CTRL_REG;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
((PROBE_FILTER_CTRL_REGISTER *) &LocalPciRegister)->PFMode = 0;
LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
F10RevDProbeFilterCritical (PciAddress, LocalPciRegister);
do {
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
} while (((PROBE_FILTER_CTRL_REGISTER *) &LocalPciRegister)->PFInitDone != 1);
IDS_OPTION_HOOK (IDS_HT_ASSIST, &PciAddress, StdHeader);
}
}
}
/*---------------------------------------------------------------------------------------*/
/**
* Save the current settings of the scrubbers, and disabled them.
*
* @param[in] L3FeatureServices L3 Feature family services.
* @param[in] Socket Processor socket to check.
* @param[in] ScrubSettings Location to store current L3 scrubber settings.
* @param[in] StdHeader Config Handle for library, services.
*
*/
VOID
STATIC
F10GetL3ScrubCtrl (
IN L3_FEATURE_FAMILY_SERVICES *L3FeatureServices,
IN UINT32 Socket,
IN UINT32 ScrubSettings[L3_SCRUBBER_CONTEXT_ARRAY_SIZE],
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 Module;
UINT32 ScrubCtrl;
UINT32 ScrubAddr;
PCI_ADDR PciAddress;
AGESA_STATUS IgnoredStatus;
for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredStatus)) {
ASSERT (Module < L3_SCRUBBER_CONTEXT_ARRAY_SIZE);
PciAddress.Address.Function = FUNC_3;
PciAddress.Address.Register = DRAM_SCRUB_ADDR_LOW_REG;
LibAmdPciRead (AccessWidth32, PciAddress, &ScrubAddr, StdHeader);
PciAddress.Address.Register = SCRUB_RATE_CTRL_REG;
LibAmdPciRead (AccessWidth32, PciAddress, &ScrubCtrl, StdHeader);
((F10_SCRUB_CONTEXT *) &ScrubSettings[Module])->DramScrub =
((SCRUB_RATE_CTRL_REGISTER *) &ScrubCtrl)->DramScrub;
((F10_SCRUB_CONTEXT *) &ScrubSettings[Module])->L3Scrub =
((SCRUB_RATE_CTRL_REGISTER *) &ScrubCtrl)->L3Scrub;
((F10_SCRUB_CONTEXT *) &ScrubSettings[Module])->Redirect =
((DRAM_SCRUB_ADDR_LOW_REGISTER *) &ScrubAddr)->ScrubReDirEn;
((SCRUB_RATE_CTRL_REGISTER *) &ScrubCtrl)->DramScrub = 0;
((SCRUB_RATE_CTRL_REGISTER *) &ScrubCtrl)->L3Scrub = 0;
((DRAM_SCRUB_ADDR_LOW_REGISTER *) &ScrubAddr)->ScrubReDirEn = 0;
LibAmdPciWrite (AccessWidth32, PciAddress, &ScrubCtrl, StdHeader);
PciAddress.Address.Register = DRAM_SCRUB_ADDR_LOW_REG;
LibAmdPciWrite (AccessWidth32, PciAddress, &ScrubAddr, StdHeader);
}
}
}
/*---------------------------------------------------------------------------------------*/
/**
* Restore the initial settings for the scrubbers.
*
* @param[in] L3FeatureServices L3 Feature family services.
* @param[in] Socket Processor socket to check.
* @param[in] ScrubSettings Location to store current L3 scrubber settings.
* @param[in] StdHeader Config Handle for library, services.
*
*/
VOID
STATIC
F10SetL3ScrubCtrl (
IN L3_FEATURE_FAMILY_SERVICES *L3FeatureServices,
IN UINT32 Socket,
IN UINT32 ScrubSettings[L3_SCRUBBER_CONTEXT_ARRAY_SIZE],
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 Module;
UINT32 LocalPciRegister;
PCI_ADDR PciAddress;
AGESA_STATUS IgnoredStatus;
for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredStatus)) {
ASSERT (Module < L3_SCRUBBER_CONTEXT_ARRAY_SIZE);
PciAddress.Address.Function = FUNC_3;
PciAddress.Address.Register = SCRUB_RATE_CTRL_REG;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
((SCRUB_RATE_CTRL_REGISTER *) &LocalPciRegister)->DramScrub =
((F10_SCRUB_CONTEXT *) &ScrubSettings[Module])->DramScrub;
((SCRUB_RATE_CTRL_REGISTER *) &LocalPciRegister)->L3Scrub =
((F10_SCRUB_CONTEXT *) &ScrubSettings[Module])->L3Scrub;
LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
PciAddress.Address.Register = DRAM_SCRUB_ADDR_LOW_REG;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
((DRAM_SCRUB_ADDR_LOW_REGISTER *) &LocalPciRegister)->ScrubReDirEn =
((F10_SCRUB_CONTEXT *) &ScrubSettings[Module])->Redirect;
LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
}
}
}
/*---------------------------------------------------------------------------------------*/
/**
* Set MSR bits required for L3 dependent features on each core.
*
* @param[in] L3FeatureServices L3 feature family services.
* @param[in] HtAssistEnabled Indicates whether Ht Assist is enabled.
* @param[in] StdHeader Config Handle for library, services.
*
*/
VOID
STATIC
F10HookDisableCache (
IN L3_FEATURE_FAMILY_SERVICES *L3FeatureServices,
IN BOOLEAN HtAssistEnabled,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT64 LocalMsrRegister;
LibAmdMsrRead (MSR_BU_CFG2, &LocalMsrRegister, StdHeader);
LocalMsrRegister |= BIT42;
LibAmdMsrWrite (MSR_BU_CFG2, &LocalMsrRegister, StdHeader);
}
/*---------------------------------------------------------------------------------------*/
/**
* Hook before L3 features initialization sequence.
*
* @param[in] L3FeatureServices L3 Feature family services.
* @param[in] Socket Processor socket to check.
* @param[in] StdHeader Config Handle for library, services.
*
*/
VOID
STATIC
F10HookBeforeInit (
IN L3_FEATURE_FAMILY_SERVICES *L3FeatureServices,
IN UINT32 Socket,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 Module;
UINT32 LocalPciRegister;
UINT32 PfCtrlRegister;
PCI_ADDR PciAddress;
CPU_LOGICAL_ID LogicalId;
AGESA_STATUS IgnoredStatus;
UINT32 PackageType;
GetLogicalIdOfSocket (Socket, &LogicalId, StdHeader);
PackageType = LibAmdGetPackageType (StdHeader);
LocalPciRegister = 0;
((PROBE_FILTER_CTRL_REGISTER *) &LocalPciRegister)->PFWayNum = 2;
((PROBE_FILTER_CTRL_REGISTER *) &LocalPciRegister)->PFSubCacheEn = 15;
((PROBE_FILTER_CTRL_REGISTER *) &LocalPciRegister)->PFLoIndexHashEn = 1;
for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredStatus)) {
PciAddress.Address.Function = FUNC_3;
PciAddress.Address.Register = PROBE_FILTER_CTRL_REG;
LibAmdPciRead (AccessWidth32, PciAddress, &PfCtrlRegister, StdHeader);
((PROBE_FILTER_CTRL_REGISTER *) &LocalPciRegister)->PFPreferredSORepl =
((PROBE_FILTER_CTRL_REGISTER *) &PfCtrlRegister)->PFPreferredSORepl;
LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
// Assumption: all socket use the same CPU package.
if (((LogicalId.Revision & AMD_F10_D0) != 0) && (PackageType == PACKAGE_TYPE_C32)) {
// Apply erratum #384
// Set F2x11C[13:12] = 11b
PciAddress.Address.Function = FUNC_2;
PciAddress.Address.Register = 0x11C;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
LocalPciRegister |= 0x3000;
LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
}
}
}
}
/*---------------------------------------------------------------------------------------*/
/**
* Check to see if the input CPU is running in the optimal configuration.
*
* @param[in] L3FeatureServices L3 Feature family services.
* @param[in] Socket Processor socket to check.
* @param[in] StdHeader Config Handle for library, services.
*
* @retval TRUE HT Assist is running sub-optimally.
* @retval FALSE HT Assist is running optimally.
*
*/
BOOLEAN
F10IsNonOptimalConfig (
IN L3_FEATURE_FAMILY_SERVICES *L3FeatureServices,
IN UINT32 Socket,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
BOOLEAN IsNonOptimal;
BOOLEAN IsMemoryPresent;
UINT32 Module;
UINT32 LocalPciRegister;
PCI_ADDR PciAddress;
AGESA_STATUS IgnoredStatus;
IsNonOptimal = FALSE;
for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredStatus)) {
IsMemoryPresent = FALSE;
PciAddress.Address.Function = FUNC_2;
PciAddress.Address.Register = DRAM_CFG_HI_REG0;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
if (((DRAM_CFG_HI_REGISTER *) &LocalPciRegister)->MemClkFreqVal == 1) {
IsMemoryPresent = TRUE;
if (((DRAM_CFG_HI_REGISTER *) &LocalPciRegister)->MemClkFreq < 4) {
IsNonOptimal = TRUE;
break;
}
}
PciAddress.Address.Register = DRAM_CFG_HI_REG1;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
if (((DRAM_CFG_HI_REGISTER *) &LocalPciRegister)->MemClkFreqVal == 1) {
IsMemoryPresent = TRUE;
if (((DRAM_CFG_HI_REGISTER *) &LocalPciRegister)->MemClkFreq < 4) {
IsNonOptimal = TRUE;
break;
}
}
if (!IsMemoryPresent) {
IsNonOptimal = TRUE;
break;
}
}
}
return IsNonOptimal;
}
CONST L3_FEATURE_FAMILY_SERVICES ROMDATA F10L3Features =
{
0,
F10IsL3FeatureSupported,
F10GetL3ScrubCtrl,
F10SetL3ScrubCtrl,
F10HookBeforeInit,
(PF_L3_FEATURE_AFTER_INIT) CommonVoid,
F10HookDisableCache,
(PF_L3_FEATURE_ENABLE_CACHE) CommonVoid,
F10IsHtAssistSupported,
F10HtAssistInit,
F10IsNonOptimalConfig,
(PF_ATM_MODE_IS_SUPPORTED) CommonReturnFalse,
(PF_ATM_MODE_INIT) CommonVoid
};

282
src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/F10RevDMsgBasedC1e.c
View File

@ -1,282 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_10 RevD Message-Based C1e feature support functions.
*
* Provides the functions necessary to initialize the message-based C1e feature.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/F10
* @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
*
*/
/*
******************************************************************************
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "amdlib.h"
#include "cpuRegisters.h"
#include "cpuFamilyTranslation.h"
#include "cpuFeatures.h"
#include "cpuServices.h"
#include "GeneralServices.h"
#include "cpuMsgBasedC1e.h"
#include "cpuApicUtilities.h"
#include "cpuF10PowerMgmt.h"
#include "OptionMultiSocket.h"
#include "Filecode.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G2_PEI)
#define FILECODE PROC_CPU_FAMILY_0X10_REVD_F10REVDMSGBASEDC1E_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
VOID
STATIC
F10InitializeMsgBasedC1eOnCore (
IN VOID *BmStsAddress,
IN AMD_CONFIG_PARAMS *StdHeader
);
BOOLEAN
STATIC
IsDramScrubberEnabled (
IN PCI_ADDR PciAddress,
IN AMD_CONFIG_PARAMS *StdHeader
);
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
/*---------------------------------------------------------------------------------------*/
/**
* Should message-based C1e be enabled
*
* @param[in] MsgBasedC1eServices Pointer to this CPU's HW C1e family services.
* @param[in] Socket Processor socket to check.
* @param[in] StdHeader Config Handle for library, services.
*
* @retval TRUE HW C1e is supported.
*
*/
BOOLEAN
STATIC
F10IsMsgBasedC1eSupported (
IN MSG_BASED_C1E_FAMILY_SERVICES *MsgBasedC1eServices,
IN UINT32 Socket,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
CPU_LOGICAL_ID LogicalId;
GetLogicalIdOfSocket (Socket, &LogicalId, StdHeader);
return ((BOOLEAN) (((LogicalId.Revision) & AMD_F10_GT_D0) != 0));
}
/*---------------------------------------------------------------------------------------*/
/**
* Core 0 task to enable message-based C1e on a family 10h CPU.
*
* @param[in] MsgBasedC1eServices Pointer to this CPU's HW C1e family services.
* @param[in] EntryPoint Timepoint designator.
* @param[in] PlatformConfig Contains the runtime modifiable feature input data.
* @param[in] StdHeader Config Handle for library, services.
*
* @return AGESA_SUCCESS Always succeeds.
*
*/
AGESA_STATUS
STATIC
F10InitializeMsgBasedC1e (
IN MSG_BASED_C1E_FAMILY_SERVICES *MsgBasedC1eServices,
IN UINT64 EntryPoint,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 AndMask;
UINT32 Core;
UINT32 Module;
UINT32 OrMask;
UINT32 LocalPciRegister;
UINT32 Socket;
AP_TASK TaskPtr;
PCI_ADDR PciAddress;
AGESA_STATUS IgnoredSts;
if ((EntryPoint & (CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_AFTER_RESUME_MTRR_SYNC)) != 0) {
// Note that this core 0 does NOT have the ability to launch
// any of its cores. Attempting to do so could lead to a system
// hang.
// Set F3xA0[IdleExitEn] = 1
PciAddress.Address.Function = FUNC_3;
PciAddress.Address.Register = PW_CTL_MISC_REG;
AndMask = 0xFFFFFFFF;
OrMask = 0;
((POWER_CTRL_MISC_REGISTER *) &OrMask)->IdleExitEn = 1;
OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F3xA0
// Erratum #610, BIOS should set F3x1B8[5]
PciAddress.Address.Register = 0x1B8;
OrMask = 0x00000020;
OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F3x1B8
// Set F3x188[EnStpGntOnFlushMaskWakeup] = 1
PciAddress.Address.Register = NB_EXT_CFG_LO_REG;
OrMask = 0;
((NB_EXT_CFG_LO_REGISTER *) &OrMask)->EnStpGntOnFlushMaskWakeup = 1;
OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F3x188
// Set F3xD4[MTC1eEn] = 1, F3xD4[CacheFlushImmOnAllHalt] = 1
// Set F3xD4[StutterScrubEn] = 1 if scrubbing is enabled
((CLK_PWR_TIMING_CTRL_REGISTER *) &AndMask)->StutterScrubEn = 0;
OrMask = 0;
((CLK_PWR_TIMING_CTRL_REGISTER *) &OrMask)->MTC1eEn = 1;
((CLK_PWR_TIMING_CTRL_REGISTER *) &OrMask)->CacheFlushImmOnAllHalt = 1;
IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts);
for (Module = 0; Module < (UINT8)GetPlatformNumberOfModules (); Module++) {
if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts)) {
PciAddress.Address.Function = FUNC_3;
PciAddress.Address.Register = CPTC0_REG;
if (IsDramScrubberEnabled (PciAddress, StdHeader)) {
((CLK_PWR_TIMING_CTRL_REGISTER *) &OrMask)->StutterScrubEn = 1;
} else {
((CLK_PWR_TIMING_CTRL_REGISTER *) &OrMask)->StutterScrubEn = 0;
}
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
LocalPciRegister &= AndMask;
LocalPciRegister |= OrMask;
LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
}
}
} else if (EntryPoint == CPU_FEAT_AFTER_PM_INIT) {
// At early, this core 0 can launch its subordinate cores.
TaskPtr.FuncAddress.PfApTaskI = F10InitializeMsgBasedC1eOnCore;
TaskPtr.DataTransfer.DataSizeInDwords = 1;
TaskPtr.DataTransfer.DataPtr = &PlatformConfig->C1ePlatformData;
TaskPtr.DataTransfer.DataTransferFlags = 0;
TaskPtr.ExeFlags = WAIT_FOR_CORE;
ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, NULL);
}
return AGESA_SUCCESS;
}
/*---------------------------------------------------------------------------------------*/
/**
* Enable message-based C1e on a family 10h core.
*
* @param[in] BmStsAddress System I/O address of the bus master status bit.
* @param[in] StdHeader Config Handle for library, services.
*
*/
VOID
STATIC
F10InitializeMsgBasedC1eOnCore (
IN VOID *BmStsAddress,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT64 LocalMsrRegister;
// Set MSRC001_0055[SmiOnCmpHalt] = 0, MSRC001_0055[C1eOnCmpHalt] = 0
LibAmdMsrRead (MSR_INTPEND, &LocalMsrRegister, StdHeader);
((INTPEND_MSR *) &LocalMsrRegister)->SmiOnCmpHalt = 0;
((INTPEND_MSR *) &LocalMsrRegister)->C1eOnCmpHalt = 0;
((INTPEND_MSR *) &LocalMsrRegister)->BmStsClrOnHltEn = 1;
((INTPEND_MSR *) &LocalMsrRegister)->IntrPndMsgDis = 0;
((INTPEND_MSR *) &LocalMsrRegister)->IntrPndMsg = 0;
((INTPEND_MSR *) &LocalMsrRegister)->IoMsgAddr = (UINT64) *((UINT32 *) BmStsAddress);
LibAmdMsrWrite (MSR_INTPEND, &LocalMsrRegister, StdHeader);
// Set MSRC001_0015[HltXSpCycEn] = 1
LibAmdMsrRead (MSR_HWCR, &LocalMsrRegister, StdHeader);
LocalMsrRegister |= BIT12;
LibAmdMsrWrite (MSR_HWCR, &LocalMsrRegister, StdHeader);
}
/*---------------------------------------------------------------------------------------*/
/**
* Check to see if the DRAM background scrubbers are enabled or not.
*
* @param[in] PciAddress Address of F10 socket/module to check.
* @param[in] StdHeader Config Handle for library, services.
*
* @retval TRUE Memory scrubbers are enabled on the current node.
* @retval FALSE Memory scrubbers are disabled on the current node.
*/
BOOLEAN
STATIC
IsDramScrubberEnabled (
IN PCI_ADDR PciAddress,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 LocalPciRegister;
PciAddress.Address.Function = FUNC_3;
PciAddress.Address.Register = 0x58;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
return ((BOOLEAN) ((LocalPciRegister & 0x1F) != 0));
}
CONST MSG_BASED_C1E_FAMILY_SERVICES ROMDATA F10MsgBasedC1e =
{
0,
F10IsMsgBasedC1eSupported,
F10InitializeMsgBasedC1e
};

455
src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/F10RevDUtilities.c
View File

@ -1,455 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_10 revision Dx specific utility functions.
*
* Provides numerous utility functions specific to family 10h rev D.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/F10
* @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
*
*/
/*
******************************************************************************
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "amdlib.h"
#include "Ids.h"
#include "cpuRegisters.h"
#include "cpuFamilyTranslation.h"
#include "cpuF10PowerMgmt.h"
#include "GeneralServices.h"
#include "cpuEarlyInit.h"
#include "cpuRegisters.h"
#include "OptionMultiSocket.h"
#include "Filecode.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G2_PEI)
#define FILECODE PROC_CPU_FAMILY_0X10_REVD_F10REVDUTILITIES_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
BOOLEAN
F10CommonRevDSetDownCoreRegister (
IN CPU_CORE_LEVELING_FAMILY_SERVICES *FamilySpecificServices,
IN UINT32 *Socket,
IN UINT32 *Module,
IN UINT32 *LeveledCores,
IN CORE_LEVELING_TYPE CoreLevelMode,
IN AMD_CONFIG_PARAMS *StdHeader
);
BOOLEAN
F10CommonRevDGetProcIddMax (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN UINT8 Pstate,
OUT UINT32 *ProcIddMax,
IN AMD_CONFIG_PARAMS *StdHeader
);
BOOLEAN
F10CommonRevDGetNbCofVidUpdate (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN PCI_ADDR *PciAddress,
OUT BOOLEAN *NbVidUpdateAll,
IN AMD_CONFIG_PARAMS *StdHeader
);
BOOLEAN
F10CommonRevDGetNbPstateInfo (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN PCI_ADDR *PciAddress,
IN UINT32 NbPstate,
OUT UINT32 *FreqNumeratorInMHz,
OUT UINT32 *FreqDivisor,
OUT UINT32 *VoltageInuV,
IN AMD_CONFIG_PARAMS *StdHeader
);
AGESA_STATUS
F10RevDGetMinMaxNbFrequency (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN PCI_ADDR *PciAddress,
OUT UINT32 *MinFreqInMHz,
OUT UINT32 *MaxFreqInMHz,
IN AMD_CONFIG_PARAMS *StdHeader
);
UINT8
F10CommonRevDGetNumberOfPhysicalCores (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CONFIG_PARAMS *StdHeader
);
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------*/
/**
* Set down core register on a revision D processor.
*
* This function set F3x190 Downcore Control Register[5:0]
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[in] Socket Socket ID.
* @param[in] Module Module ID in socket.
* @param[in] LeveledCores Number of core.
* @param[in] CoreLevelMode Core level mode.
* @param[in] StdHeader Header for library and services.
*
* @retval TRUE Down Core register is updated.
* @retval FALSE Down Core register is not updated.
*/
BOOLEAN
F10CommonRevDSetDownCoreRegister (
IN CPU_CORE_LEVELING_FAMILY_SERVICES *FamilySpecificServices,
IN UINT32 *Socket,
IN UINT32 *Module,
IN UINT32 *LeveledCores,
IN CORE_LEVELING_TYPE CoreLevelMode,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 TempVar32_a;
UINT32 CoreDisableBits;
PCI_ADDR PciAddress;
BOOLEAN IsUpdated;
AGESA_STATUS AgesaStatus;
IsUpdated = FALSE;
switch (*LeveledCores) {
case 1:
CoreDisableBits = DOWNCORE_MASK_SINGLE;
break;
case 2:
CoreDisableBits = DOWNCORE_MASK_DUAL;
break;
case 3:
CoreDisableBits = DOWNCORE_MASK_TRI;
break;
case 4:
CoreDisableBits = DOWNCORE_MASK_FOUR;
break;
case 5:
CoreDisableBits = DOWNCORE_MASK_FIVE;
break;
default:
CoreDisableBits = 0;
break;
}
if (CoreDisableBits != 0) {
if (GetPciAddress (StdHeader, (UINT8) *Socket, (UINT8) *Module, &PciAddress, &AgesaStatus)) {
PciAddress.Address.Function = FUNC_3;
PciAddress.Address.Register = NORTH_BRIDGE_CAPABILITIES_REG;
LibAmdPciRead (AccessWidth32, PciAddress, &TempVar32_a, StdHeader);
TempVar32_a = ((TempVar32_a >> 12) & 0x3) | ((TempVar32_a >> 13) & 0x4);
if (TempVar32_a == 0) {
CoreDisableBits &= 0x1;
} else if (TempVar32_a == 1) {
CoreDisableBits &= 0x3;
} else if (TempVar32_a == 2) {
CoreDisableBits &= 0x7;
} else if (TempVar32_a == 3) {
CoreDisableBits &= 0x0F;
} else if (TempVar32_a == 4) {
CoreDisableBits &= 0x1F;
} else if (TempVar32_a == 5) {
CoreDisableBits &= 0x3F;
}
PciAddress.Address.Register = DOWNCORE_CTRL;
LibAmdPciRead (AccessWidth32, PciAddress, &TempVar32_a, StdHeader);
if ((TempVar32_a | CoreDisableBits) != TempVar32_a) {
TempVar32_a |= CoreDisableBits;
LibAmdPciWrite (AccessWidth32, PciAddress, &TempVar32_a, StdHeader);
IsUpdated = TRUE;
}
}
}
return IsUpdated;
}
CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F10RevDCoreLeveling =
{
0,
F10CommonRevDSetDownCoreRegister
};
/*---------------------------------------------------------------------------------------*/
/**
* Get CPU pstate current on a revision D processor.
*
* @CpuServiceMethod{::F_CPU_GET_IDD_MAX}.
*
* This function returns the ProcIddMax.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[in] Pstate The P-state to check.
* @param[out] ProcIddMax P-state current in mA.
* @param[in] StdHeader Handle of Header for calling lib functions and services.
*
* @retval TRUE P-state is enabled
* @retval FALSE P-state is disabled
*/
BOOLEAN
F10CommonRevDGetProcIddMax (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN UINT8 Pstate,
OUT UINT32 *ProcIddMax,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 IddDiv;
UINT32 CmpCap;
UINT32 MultiNodeCpu;
UINT32 NbCaps;
UINT32 MsrAddress;
UINT64 PstateMsr;
BOOLEAN IsPstateEnabled;
PCI_ADDR PciAddress;
IsPstateEnabled = FALSE;
MsrAddress = (UINT32) (Pstate + PS_REG_BASE);
ASSERT (MsrAddress <= PS_MAX_REG);
LibAmdMsrRead (MsrAddress, &PstateMsr, StdHeader);
if (((PSTATE_MSR *) &PstateMsr)->PsEnable == 1) {
OptionMultiSocketConfiguration.GetCurrPciAddr (&PciAddress, StdHeader);
PciAddress.Address.Function = FUNC_3;
PciAddress.Address.Register = NB_CAPS_REG;
LibAmdPciRead (AccessWidth32, PciAddress, &NbCaps, StdHeader); // F3xE8
switch (((PSTATE_MSR *) &PstateMsr)->IddDiv) {
case 0:
IddDiv = 1000;
break;
case 1:
IddDiv = 100;
break;
case 2:
IddDiv = 10;
break;
default: // IddDiv = 3 is reserved. Use 10
IddDiv = 10;
break;
}
MultiNodeCpu = (UINT32) (((NB_CAPS_REGISTER *) &NbCaps)->MultiNodeCpu + 1);
CmpCap = (UINT32) (((NB_CAPS_REGISTER *) &NbCaps)->CmpCapHi << 2);
CmpCap |= (UINT32) (((NB_CAPS_REGISTER *) &NbCaps)->CmpCapLo);
CmpCap++;
*ProcIddMax = (UINT32) ((PSTATE_MSR *) &PstateMsr)->IddValue * IddDiv * CmpCap * MultiNodeCpu;
IsPstateEnabled = TRUE;
}
return IsPstateEnabled;
}
/*---------------------------------------------------------------------------------------*/
/**
* Returns whether or not BIOS is responsible for configuring the NB COFVID.
*
* @CpuServiceMethod{::F_CPU_IS_NBCOF_INIT_NEEDED}.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[in] PciAddress The northbridge to query by pci base address.
* @param[out] NbVidUpdateAll Do all NbVids need to be updated
* @param[in] StdHeader Header for library and services
*
* @retval TRUE Perform northbridge frequency and voltage config.
* @retval FALSE Do not configure them.
*/
BOOLEAN
F10CommonRevDGetNbCofVidUpdate (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN PCI_ADDR *PciAddress,
OUT BOOLEAN *NbVidUpdateAll,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
*NbVidUpdateAll = FALSE;
return FALSE;
}
/*---------------------------------------------------------------------------------------*/
/**
* Determines the NB clock on the desired node.
*
* @CpuServiceMethod{::F_CPU_GET_NB_PSTATE_INFO}.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[in] PlatformConfig Platform profile/build option config structure.
* @param[in] PciAddress The segment, bus, and device numbers of the CPU in question.
* @param[in] NbPstate The NB P-state number to check.
* @param[out] FreqNumeratorInMHz The desired node's frequency numerator in megahertz.
* @param[out] FreqDivisor The desired node's frequency divisor.
* @param[out] VoltageInuV The desired node's voltage in microvolts.
* @param[in] StdHeader Handle of Header for calling lib functions and services.
*
* @retval TRUE NbPstate is valid
* @retval FALSE NbPstate is disabled or invalid
*/
BOOLEAN
F10CommonRevDGetNbPstateInfo (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN PCI_ADDR *PciAddress,
IN UINT32 NbPstate,
OUT UINT32 *FreqNumeratorInMHz,
OUT UINT32 *FreqDivisor,
OUT UINT32 *VoltageInuV,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 LocalPciRegister;
UINT64 LocalMsrRegister;
BOOLEAN PstateIsValid;
PstateIsValid = FALSE;
if (NbPstate == 0) {
PciAddress->Address.Function = FUNC_3;
PciAddress->Address.Register = CPTC0_REG;
LibAmdPciRead (AccessWidth32, *PciAddress, &LocalPciRegister, StdHeader);
*FreqNumeratorInMHz = ((((CLK_PWR_TIMING_CTRL_REGISTER *) &LocalPciRegister)->NbFid + 4) * 200);
*FreqDivisor = 1;
LibAmdMsrRead (MSR_COFVID_STS, &LocalMsrRegister, StdHeader);
*VoltageInuV = (1550000 - (12500 * ((UINT32) ((COFVID_STS_MSR *) &LocalMsrRegister)->CurNbVid)));
PstateIsValid = TRUE;
}
return PstateIsValid;
}
/*---------------------------------------------------------------------------------------*/
/**
* Returns the node's minimum and maximum northbridge frequency.
*
* @CpuServiceMethod{::F_CPU_GET_MIN_MAX_NB_FREQ}.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[in] PlatformConfig Platform profile/build option config structure.
* @param[in] PciAddress The segment, bus, and device numbers of the CPU in question.
* @param[out] MinFreqInMHz The node's minimum northbridge frequency.
* @param[out] MaxFreqInMHz The node's maximum northbridge frequency.
* @param[in] StdHeader Handle of Header for calling lib functions and services.
*
* @retval AGESA_STATUS Northbridge frequency is valid
*/
AGESA_STATUS
F10RevDGetMinMaxNbFrequency (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN PCI_ADDR *PciAddress,
OUT UINT32 *MinFreqInMHz,
OUT UINT32 *MaxFreqInMHz,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 LocalPciRegister;
PciAddress->Address.Function = FUNC_3;
PciAddress->Address.Register = CPTC0_REG;
LibAmdPciRead (AccessWidth32, *PciAddress, &LocalPciRegister, StdHeader);
*MinFreqInMHz = ((((CLK_PWR_TIMING_CTRL_REGISTER *) &LocalPciRegister)->NbFid + 4) * 200);
*MaxFreqInMHz = *MinFreqInMHz;
return AGESA_SUCCESS;
}
/*---------------------------------------------------------------------------------------*/
/**
* Get the number of physical cores of current processor.
*
* @CpuServiceMethod{::F_CPU_NUMBER_OF_PHYSICAL_CORES}.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[in] StdHeader Handle of Header for calling lib functions and services.
*
* @return The number of physical cores.
*/
UINT8
F10CommonRevDGetNumberOfPhysicalCores (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 CmpCap;
UINT32 CmpCapOnNode;
UINT32 Socket;
UINT32 Module;
UINT32 Core;
UINT32 LocalPciRegister;
PCI_ADDR PciAddress;
AGESA_STATUS IgnoredSts;
CmpCap = 0;
IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts);
for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts)) {
PciAddress.Address.Function = FUNC_3;
PciAddress.Address.Register = NB_CAPS_REG;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
CmpCapOnNode = (UINT8) (((NB_CAPS_REGISTER *) &LocalPciRegister)->CmpCapHi << 2);
CmpCapOnNode |= (UINT8) (((NB_CAPS_REGISTER *) &LocalPciRegister)->CmpCapLo);
CmpCapOnNode++;
CmpCap += CmpCapOnNode;
}
}
return ((UINT8) CmpCap);
}

114
src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/HY/F10HyEquivalenceTable.c
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@ -1,114 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_10 Hydra Equivalence Table related data
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/Family/0x10
* @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
*
*/
/*
******************************************************************************
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "cpuFamilyTranslation.h"
#include "Filecode.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G2_PEI)
#define FILECODE PROC_CPU_FAMILY_0X10_REVD_HY_F10HYEQUIVALENCETABLE_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
VOID
GetF10HyMicrocodeEquivalenceTable (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
OUT CONST VOID **HyEquivalenceTablePtr,
OUT UINT8 *NumberOfElements,
IN AMD_CONFIG_PARAMS *StdHeader
);
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
STATIC CONST UINT16 ROMDATA CpuF10HyMicrocodeEquivalenceTable[] =
{
0x1080, 0x1080,
0x1081, 0x1081,
0x1091, 0x1081
};
/*---------------------------------------------------------------------------------------*/
/**
* Returns the appropriate microcode patch equivalent ID table.
*
* @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[out] HyEquivalenceTablePtr Points to the first entry in the table.
* @param[out] NumberOfElements Number of valid entries in the table.
* @param[in] StdHeader Header for library and services.
*
*/
VOID
GetF10HyMicrocodeEquivalenceTable (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
OUT CONST VOID **HyEquivalenceTablePtr,
OUT UINT8 *NumberOfElements,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
*NumberOfElements = ((sizeof (CpuF10HyMicrocodeEquivalenceTable) / sizeof (UINT16)) / 2);
*HyEquivalenceTablePtr = CpuF10HyMicrocodeEquivalenceTable;
}

1294
src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/HY/F10HyHtPhyTables.c
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File diff suppressed because it is too large Load Diff

144
src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/HY/F10HyInitEarlyTable.c
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@ -1,144 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Implements the workaround for erratum 419.
*
* Returns the table of initialization steps to perform at
* AmdInitEarly.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/FAMILY/0x10/RevD/HY
* @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
*
*/
/*
******************************************************************************
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "amdlib.h"
#include "cpuRegisters.h"
#include "cpuFamilyTranslation.h"
#include "F10PackageType.h"
#include "cpuEarlyInit.h"
#include "Filecode.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G2_PEI)
#define FILECODE PROC_CPU_FAMILY_0X10_REVD_HY_F10HYINITEARLYTABLE_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
VOID
GetF10HyEarlyInitOnCoreTable (
IN CPU_SPECIFIC_SERVICES *FamilyServices,
OUT CONST S_PERFORM_EARLY_INIT_ON_CORE **Table,
IN AMD_CPU_EARLY_PARAMS *EarlyParams,
IN AMD_CONFIG_PARAMS *StdHeader
);
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
extern F_PERFORM_EARLY_INIT_ON_CORE McaInitializationAtEarly;
extern F_PERFORM_EARLY_INIT_ON_CORE SetRegistersFromTablesAtEarly;
extern F_PERFORM_EARLY_INIT_ON_CORE SetBrandIdRegistersAtEarly;
extern F_PERFORM_EARLY_INIT_ON_CORE LocalApicInitializationAtEarly;
extern F_PERFORM_EARLY_INIT_ON_CORE LoadMicrocodePatchAtEarly;
extern F_GET_EARLY_INIT_TABLE GetF10EarlyInitOnCoreTable;
CONST S_PERFORM_EARLY_INIT_ON_CORE ROMDATA F10HyC32D0EarlyInitOnCoreTable[] =
{
{McaInitializationAtEarly, PERFORM_EARLY_ANY_CONDITION},
{SetRegistersFromTablesAtEarly, PERFORM_EARLY_ANY_CONDITION},
{LocalApicInitializationAtEarly, PERFORM_EARLY_ANY_CONDITION},
{LoadMicrocodePatchAtEarly, PERFORM_EARLY_WARM_RESET},
{SetBrandIdRegistersAtEarly, PERFORM_EARLY_ANY_CONDITION},
{NULL, 0}
};
/*------------------------------------------------------------------------------------*/
/**
* Initializer routine that may be invoked at AmdCpuEarly to return the steps
* appropriate for the executing Rev D core.
*
* @CpuServiceMethod{::F_GET_EARLY_INIT_TABLE}.
*
* @param[in] FamilyServices The current Family Specific Services.
* @param[out] Table Table of appropriate init steps for the executing core.
* @param[in] EarlyParams Service Interface structure to initialize.
* @param[in] StdHeader Opaque handle to standard config header.
*
*/
VOID
GetF10HyEarlyInitOnCoreTable (
IN CPU_SPECIFIC_SERVICES *FamilyServices,
OUT CONST S_PERFORM_EARLY_INIT_ON_CORE **Table,
IN AMD_CPU_EARLY_PARAMS *EarlyParams,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 ProcessorPackageType;
CPU_LOGICAL_ID LogicalId;
GetLogicalIdOfCurrentCore (&LogicalId, StdHeader);
ProcessorPackageType = LibAmdGetPackageType (StdHeader);
// Check if this CPU is affected by erratum 419.
if (((LogicalId.Revision & AMD_F10_HY_SCM_D0) != 0) && ((ProcessorPackageType & (PACKAGE_TYPE_G34 | PACKAGE_TYPE_FR2_FR5_FR6)) == 0)) {
// Return initialization steps such that the microcode patch is applied before
// brand string determination is performed.
*Table = F10HyC32D0EarlyInitOnCoreTable;
} else {
// No workaround is necessary. Return the standard table.
GetF10EarlyInitOnCoreTable (FamilyServices, Table, EarlyParams, StdHeader);
}
}

116
src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/HY/F10HyLogicalIdTables.c
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@ -1,116 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_10 Hydra Logical ID Table
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/FAMILY/0x10
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $
*
*/
/*
******************************************************************************
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "cpuRegisters.h"
#include "Filecode.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G1_PEICC)
#define FILECODE PROC_CPU_FAMILY_0X10_REVD_HY_F10HYLOGICALIDTABLES_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
VOID
GetF10HyLogicalIdAndRev (
OUT CONST CPU_LOGICAL_ID_XLAT **HyIdPtr,
OUT UINT8 *NumberOfElements,
OUT UINT64 *LogicalFamily,
IN OUT AMD_CONFIG_PARAMS *StdHeader
);
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
STATIC CONST CPU_LOGICAL_ID_XLAT ROMDATA CpuF10HyLogicalIdAndRevArray[] =
{
{
0x1080,
AMD_F10_HY_SCM_D0
},
{
0x1090,
AMD_F10_HY_MCM_D0
},
{
0x1081,
AMD_F10_HY_SCM_D1
},
{
0x1091,
AMD_F10_HY_MCM_D1
}
};
VOID
GetF10HyLogicalIdAndRev (
OUT CONST CPU_LOGICAL_ID_XLAT **HyIdPtr,
OUT UINT8 *NumberOfElements,
OUT UINT64 *LogicalFamily,
IN OUT AMD_CONFIG_PARAMS *StdHeader
)
{
*NumberOfElements = (sizeof (CpuF10HyLogicalIdAndRevArray) / sizeof (CPU_LOGICAL_ID_XLAT));
*HyIdPtr = CpuF10HyLogicalIdAndRevArray;
*LogicalFamily = AMD_FAMILY_10_HY;
}

114
src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/HY/F10HyMicrocodePatchTables.c
View File

@ -1,114 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_10 Hydra PCI tables with values as defined in BKDG
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/Family/0x10
* @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
*
*/
/*
******************************************************************************
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "cpuRegisters.h"
#include "cpuEarlyInit.h"
#include "cpuFamilyTranslation.h"
#include "Filecode.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G2_PEI)
#define FILECODE PROC_CPU_FAMILY_0X10_REVD_HY_F10HYMICROCODEPATCHTABLES_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
extern CONST MICROCODE_PATCHES ROMDATA *CpuF10HyMicroCodePatchArray[];
extern CONST UINT8 ROMDATA CpuF10HyNumberOfMicrocodePatches;
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
VOID
GetF10HyMicroCodePatchesStruct (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
OUT CONST VOID **HyUcodePtr,
OUT UINT8 *NumberOfElements,
IN AMD_CONFIG_PARAMS *StdHeader
);
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------*/
/**
* Returns a table containing the appropriate microcode patches.
*
* @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[out] HyUcodePtr Points to the first entry in the table.
* @param[out] NumberOfElements Number of valid entries in the table.
* @param[in] StdHeader Header for library and services.
*
*/
VOID
GetF10HyMicroCodePatchesStruct (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
OUT CONST VOID **HyUcodePtr,
OUT UINT8 *NumberOfElements,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
*NumberOfElements = CpuF10HyNumberOfMicrocodePatches;
*HyUcodePtr = &CpuF10HyMicroCodePatchArray[0];
}

137
src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/HY/F10HyMsrTables.c
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@ -1,137 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_10 HY MSR tables with values as defined in BKDG
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU
* @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
*
*/
/*
******************************************************************************
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "cpuRegisters.h"
#include "Table.h"
#include "Filecode.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G2_PEI)
#define FILECODE PROC_CPU_FAMILY_0X10_REVD_HY_F10HYMSRTABLES_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
STATIC CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F10HyMsrRegisters[] =
{
// M S R T a b l e s
// ----------------------
// MSR_LS_CFG (0xC0011020)
// bit[1] = 0
{
MsrRegister,
{
AMD_FAMILY_10, // CpuFamily
AMD_F10_GT_B0 // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MSR_LS_CFG, // MSR Address
0x0000000000000000, // OR Mask
(1 << 1) // NAND Mask
}}
},
// MSR_BU_CFG (0xC0011023)
// bit[21] = 1
{
MsrRegister,
{
AMD_FAMILY_10, // CpuFamily
AMD_F10_GT_B0 // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MSR_BU_CFG, // MSR Address
(1 << 21), // OR Mask
(1 << 21), // NAND Mask
}}
},
// MSR_BU_CFG2 (0xC001102A)
// bit[50] = 1
// For GH rev C1 and later [RdMmExtCfgQwEn]=1
{
MsrRegister,
{
AMD_FAMILY_10, // CpuFamily
AMD_F10_GT_C0 // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MSR_BU_CFG2, // MSR Address
0x0004000000000000, // OR Mask
0x0004000000000000, // NAND Mask
}}
}
};
CONST REGISTER_TABLE ROMDATA F10HyMsrRegisterTable = {
AllCores,
(sizeof (F10HyMsrRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
(TABLE_ENTRY_FIELDS *) &F10HyMsrRegisters,
};

384
src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/HY/F10HyPciTables.c
View File

@ -1,384 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_10 Hydra PCI tables with values as defined in BKDG
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/FAMILY/0x10
* @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
*
*/
/*
******************************************************************************
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "cpuRegisters.h"
#include "Table.h"
#include "Filecode.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G2_PEI)
#define FILECODE PROC_CPU_FAMILY_0X10_REVD_HY_F10HYPCITABLES_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
// P C I T a b l e s
// ----------------------
STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10HyPciRegisters[] =
{
// F0x68 -
// BufRelPri for rev D
// bits[14:13] BufRelPri = 1
// bit [25] CHtExtAddrEn = 1
{
PciRegister,
{
AMD_FAMILY_10, // CpuFamily
AMD_F10_Dx // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO(0, 0, 24, FUNC_0, 0x68), // Address
0x02002000, // regData
0x02006000, // regMask
}}
},
// F0x[E4,A4,C4,84] Link Control Register
// bit [15] Addr64bitEn = 1
{
HtHostPciRegister,
{
AMD_FAMILY_10, // CpuFamily
AMD_F10_Dx // CpuRevision
},
{AMD_PF_ALL},
{{
HT_HOST_FEAT_NONCOHERENT,
0x4,
0x00008000,
0x00008000,
}}
},
// F0x150 - Link Global Retry Control Register
// bit[18:16] TotalRetryAttempts = 7
// bit[13] HtRetryCrcDatInsDynEn = 1
// bit[12]HtRetryCrcCmdPackDynEn = 1
// bit[11:9] HtRetryCrcDatIns = 0
// bit[8] HtRetryCrcCmdPack = 1
{
PciRegister,
{
AMD_FAMILY_10, // CpuFamily
AMD_F10_D0 // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_0, 0x150), // Address
0x00073100, // regData
0x00073F00, // regMask
}}
},
// F0x16C - Link Global Extended Control Register
// bit[15:13] ForceFullT0 = 6
// bit[5:0] T0Time = 0x26
{
PciRegister,
{
AMD_FAMILY_10_HY, // CpuFamily
AMD_F10_D1 // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_0, 0x16C), // Address
0x0000C026, // regData
0x0000E03F, // regMask
}}
},
// F0x16C - Link Global Extended Control Register
// bit[9] RXCalEn = 1
{
PciRegister,
{
AMD_FAMILY_10_HY, // CpuFamily
AMD_F10_Dx // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_0, 0x16C), // Address
0x00000200, // regData
0x00000200, // regMask
}}
},
// F0x16C - Link Global Extended Control Register
// bit[7:6] InLnSt = 01b (PHY_OFF)
{
PciRegister,
{
AMD_FAMILY_10, // CpuFamily
AMD_F10_Dx // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_0, 0x16C), // Address
0x00000040, // regData
0x000000C0, // regMask
}}
},
// F0x[18C:170] - Link Extended Control Register - All connected links.
// bit[8] LS2En = 1
{
HtLinkPciRegister,
{
AMD_FAMILY_10_HY, // CpuFamily
AMD_F10_D1 // CpuRevision
},
{AMD_PF_ALL}, // platform Features
{{
HT_HOST_FEATURES_ALL,
MAKE_SBDFO (0, 0, 24, FUNC_0, 0x170), // Address
0x00000100, // regData
0x00000100, // regMask
}}
},
// F2x1B0 - Extended Memory Controller Configuration Low
// bits[10:8], CohPrefPrbLmt = 0
{
ProfileFixup,
{
AMD_FAMILY_10, // CpuFamily
AMD_F10_Dx // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
PERFORMANCE_PROBEFILTER, // Features
MAKE_SBDFO (0, 0, 24, FUNC_2, 0x1B0), // Address
0x00000000, // regData
0x00000700, // regMask
}}
},
// Function 3 - Misc. Control
// F3x158 - Link to XCS Token Count
// bits[3:0] LnkToXcsDRToken = 3
{
PciRegister,
{
AMD_FAMILY_10, // CpuFamily
AMD_F10_GT_A2 // CpuRevision
},
{AMD_PF_UMA}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_3, 0x158), // Address
0x00000003, // regData
0x0000000F, // regMask
}}
},
// F3x80 - ACPI Power State Control
// ACPI State C2
// bits[0] CpuPrbEn = 1
// bits[1] NbLowPwrEn = 0
// bits[2] NbGateEn = 0
// bits[3] NbCofChg = 0
// bits[4] AltVidEn = 0
// bits[7:5] ClkDivisor = 1
// ACPI State C3, C1E or Link init
// bits[0] CpuPrbEn = 0
// bits[1] NbLowPwrEn = 1
// bits[2] NbGateEn = 1
// bits[3] NbCofChg = 0
// bits[4] AltVidEn = 0
// bits[7:5] ClkDivisor = 5
{
PciRegister,
{
AMD_FAMILY_10, // CpuFamily
AMD_F10_GT_Ax // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_3, 0x80), // Address
0x0000A681, // regData
0x0000FFFF, // regMask
}}
},
// F3x80 - ACPI Power State Control
// ACPI State C3, C1E or Link init
// bits[0] CpuPrbEn = 0
// bits[1] NbLowPwrEn = 1
// bits[2] NbGateEn = 1
// bits[3] NbCofChg = 0
// bits[4] AltVidEn = 0
// bits[7:5] ClkDivisor = 7
{
PciRegister,
{
AMD_FAMILY_10, // CpuFamily
AMD_F10_GT_D0 // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_3, 0x80), // Address
0x0000E600, // regData
0x0000FF00, // regMask
}}
},
// F3xA0 - Power Control Miscellaneous
// bit[14] BpPinsTriEn = 1
{
PciRegister,
{
AMD_FAMILY_10, // CpuFamily
AMD_F10_GT_D0 // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_3, 0xA0), // Address
0x00004000, // regData
0x00004000, // regMask
}}
},
// F3xD4 - Clock Power Timing Control 0
// bits[15] StutterScrubEn = 0
// bits[14] CacheFlushImmOnAllHalt = 0
// bits[13] MTC1eEn = 0
{
PciRegister,
{
AMD_FAMILY_10, // CpuFamily
AMD_F10_Dx // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_3, 0xD4), // Address
0x00000000, // regData
0x0000E000, // regMask
}}
},
// F3x188 - NB Extended Configuration Low Register
// bit[27] = DisCpuWrSzDw64ReOrd
{
PciRegister,
{
AMD_FAMILY_10, // CpuFamily
AMD_F10_D0 // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_3, 0x188), // Address
0x08000000, // regData
0x08000000, // regMask
}}
},
// F3x1B8 - L3 Control
// bit[18] L3RdBufBypDis = 1, Erratum 374
{
PciRegister,
{
AMD_FAMILY_10, // CpuFamily
AMD_F10_D0 // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_3, 0x1B8), // Address
0x00040000, // regData
0x00040000, // regMask
}}
},
// F3x1B8 - L3 Control
// bit[23] L3BankSwapDis = 1, Erratum 385
{
PciRegister,
{
AMD_FAMILY_10, // CpuFamily
AMD_F10_Dx // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_3, 0x1B8), // Address
0x00800000, // regData
0x00800000, // regMask
}}
},
// F3x1D4 - Probe Filter Control Register
// bits[21:20] PFPreferedSORepl = 2
{
PciRegister,
{
AMD_FAMILY_10, // CpuFamily
AMD_F10_Dx // CpuRevision
},
{AMD_PF_ALL}, // platformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_3, 0x1D4), // Address
0x00200000, // regData
0x00300000, // regMask
}}
}
};
CONST REGISTER_TABLE ROMDATA F10HyPciRegisterTable = {
PrimaryCores,
(sizeof (F10HyPciRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
F10HyPciRegisters,
};

14
src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/HY/Makefile.inc
View File

@ -1,14 +0,0 @@
libagesa-y += F10HyEquivalenceTable.c
libagesa-y += F10HyEquivalenceTable.c
libagesa-y += F10HyHtPhyTables.c
libagesa-y += F10HyHtPhyTables.c
libagesa-y += F10HyInitEarlyTable.c
libagesa-y += F10HyInitEarlyTable.c
libagesa-y += F10HyLogicalIdTables.c
libagesa-y += F10HyLogicalIdTables.c
libagesa-y += F10HyMicrocodePatchTables.c
libagesa-y += F10HyMicrocodePatchTables.c
libagesa-y += F10HyMsrTables.c
libagesa-y += F10HyMsrTables.c
libagesa-y += F10HyPciTables.c
libagesa-y += F10HyPciTables.c

10
src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/Makefile.inc
View File

@ -1,10 +0,0 @@
libagesa-y += F10MicrocodePatch010000c5.c
libagesa-y += F10MicrocodePatch010000c5.c
libagesa-y += F10MicrocodePatch010000d9.c
libagesa-y += F10MicrocodePatch010000d9.c
libagesa-y += F10RevDL3Features.c
libagesa-y += F10RevDL3Features.c
libagesa-y += F10RevDMsgBasedC1e.c
libagesa-y += F10RevDMsgBasedC1e.c
libagesa-y += F10RevDUtilities.c
libagesa-y += F10RevDUtilities.c

329
src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuCommonF10Utilities.c
View File

@ -1,329 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_10 specific utility functions.
*
* Provides numerous utility functions specific to family 10h.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/F10
* @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
*
*/
/*
*****************************************************************************
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "amdlib.h"
#include "Ids.h"
#include "cpuRegisters.h"
#include "cpuServices.h"
#include "GeneralServices.h"
#include "cpuFamilyTranslation.h"
#include "cpuCommonF10Utilities.h"
#include "Filecode.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G2_PEI)
#define FILECODE PROC_CPU_FAMILY_0X10_CPUCOMMONF10UTILITIES_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/**
* Node ID MSR register fields.
* Provide the layout of fields in the Node ID MSR.
*/
typedef struct {
UINT64 NodeId:3; ///< The core is on the node with this node id.
UINT64 NodesPerProcessor:3; ///< The number of Nodes in this processor.
UINT64 HeapIndex:6; ///< The AP core heap index.
UINT64 :(63 - 11); ///< Reserved.
} NODE_ID_MSR_FIELDS;
/// Node ID MSR.
typedef union {
NODE_ID_MSR_FIELDS Fields; ///< Access the register as individual fields
UINT64 Value; ///< Access the register value.
} NODE_ID_MSR;
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------*/
/**
* Set warm reset status and count
*
* @CpuServiceMethod{::F_CPU_SET_WARM_RESET_FLAG}.
*
* This function will use bit9, and bit 10 of register F0x6C as a warm reset status and count.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[in] StdHeader Handle of Header for calling lib functions and services.
* @param[in] Request Indicate warm reset status
*
*/
VOID
F10SetAgesaWarmResetFlag (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CONFIG_PARAMS *StdHeader,
IN WARM_RESET_REQUEST *Request
)
{
PCI_ADDR PciAddress;
UINT32 PciData;
PciAddress.AddressValue = MAKE_SBDFO (0, 0 , PCI_DEV_BASE, FUNC_0, HT_INIT_CTRL);
LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader);
// bit[5] - indicate a warm reset is or is not required
PciData &= ~(HT_INIT_BIOS_RST_DET_0);
PciData = PciData | (Request->RequestBit << 5);
// bit[10,9] - indicate warm reset status and count
PciData &= ~(HT_INIT_BIOS_RST_DET_1 | HT_INIT_BIOS_RST_DET_2);
PciData |= Request->StateBits << 9;
LibAmdPciWrite (AccessWidth32, PciAddress, &PciData, StdHeader);
}
/*---------------------------------------------------------------------------------------*/
/**
* Get warm reset status and count
*
* @CpuServiceMethod{::F_CPU_GET_WARM_RESET_FLAG}.
*
* This function will bit9, and bit 10 of register F0x6C as a warm reset status and count.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[in] StdHeader Config handle for library and services
* @param[out] Request Indicate warm reset status
*
*/
VOID
F10GetAgesaWarmResetFlag (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CONFIG_PARAMS *StdHeader,
OUT WARM_RESET_REQUEST *Request
)
{
PCI_ADDR PciAddress;
UINT32 PciData;
PciAddress.AddressValue = MAKE_SBDFO (0, 0 , PCI_DEV_BASE, FUNC_0, HT_INIT_CTRL);
LibAmdPciRead (AccessWidth32, PciAddress, &PciData, StdHeader);
// bit[5] - indicate a warm reset is or is not required
Request->RequestBit = (UINT8) ((PciData & HT_INIT_BIOS_RST_DET_0) >> 5);
// bit[10,9] - indicate warm reset status and count
Request->StateBits = (UINT8) ((PciData & (HT_INIT_BIOS_RST_DET_1 | HT_INIT_BIOS_RST_DET_2)) >> 9);
}
/*---------------------------------------------------------------------------------------*/
/**
* Use the Mailbox Register to get the Ap Mailbox info for the current core.
*
* @CpuServiceMethod{::F_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE}.
*
* Access the mailbox register used with this NB family. This is valid until the
* point that some init code initializes the mailbox register for its normal use.
* The Machine Check Misc (Thresholding) register is available as both a PCI config
* register and a MSR, so it can be used as a mailbox from HT to other functions.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[out] ApMailboxInfo The AP Mailbox info
* @param[in] StdHeader Handle of Header for calling lib functions and services.
*
*/
VOID
F10GetApMailboxFromHardware (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
OUT AP_MAILBOXES *ApMailboxInfo,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT64 MailboxInfo;
LibAmdMsrRead (MSR_MC_MISC_LINK_THRESHOLD, &MailboxInfo, StdHeader);
// Mailbox info is in bits 32 thru 43, 12 bits.
ApMailboxInfo->ApMailInfo.Info = (((UINT32) (MailboxInfo >> 32)) & (UINT32)0x00000FFF);
LibAmdMsrRead (MSR_MC_MISC_L3_THRESHOLD, &MailboxInfo, StdHeader);
// Mailbox info is in bits 32 thru 43, 12 bits.
ApMailboxInfo->ApMailExtInfo.Info = (((UINT32) (MailboxInfo >> 32)) & (UINT32)0x00000FFF);
}
/*---------------------------------------------------------------------------------------*/
/**
* Set the system AP core number in the AP's Mailbox.
*
* @CpuServiceMethod{::F_CPU_SET_AP_CORE_NUMBER}.
*
* Access the mailbox register used with this NB family. This is only intended to
* run on the BSC at the time of initial AP launch.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[in] Socket The AP's socket
* @param[in] Module The AP's module
* @param[in] ApCoreNumber The AP's unique core number
* @param[in] StdHeader Handle of Header for calling lib functions and services.
*
*/
VOID
F10SetApCoreNumber (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN UINT32 Socket,
IN UINT32 Module,
IN UINT32 ApCoreNumber,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 LocalPciRegister;
PCI_ADDR PciAddress;
AGESA_STATUS IgnoredStatus;
GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredStatus);
PciAddress.Address.Function = FUNC_3;
PciAddress.Address.Register = 0x170;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
((AP_MAIL_EXT_INFO *) &LocalPciRegister)->Fields.HeapIndex = ApCoreNumber;
LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
}
/*---------------------------------------------------------------------------------------*/
/**
* Get this AP's system core number from hardware.
*
* @CpuServiceMethod{::F_CPU_GET_AP_CORE_NUMBER}.
*
* Returns the system core number from the scratch MSR, where
* it was saved at heap initialization.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[in] StdHeader Handle of Header for calling lib functions and services.
*
* @return The AP's unique core number
*/
UINT32
F10GetApCoreNumber (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
NODE_ID_MSR NodeIdMsr;
LibAmdMsrRead (0xC001100C, &NodeIdMsr.Value, StdHeader);
return (UINT32) NodeIdMsr.Fields.HeapIndex;
}
/*---------------------------------------------------------------------------------------*/
/**
* Move the AP's core number from the mailbox to hardware.
*
* @CpuServiceMethod{::F_CPU_TRANSFER_AP_CORE_NUMBER}.
*
* Transfers this AP's system core number from the mailbox to
* the NodeId MSR and initializes the other NodeId fields.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[in] StdHeader Handle of Header for calling lib functions and services.
*
*/
VOID
F10TransferApCoreNumber (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
AP_MAILBOXES Mailboxes;
NODE_ID_MSR NodeIdMsr;
UINT64 ExtFeatures;
NodeIdMsr.Value = 0;
FamilySpecificServices->GetApMailboxFromHardware (FamilySpecificServices, &Mailboxes, StdHeader);
NodeIdMsr.Fields.HeapIndex = Mailboxes.ApMailExtInfo.Fields.HeapIndex;
NodeIdMsr.Fields.NodeId = Mailboxes.ApMailInfo.Fields.Node;
NodeIdMsr.Fields.NodesPerProcessor = Mailboxes.ApMailInfo.Fields.ModuleType;
LibAmdMsrWrite (0xC001100C, &NodeIdMsr.Value, StdHeader);
// Indicate that the NodeId MSR is supported.
LibAmdMsrRead (MSR_CPUID_EXT_FEATS, &ExtFeatures, StdHeader);
ExtFeatures = (ExtFeatures | BIT51);
LibAmdMsrWrite (MSR_CPUID_EXT_FEATS, &ExtFeatures, StdHeader);
}
/*---------------------------------------------------------------------------------------*/
/**
* Return a number zero or one, based on the Core ID position in the initial APIC Id.
*
* @CpuServiceMethod{::F_CORE_ID_POSITION_IN_INITIAL_APIC_ID}.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[in] StdHeader Handle of Header for calling lib functions and services.
*
* @retval CoreIdPositionZero Core Id is not low
* @retval CoreIdPositionOne Core Id is low
*/
CORE_ID_POSITION
F10CpuAmdCoreIdPositionInInitialApicId (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT64 InitApicIdCpuIdLo;
// Check bit_54 [InitApicIdCpuIdLo] to find core id position.
LibAmdMsrRead (MSR_NB_CFG, &InitApicIdCpuIdLo, StdHeader);
InitApicIdCpuIdLo = ((InitApicIdCpuIdLo & BIT54) >> 54);
return ((InitApicIdCpuIdLo == 0) ? CoreIdPositionZero : CoreIdPositionOne);
}

120
src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuCommonF10Utilities.h
View File

@ -1,120 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_10 specific utility functions.
*
* Provides numerous utility functions specific to family 10h.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: IDS
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $
*
*/
/*
******************************************************************************
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef _CPU_COMMON_F10_UTILITES_H_
#define _CPU_COMMON_F10_UTILITES_H_
/*---------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*---------------------------------------------------------------------------------------
*/
VOID
F10GetApMailboxFromHardware (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
OUT AP_MAILBOXES *ApMailboxInfo,
IN AMD_CONFIG_PARAMS *StdHeader
);
CORE_ID_POSITION
F10CpuAmdCoreIdPositionInInitialApicId (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CONFIG_PARAMS *StdHeader
);
VOID
F10SetApCoreNumber (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN UINT32 Socket,
IN UINT32 Module,
IN UINT32 ApCoreNumber,
IN AMD_CONFIG_PARAMS *StdHeader
);
UINT32
F10GetApCoreNumber (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CONFIG_PARAMS *StdHeader
);
VOID
F10TransferApCoreNumber (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CONFIG_PARAMS *StdHeader
);
VOID
F10SetAgesaWarmResetFlag (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CONFIG_PARAMS *StdHeader,
IN WARM_RESET_REQUEST *Request
);
VOID
F10GetAgesaWarmResetFlag (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CONFIG_PARAMS *StdHeader,
OUT WARM_RESET_REQUEST *Request
);
#endif // _CPU_COMMON_F10_UTILITES_H_

160
src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10BrandId.c
View File

@ -1,160 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD CPU BrandId related functions and structures.
*
* Contains code that provides CPU BrandId information
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU
* @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
*
*/
/*
******************************************************************************
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "cpuRegisters.h"
#include "cpuEarlyInit.h"
#include "cpuFamilyTranslation.h"
#include "Filecode.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G2_PEI)
#define FILECODE PROC_CPU_FAMILY_0X10_CPUF10BRANDID_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
VOID
GetF10BrandIdString1 (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
OUT CONST VOID **BrandString1Ptr,
OUT UINT8 *NumberOfElements,
IN AMD_CONFIG_PARAMS *StdHeader
);
VOID
GetF10BrandIdString2 (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
OUT CONST VOID **BrandString2Ptr,
OUT UINT8 *NumberOfElements,
IN AMD_CONFIG_PARAMS *StdHeader
);
extern CPU_BRAND_TABLE *F10BrandIdString1Tables[];
extern CPU_BRAND_TABLE *F10BrandIdString2Tables[];
extern CONST UINT8 F10BrandIdString1TableCount;
extern CONST UINT8 F10BrandIdString2TableCount;
/*---------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------*/
/**
* Returns a table containing the appropriate beginnings of the CPU brandstring.
*
* @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[out] BrandString1Ptr Points to the first entry in the table.
* @param[out] NumberOfElements Number of valid entries in the table.
* @param[in] StdHeader Header for library and services.
*
*/
VOID
GetF10BrandIdString1 (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
OUT CONST VOID **BrandString1Ptr,
OUT UINT8 *NumberOfElements,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
CPU_BRAND_TABLE **TableEntryPtr;
TableEntryPtr = &F10BrandIdString1Tables[0];
*BrandString1Ptr = TableEntryPtr;
*NumberOfElements = F10BrandIdString1TableCount;
}
/*---------------------------------------------------------------------------------------*/
/**
* Returns a table containing the appropriate endings of the CPU brandstring.
*
* @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[out] BrandString2Ptr Points to the first entry in the table.
* @param[out] NumberOfElements Number of valid entries in the table.
* @param[in] StdHeader Header for library and services.
*
*/
VOID
GetF10BrandIdString2 (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
OUT CONST VOID **BrandString2Ptr,
OUT UINT8 *NumberOfElements,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
CPU_BRAND_TABLE **TableEntryPtr;
TableEntryPtr = &F10BrandIdString2Tables[0];
*BrandString2Ptr = TableEntryPtr;
*NumberOfElements = F10BrandIdString2TableCount;
}

335
src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10BrandIdAm3.c
View File

@ -1,335 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD CPU BrandId related functions and structures for socket Am3.
*
* Contains code that provides CPU BrandId information
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU
* @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
*
*/
/*
******************************************************************************
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "cpuRegisters.h"
#include "cpuEarlyInit.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G2_PEI)
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
// PRIVATE FORMAT FOR BRAND TABLE ... FOR AMD USE ONLY
// String1
/*CHAR8 strEngSample[] = "AMD Engineering Sample";
CHAR8 strTtkSample[] = "AMD Thermal Test Kit";
CHAR8 strUnknown[] = "AMD Processor model unknown";
*/
//AM3 NC 0
CONST CHAR8 ROMDATA str_F10_Am3_SC_AthlonLE[] = "AMD Athlon(tm) Processor LE-";
CONST CHAR8 ROMDATA str_F10_Am3_SC_SempronLE[] = "AMD Sempron(tm) Processor LE-";
CONST CHAR8 ROMDATA str_F10_Am3_SC_Sempron_1[] = "AMD Sempron(tm) 1";
CONST CHAR8 ROMDATA str_F10_Am3_SC_Athlon_1[] = "AMD Athlon(tm) II 1";
//AM3 NC 1
CONST CHAR8 ROMDATA str_F10_Am3_Athlon[] = "AMD Athlon(tm) ";
CONST CHAR8 ROMDATA str_F10_Am3_Athlon_II_XL_V[] = "AMD Athlon(tm) II XL V";
CONST CHAR8 ROMDATA str_F10_Am3_Athlon_II_XLT_V[] = "AMD Athlon(tm) II XLT V";
CONST CHAR8 ROMDATA str_F10_Am3_Athlon_II_X2_4[] = "AMD Athlon(tm) II X2 4";
CONST CHAR8 ROMDATA str_F10_Am3_Athlon_II_X2_2[] = "AMD Athlon(tm) II X2 2";
CONST CHAR8 ROMDATA str_F10_Am3_Athlon_II_X2_B[] = "AMD Athlon(tm) II X2 B";
CONST CHAR8 ROMDATA str_F10_Am3_Athlon_II_X2[] = "AMD Athlon(tm) II X2 ";
CONST CHAR8 ROMDATA str_F10_Am3_Athlon_II_Neo_X2[] = "AMD Athlon(tm) II Neo X2 ";
CONST CHAR8 ROMDATA str_F10_Am3_Phenom_II_X2_5[] = "AMD Phenom(tm) II X2 5";
CONST CHAR8 ROMDATA str_F10_Am3_Athlon_II_X2_5[] = "AMD Athlon(tm) II X2 5";
CONST CHAR8 ROMDATA str_F10_Am3_Athlon_II_X2_3[] = "AMD Athlon(tm) II X2 3";
CONST CHAR8 ROMDATA str_F10_Am3_Phenom_II_X2[] = "AMD Phenom(tm) II X2 ";
CONST CHAR8 ROMDATA str_F10_Am3_Phenom_II_X2_B[] = "AMD Phenom(tm) II X2 B";
CONST CHAR8 ROMDATA str_F10_Am3_DC_Opteron13[] = "Dual-Core AMD Opteron(tm) Processor 13";
CONST CHAR8 ROMDATA str_F10_Am3_Sempron_X2_1[] = "AMD Sempron(tm) X2 1";
//AM3 NC2
CONST CHAR8 ROMDATA str_F10_Am3_Phenom[] = "AMD Phenom(tm) ";
CONST CHAR8 ROMDATA str_F10_Am3_Phenom_II_X3_5[] = "AMD Phenom(tm) II X3 5";
CONST CHAR8 ROMDATA str_F10_Am3_Phenom_II_X3_4[] = "AMD Phenom(tm) II X3 4";
CONST CHAR8 ROMDATA str_F10_Am3_Phenom_II_X3_B[] = "AMD Phenom(tm) II X3 B";
CONST CHAR8 ROMDATA str_F10_Am3_Phenom_II_X3[] = "AMD Phenom(tm) II X3 ";
CONST CHAR8 ROMDATA str_F10_Am3_Athlon_II_X3_3[] = "AMD Athlon(tm) II X3 3";
CONST CHAR8 ROMDATA str_F10_Am3_Athlon_II_Neo_X3[] = "AMD Athlon(tm) II Neo X3 ";
CONST CHAR8 ROMDATA str_F10_Am3_Athlon_II_X3_4[] = "AMD Athlon(tm) II X3 4";
CONST CHAR8 ROMDATA str_F10_Am3_Phenom_II_X3_7[] = "AMD Phenom(tm) II X3 7";
CONST CHAR8 ROMDATA str_F10_Am3_Athlon_II_X3_B[] = "AMD Athlon(tm) II X3 B";
CONST CHAR8 ROMDATA str_F10_Am3_Athlon_II_X3[] = "AMD Athlon(tm) II X3 ";
//AM3 NC 3
CONST CHAR8 ROMDATA str_F10_Am3_Phenom_FX[] = "AMD Phenom(tm) FX-";
CONST CHAR8 ROMDATA str_F10_Am3_Phenom_II_X4_9[] = "AMD Phenom(tm) II X4 9";
CONST CHAR8 ROMDATA str_F10_Am3_Phenom_II_X4_8[] = "AMD Phenom(tm) II X4 8";
CONST CHAR8 ROMDATA str_F10_Am3_Phenom_II_X4_7[] = "AMD Phenom(tm) II X4 7";
CONST CHAR8 ROMDATA str_F10_Am3_Phenom_II_X4_6[] = "AMD Phenom(tm) II X4 6";
CONST CHAR8 ROMDATA str_F10_Am3_Phenom_II_X4_B[] = "AMD Phenom(tm) II X4 B";
CONST CHAR8 ROMDATA str_F10_Am3_Phenom_II_X4[] = "AMD Phenom(tm) II X4 ";
CONST CHAR8 ROMDATA str_F10_Am3_Phenom_II_Neo_X4[] = "AMD Phenom(tm) II Neo X4 ";
CONST CHAR8 ROMDATA str_F10_Am3_Athlon_II_X4_6[] = "AMD Athlon(tm) II X4 6";
CONST CHAR8 ROMDATA str_F10_Am3_Athlon_II_X4_5[] = "AMD Athlon(tm) II X4 5";
CONST CHAR8 ROMDATA str_F10_Am3_Athlon_II_Neo_X4[] = "AMD Athlon(tm) II Neo X4 ";
CONST CHAR8 ROMDATA str_F10_Am3_Athlon_II_X4_B[] = "AMD Athlon(tm) II X4 B";
CONST CHAR8 ROMDATA str_F10_Am3_Phenom_II__FX[] = "AMD Phenom(tm) II FX-";
CONST CHAR8 ROMDATA str_F10_Am3_Athlon_II_X4[] = "AMD Athlon(tm) II X4 ";
CONST CHAR8 ROMDATA str_F10_Am3_Phenom_II[] = "AMD Phenom(tm) II ";
CONST CHAR8 ROMDATA str_F10_Am3_Phenom_II_XLT_Q[] = "AMD Phenom(tm) II XLT Q";
CONST CHAR8 ROMDATA str_F10_Am3_QC_Opteron13[] = "Quad-Core AMD Opteron(tm) Processor 13";
//AM3 NC 5
CONST CHAR8 ROMDATA str_F10_Am3_Phenom_II_X6_1[] = "AMD Phenom(tm) II X6 1";
// String2
CONST CHAR8 ROMDATA str2_F10_Am3_SE[] = " SE";
CONST CHAR8 ROMDATA str2_F10_Am3_HE[] = " HE";
CONST CHAR8 ROMDATA str2_F10_Am3_EE[] = " EE";
CONST CHAR8 ROMDATA str2_F10_Am3_QCP[] = " Quad-Core Processor";
CONST CHAR8 ROMDATA str2_F10_Am3_00[] = "00";
CONST CHAR8 ROMDATA str2_F10_Am3_10[] = "10";
CONST CHAR8 ROMDATA str2_F10_Am3_20[] = "20";
CONST CHAR8 ROMDATA str2_F10_Am3_30[] = "30";
CONST CHAR8 ROMDATA str2_F10_Am3_40[] = "40";
CONST CHAR8 ROMDATA str2_F10_Am3_50[] = "50";
CONST CHAR8 ROMDATA str2_F10_Am3_60[] = "60";
CONST CHAR8 ROMDATA str2_F10_Am3_70[] = "70";
CONST CHAR8 ROMDATA str2_F10_Am3_80[] = "80";
CONST CHAR8 ROMDATA str2_F10_Am3_90[] = "90";
CONST CHAR8 ROMDATA str2_F10_Am3_DC_00[] = "00 Dual-Core Processor";
CONST CHAR8 ROMDATA str2_F10_Am3_DC_00e[] = "00e Dual-Core Processor";
CONST CHAR8 ROMDATA str2_F10_Am3_DC_00B[] = "00B Dual-Core Processor";
CONST CHAR8 ROMDATA str2_F10_Am3_DC_50[] = "50 Dual-Core Processor";
CONST CHAR8 ROMDATA str2_F10_Am3_DC_50e[] = "50e Dual-Core Processor";
CONST CHAR8 ROMDATA str2_F10_Am3_DC_50B[] = "50B Dual-Core Processor";
CONST CHAR8 ROMDATA str2_F10_Am3_Processor[] = " Processor";
CONST CHAR8 ROMDATA str2_F10_Am3_e_Processor[] = "e Processor";
CONST CHAR8 ROMDATA str2_F10_Am3_B_Processor[] = "B Processor";
CONST CHAR8 ROMDATA str2_F10_Am3_0e_Processor[] = "0e Processor";
CONST CHAR8 ROMDATA str2_F10_Am3_u_Processor[] = "u Processor";
CONST CHAR8 ROMDATA str2_F10_Am3_0_Processor[] = "0 Processor";
CONST CHAR8 ROMDATA str2_F10_Am3_L_Processor[] = "L Processor";
CONST CHAR8 ROMDATA str2_F10_Am3_C_Processor[] = "C Processor";
CONST CHAR8 ROMDATA str2_F10_Am3_TWKR_Black_Edition[] = " TWKR Black Edition";
CONST CHAR8 ROMDATA str2_F10_Am3_TC_00[] = "00 Triple-Core Processor";
CONST CHAR8 ROMDATA str2_F10_Am3_TC_00e[] = "00e Triple-Core Processor";
CONST CHAR8 ROMDATA str2_F10_Am3_TC_00B[] = "00B Triple-Core Processor";
CONST CHAR8 ROMDATA str2_F10_Am3_TC_50[] = "50 Triple-Core Processor";
CONST CHAR8 ROMDATA str2_F10_Am3_TC_50e[] = "50e Triple-Core Processor";
CONST CHAR8 ROMDATA str2_F10_Am3_TC_50B[] = "50B Triple-Core Processor";
CONST CHAR8 ROMDATA str2_F10_Am3_QC_00[] = "00 Quad-Core Processor";
CONST CHAR8 ROMDATA str2_F10_Am3_QC_00e[] = "00e Quad-Core Processor";
CONST CHAR8 ROMDATA str2_F10_Am3_QC_00B[] = "00B Quad-Core Processor";
CONST CHAR8 ROMDATA str2_F10_Am3_QC_50[] = "50 Quad-Core Processor";
CONST CHAR8 ROMDATA str2_F10_Am3_QC_50e[] = "50e Quad-Core Processor";
CONST CHAR8 ROMDATA str2_F10_Am3_QC_50B[] = "50B Quad-Core Processor";
CONST CHAR8 ROMDATA str2_F10_Am3_QC_T[] = "T Processor";
CONST CHAR8 ROMDATA str2_F10_Am3_SC_0T[] = "0T Processor";
CONST CHAR8 ROMDATA str2_F10_Am3_SC_5T[] = "5T Processor";
/*---------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*---------------------------------------------------------------------------------------
*/
CONST AMD_CPU_BRAND ROMDATA CpuF10BrandIdString1ArrayAm3[] =
{
// AM3
{1, 0, 0, DR_SOCKET_AM3, str_F10_Am3_SC_AthlonLE, sizeof (str_F10_Am3_SC_AthlonLE)},
{1, 0, 1, DR_SOCKET_AM3, str_F10_Am3_SC_SempronLE, sizeof (str_F10_Am3_SC_SempronLE)},
{1, 0, 2, DR_SOCKET_AM3, str_F10_Am3_SC_Sempron_1, sizeof (str_F10_Am3_SC_Sempron_1)},
{1, 0, 3, DR_SOCKET_AM3, str_F10_Am3_SC_Athlon_1, sizeof (str_F10_Am3_SC_Athlon_1)},
{2, 0, 0, DR_SOCKET_AM3, str_F10_Am3_DC_Opteron13, sizeof (str_F10_Am3_DC_Opteron13)},
{2, 0, 1, DR_SOCKET_AM3, str_F10_Am3_Athlon, sizeof (str_F10_Am3_Athlon)},
{2, 0, 2, DR_SOCKET_AM3, str_F10_Am3_Athlon_II_X2_4, sizeof (str_F10_Am3_Athlon_II_X2_4)},
{2, 0, 3, DR_SOCKET_AM3, str_F10_Am3_Athlon_II_X2_2, sizeof (str_F10_Am3_Athlon_II_X2_2)},
{2, 0, 4, DR_SOCKET_AM3, str_F10_Am3_Athlon_II_X2_B, sizeof (str_F10_Am3_Athlon_II_X2_B)},
{2, 0, 5, DR_SOCKET_AM3, str_F10_Am3_Athlon_II_X2, sizeof (str_F10_Am3_Athlon_II_X2)},
{2, 0, 6, DR_SOCKET_AM3, str_F10_Am3_Athlon_II_Neo_X2, sizeof (str_F10_Am3_Athlon_II_Neo_X2)},
{2, 0, 7, DR_SOCKET_AM3, str_F10_Am3_Phenom_II_X2_5, sizeof (str_F10_Am3_Phenom_II_X2_5)},
{2, 0, 8, DR_SOCKET_AM3, str_F10_Am3_Athlon_II_X2_5, sizeof (str_F10_Am3_Athlon_II_X2_5)},
{2, 0, 9, DR_SOCKET_AM3, str_F10_Am3_Athlon_II_X2_3, sizeof (str_F10_Am3_Athlon_II_X2_3)},
{2, 0, 10, DR_SOCKET_AM3, str_F10_Am3_Phenom_II_X2, sizeof (str_F10_Am3_Phenom_II_X2)},
{2, 0, 11, DR_SOCKET_AM3, str_F10_Am3_Phenom_II_X2_B, sizeof (str_F10_Am3_Phenom_II_X2_B)},
{2, 0, 12, DR_SOCKET_AM3, str_F10_Am3_Sempron_X2_1, sizeof (str_F10_Am3_Sempron_X2_1)},
{2, 1, 1, DR_SOCKET_AM3, str_F10_Am3_Athlon_II_XLT_V, sizeof (str_F10_Am3_Athlon_II_XLT_V)},
{2, 1, 2, DR_SOCKET_AM3, str_F10_Am3_Athlon_II_XL_V, sizeof (str_F10_Am3_Athlon_II_XL_V)},
{3, 0, 0, DR_SOCKET_AM3, str_F10_Am3_Phenom, sizeof (str_F10_Am3_Phenom)},
{3, 0, 1, DR_SOCKET_AM3, str_F10_Am3_Phenom_II_X3_5, sizeof (str_F10_Am3_Phenom_II_X3_5)},
{3, 0, 2, DR_SOCKET_AM3, str_F10_Am3_Phenom_II_X3_4, sizeof (str_F10_Am3_Phenom_II_X3_4)},
{3, 0, 3, DR_SOCKET_AM3, str_F10_Am3_Phenom_II_X3_B, sizeof (str_F10_Am3_Phenom_II_X3_B)},
{3, 0, 4, DR_SOCKET_AM3, str_F10_Am3_Phenom_II_X3, sizeof (str_F10_Am3_Phenom_II_X3)},
{3, 0, 5, DR_SOCKET_AM3, str_F10_Am3_Athlon_II_X3_3, sizeof (str_F10_Am3_Athlon_II_X3_3)},
{3, 0, 6, DR_SOCKET_AM3, str_F10_Am3_Athlon_II_Neo_X3, sizeof (str_F10_Am3_Athlon_II_Neo_X3)},
{3, 0, 7, DR_SOCKET_AM3, str_F10_Am3_Athlon_II_X3_4, sizeof (str_F10_Am3_Athlon_II_X3_4)},
{3, 0, 8, DR_SOCKET_AM3, str_F10_Am3_Phenom_II_X3_7, sizeof (str_F10_Am3_Phenom_II_X3_7)},
{3, 0, 9, DR_SOCKET_AM3, str_F10_Am3_Athlon_II_X3_B, sizeof (str_F10_Am3_Athlon_II_X3_B)},
{3, 0, 10, DR_SOCKET_AM3, str_F10_Am3_Athlon_II_X3, sizeof (str_F10_Am3_Athlon_II_X3)},
{4, 0, 0, DR_SOCKET_AM3, str_F10_Am3_QC_Opteron13, sizeof (str_F10_Am3_QC_Opteron13)},
{4, 0, 1, DR_SOCKET_AM3, str_F10_Am3_Phenom_FX, sizeof (str_F10_Am3_Phenom_FX)},
{4, 0, 2, DR_SOCKET_AM3, str_F10_Am3_Phenom, sizeof (str_F10_Am3_Phenom)},
{4, 0, 3, DR_SOCKET_AM3, str_F10_Am3_Phenom_II_X4_9, sizeof (str_F10_Am3_Phenom_II_X4_9)},
{4, 0, 4, DR_SOCKET_AM3, str_F10_Am3_Phenom_II_X4_8, sizeof (str_F10_Am3_Phenom_II_X4_8)},
{4, 0, 5, DR_SOCKET_AM3, str_F10_Am3_Phenom_II_X4_7, sizeof (str_F10_Am3_Phenom_II_X4_7)},
{4, 0, 6, DR_SOCKET_AM3, str_F10_Am3_Phenom_II_X4_6, sizeof (str_F10_Am3_Phenom_II_X4_6)},
{4, 0, 7, DR_SOCKET_AM3, str_F10_Am3_Phenom_II_X4_B, sizeof (str_F10_Am3_Phenom_II_X4_B)},
{4, 0, 8, DR_SOCKET_AM3, str_F10_Am3_Phenom_II_X4, sizeof (str_F10_Am3_Phenom_II_X4)},
{4, 0, 9, DR_SOCKET_AM3, str_F10_Am3_Phenom_II_Neo_X4, sizeof (str_F10_Am3_Phenom_II_Neo_X4)},
{4, 0, 10, DR_SOCKET_AM3, str_F10_Am3_Athlon_II_X4_6, sizeof (str_F10_Am3_Athlon_II_X4_6)},
{4, 0, 11, DR_SOCKET_AM3, str_F10_Am3_Athlon_II_X4_5, sizeof (str_F10_Am3_Athlon_II_X4_5)},
{4, 0, 12, DR_SOCKET_AM3, str_F10_Am3_Athlon_II_Neo_X4, sizeof (str_F10_Am3_Athlon_II_Neo_X4)},
{4, 0, 13, DR_SOCKET_AM3, str_F10_Am3_Athlon_II_X4_B, sizeof (str_F10_Am3_Athlon_II_X4_B)},
{4, 0, 14, DR_SOCKET_AM3, str_F10_Am3_Phenom_II__FX, sizeof (str_F10_Am3_Phenom_II__FX)},
{4, 0, 15, DR_SOCKET_AM3, str_F10_Am3_Athlon_II_X4, sizeof (str_F10_Am3_Athlon_II_X4)},
{4, 1, 0, DR_SOCKET_AM3, str_F10_Am3_Phenom_II, sizeof (str_F10_Am3_Phenom_II)},
{4, 1, 1, DR_SOCKET_AM3, str_F10_Am3_Phenom_II_XLT_Q, sizeof (str_F10_Am3_Phenom_II_XLT_Q)},
{4, 1, 2, DR_SOCKET_AM3, str_F10_Am3_Phenom_II_X4_9, sizeof (str_F10_Am3_Phenom_II_X4_9)},
{4, 1, 3, DR_SOCKET_AM3, str_F10_Am3_Phenom_II_X4_8, sizeof (str_F10_Am3_Phenom_II_X4_8)},
{4, 1, 4, DR_SOCKET_AM3, str_F10_Am3_Phenom_II_X4_6, sizeof (str_F10_Am3_Phenom_II_X4_6)},
{6, 0, 0, DR_SOCKET_AM3, str_F10_Am3_Phenom_II_X6_1, sizeof (str_F10_Am3_Phenom_II_X6_1)}
}; //Cores, page, index, socket, stringstart, stringlength
CONST AMD_CPU_BRAND ROMDATA CpuF10BrandIdString2ArrayAm3[] =
{
// AM3
{1, 0, 0x00, DR_SOCKET_AM3, str2_F10_Am3_00, sizeof (str2_F10_Am3_00)},
{1, 0, 0x01, DR_SOCKET_AM3, str2_F10_Am3_10, sizeof (str2_F10_Am3_10)},
{1, 0, 0x02, DR_SOCKET_AM3, str2_F10_Am3_20, sizeof (str2_F10_Am3_20)},
{1, 0, 0x03, DR_SOCKET_AM3, str2_F10_Am3_30, sizeof (str2_F10_Am3_30)},
{1, 0, 0x04, DR_SOCKET_AM3, str2_F10_Am3_40, sizeof (str2_F10_Am3_40)},
{1, 0, 0x05, DR_SOCKET_AM3, str2_F10_Am3_50, sizeof (str2_F10_Am3_50)},
{1, 0, 0x06, DR_SOCKET_AM3, str2_F10_Am3_60, sizeof (str2_F10_Am3_60)},
{1, 0, 0x07, DR_SOCKET_AM3, str2_F10_Am3_70, sizeof (str2_F10_Am3_70)},
{1, 0, 0x08, DR_SOCKET_AM3, str2_F10_Am3_80, sizeof (str2_F10_Am3_80)},
{1, 0, 0x09, DR_SOCKET_AM3, str2_F10_Am3_90, sizeof (str2_F10_Am3_90)},
{1, 0, 0x0A, DR_SOCKET_AM3, str2_F10_Am3_Processor, sizeof (str2_F10_Am3_Processor)},
{1, 0, 0x0B, DR_SOCKET_AM3, str2_F10_Am3_u_Processor, sizeof (str2_F10_Am3_u_Processor)},
{1, 0, 0x0F, DR_SOCKET_AM3, 0, 0}, //Size 0 for no suffix
{2, 0, 0x00, DR_SOCKET_AM3, str2_F10_Am3_DC_00, sizeof (str2_F10_Am3_DC_00)},
{2, 0, 0x01, DR_SOCKET_AM3, str2_F10_Am3_DC_00e, sizeof (str2_F10_Am3_DC_00e)},
{2, 0, 0x02, DR_SOCKET_AM3, str2_F10_Am3_DC_00B, sizeof (str2_F10_Am3_DC_00B)},
{2, 0, 0x03, DR_SOCKET_AM3, str2_F10_Am3_DC_50, sizeof (str2_F10_Am3_DC_50)},
{2, 0, 0x04, DR_SOCKET_AM3, str2_F10_Am3_DC_50e, sizeof (str2_F10_Am3_DC_50e)},
{2, 0, 0x05, DR_SOCKET_AM3, str2_F10_Am3_DC_50B, sizeof (str2_F10_Am3_DC_50B)},
{2, 0, 0x06, DR_SOCKET_AM3, str2_F10_Am3_Processor, sizeof (str2_F10_Am3_Processor)},
{2, 0, 0x07, DR_SOCKET_AM3, str2_F10_Am3_e_Processor, sizeof (str2_F10_Am3_e_Processor)},
{2, 0, 0x08, DR_SOCKET_AM3, str2_F10_Am3_B_Processor, sizeof (str2_F10_Am3_B_Processor)},
{2, 0, 0x09, DR_SOCKET_AM3, str2_F10_Am3_0_Processor, sizeof (str2_F10_Am3_0_Processor)},
{2, 0, 0x0A, DR_SOCKET_AM3, str2_F10_Am3_0e_Processor, sizeof (str2_F10_Am3_0e_Processor)},
{2, 0, 0x0B, DR_SOCKET_AM3, str2_F10_Am3_u_Processor, sizeof (str2_F10_Am3_u_Processor)},
{2, 0, 0x0F, DR_SOCKET_AM3, 0, 0}, // Size 0 for no suffix
{2, 1, 0x01, DR_SOCKET_AM3, str2_F10_Am3_L_Processor, sizeof (str2_F10_Am3_L_Processor)},
{2, 1, 0x02, DR_SOCKET_AM3, str2_F10_Am3_C_Processor, sizeof (str2_F10_Am3_C_Processor)},
{3, 0, 0x00, DR_SOCKET_AM3, str2_F10_Am3_TC_00, sizeof (str2_F10_Am3_TC_00)},
{3, 0, 0x01, DR_SOCKET_AM3, str2_F10_Am3_TC_00e, sizeof (str2_F10_Am3_TC_00e)},
{3, 0, 0x02, DR_SOCKET_AM3, str2_F10_Am3_TC_00B, sizeof (str2_F10_Am3_TC_00B)},
{3, 0, 0x03, DR_SOCKET_AM3, str2_F10_Am3_TC_50, sizeof (str2_F10_Am3_TC_50)},
{3, 0, 0x04, DR_SOCKET_AM3, str2_F10_Am3_TC_50e, sizeof (str2_F10_Am3_TC_50e)},
{3, 0, 0x05, DR_SOCKET_AM3, str2_F10_Am3_TC_50B, sizeof (str2_F10_Am3_TC_50B)},
{3, 0, 0x06, DR_SOCKET_AM3, str2_F10_Am3_Processor, sizeof (str2_F10_Am3_Processor)},
{3, 0, 0x07, DR_SOCKET_AM3, str2_F10_Am3_e_Processor, sizeof (str2_F10_Am3_e_Processor)},
{3, 0, 0x08, DR_SOCKET_AM3, str2_F10_Am3_B_Processor, sizeof (str2_F10_Am3_B_Processor)},
{3, 0, 0x09, DR_SOCKET_AM3, str2_F10_Am3_0e_Processor, sizeof (str2_F10_Am3_0e_Processor)},
{3, 0, 0x0A, DR_SOCKET_AM3, str2_F10_Am3_0_Processor, sizeof (str2_F10_Am3_0_Processor)},
{3, 0, 0x0F, DR_SOCKET_AM3, 0, 0}, //Size 0 for no suffix
{4, 0, 0x00, DR_SOCKET_AM3, str2_F10_Am3_QC_00, sizeof (str2_F10_Am3_QC_00)},
{4, 0, 0x01, DR_SOCKET_AM3, str2_F10_Am3_QC_00e, sizeof (str2_F10_Am3_QC_00e)},
{4, 0, 0x02, DR_SOCKET_AM3, str2_F10_Am3_QC_00B, sizeof (str2_F10_Am3_QC_00B)},
{4, 0, 0x03, DR_SOCKET_AM3, str2_F10_Am3_QC_50, sizeof (str2_F10_Am3_QC_50)},
{4, 0, 0x04, DR_SOCKET_AM3, str2_F10_Am3_QC_50e, sizeof (str2_F10_Am3_QC_50e)},
{4, 0, 0x05, DR_SOCKET_AM3, str2_F10_Am3_QC_50B, sizeof (str2_F10_Am3_QC_50B)},
{4, 0, 0x06, DR_SOCKET_AM3, str2_F10_Am3_Processor, sizeof (str2_F10_Am3_Processor)},
{4, 0, 0x07, DR_SOCKET_AM3, str2_F10_Am3_e_Processor, sizeof (str2_F10_Am3_e_Processor)},
{4, 0, 0x08, DR_SOCKET_AM3, str2_F10_Am3_B_Processor, sizeof (str2_F10_Am3_B_Processor)},
{4, 0, 0x09, DR_SOCKET_AM3, str2_F10_Am3_0e_Processor, sizeof (str2_F10_Am3_0e_Processor)},
{4, 0, 0x0A, DR_SOCKET_AM3, str2_F10_Am3_SE, sizeof (str2_F10_Am3_SE)},
{4, 0, 0x0B, DR_SOCKET_AM3, str2_F10_Am3_HE, sizeof (str2_F10_Am3_HE)},
{4, 0, 0x0C, DR_SOCKET_AM3, str2_F10_Am3_EE, sizeof (str2_F10_Am3_EE)},
{4, 0, 0x0D, DR_SOCKET_AM3, str2_F10_Am3_QCP, sizeof (str2_F10_Am3_QCP)},
{4, 0, 0x0E, DR_SOCKET_AM3, str2_F10_Am3_0_Processor, sizeof (str2_F10_Am3_0_Processor)},
{4, 0, 0x0F, DR_SOCKET_AM3, 0, 0}, //Size 0 for no suffix
{4, 1, 0x00, DR_SOCKET_AM3, str2_F10_Am3_TWKR_Black_Edition, sizeof (str2_F10_Am3_TWKR_Black_Edition)},
{4, 1, 0x01, DR_SOCKET_AM3, str2_F10_Am3_L_Processor, sizeof (str2_F10_Am3_L_Processor)},
{4, 1, 0x04, DR_SOCKET_AM3, str2_F10_Am3_QC_T, sizeof (str2_F10_Am3_QC_T)},
{6, 0, 0x00, DR_SOCKET_AM3, str2_F10_Am3_SC_5T, sizeof (str2_F10_Am3_SC_5T)},
{6, 0, 0x01, DR_SOCKET_AM3, str2_F10_Am3_SC_0T, sizeof (str2_F10_Am3_SC_0T)},
{6, 0, 0x0F, DR_SOCKET_AM3, 0, 0} //Size 0 for no suffix
};
CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString1ArrayAm3 = {
(sizeof (CpuF10BrandIdString1ArrayAm3) / sizeof (AMD_CPU_BRAND)),
CpuF10BrandIdString1ArrayAm3
};
CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayAm3 = {
(sizeof (CpuF10BrandIdString2ArrayAm3) / sizeof (AMD_CPU_BRAND)),
CpuF10BrandIdString2ArrayAm3
};

136
src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10BrandIdAsb2.c
View File

@ -1,136 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD CPU BrandId related functions and structures for package ASB2.
*
* Contains code that provides CPU BrandId information
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU
* @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
*
*/
/*
******************************************************************************
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "cpuRegisters.h"
#include "cpuEarlyInit.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G2_PEI)
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
// String1
CONST CHAR8 ROMDATA str_F10_Asb2_AMD_V[] = "AMD V";
CONST CHAR8 ROMDATA str_F10_Asb2_Athlon_II_Neo_K[] = "AMD Athlon(tm) II Neo K";
CONST CHAR8 ROMDATA str_F10_Asb2_Athlon_II_Neo_N[] = "AMD Athlon(tm) II Neo N";
CONST CHAR8 ROMDATA str_F10_Asb2_Athlon_II_Neo_R[] = "AMD Athlon(tm) II Neo R";
CONST CHAR8 ROMDATA str_F10_Asb2_Turion_II_Neo_K[] = "AMD Turion(tm) II Neo K";
CONST CHAR8 ROMDATA str_F10_Asb2_Turion_II_Neo_N[] = "AMD Turion(tm) II Neo N";
// String2
CONST CHAR8 ROMDATA str_F10_Asb2_5_Processor[] = "5 Processor";
CONST CHAR8 ROMDATA str_F10_Asb2_5_Dual_Core_Processor[] = "5 Dual-Core Processor";
CONST CHAR8 ROMDATA str_F10_Asb2_L_Processor[] = "L Processor";
CONST CHAR8 ROMDATA str_F10_Asb2_L_Dual_Core_Processor[] = "L Dual-Core Processor";
CONST CHAR8 ROMDATA str_F10_Asb2_H_Dual_Core_Processor[] = "H Dual-Core Processor";
/*---------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*---------------------------------------------------------------------------------------
*/
CONST AMD_CPU_BRAND ROMDATA CpuF10BrandIdString1ArrayAsb2[] =
{
// ASB2
{1, 0, 1, DR_SOCKET_ASB2, str_F10_Asb2_Athlon_II_Neo_K, sizeof (str_F10_Asb2_Athlon_II_Neo_K)},
{1, 0, 2, DR_SOCKET_ASB2, str_F10_Asb2_AMD_V, sizeof (str_F10_Asb2_AMD_V)},
{1, 0, 3, DR_SOCKET_ASB2, str_F10_Asb2_Athlon_II_Neo_R, sizeof (str_F10_Asb2_Athlon_II_Neo_R)},
{2, 0, 1, DR_SOCKET_ASB2, str_F10_Asb2_Turion_II_Neo_K, sizeof (str_F10_Asb2_Turion_II_Neo_K)},
{2, 0, 2, DR_SOCKET_ASB2, str_F10_Asb2_Athlon_II_Neo_K, sizeof (str_F10_Asb2_Athlon_II_Neo_K)},
{2, 0, 3, DR_SOCKET_ASB2, str_F10_Asb2_AMD_V, sizeof (str_F10_Asb2_AMD_V)},
{2, 0, 4, DR_SOCKET_ASB2, str_F10_Asb2_Turion_II_Neo_N, sizeof (str_F10_Asb2_Turion_II_Neo_N)},
{2, 0, 5, DR_SOCKET_ASB2, str_F10_Asb2_Athlon_II_Neo_N, sizeof (str_F10_Asb2_Athlon_II_Neo_N)}
}; //Cores, page, index, socket, stringstart, stringlength
CONST AMD_CPU_BRAND ROMDATA CpuF10BrandIdString2ArrayAsb2[] =
{
// ASB2
{1, 0, 0x01, DR_SOCKET_ASB2, str_F10_Asb2_5_Processor, sizeof (str_F10_Asb2_5_Processor)},
{1, 0, 0x02, DR_SOCKET_ASB2, str_F10_Asb2_L_Processor, sizeof (str_F10_Asb2_L_Processor)},
{2, 0, 0x01, DR_SOCKET_ASB2, str_F10_Asb2_5_Dual_Core_Processor, sizeof (str_F10_Asb2_5_Dual_Core_Processor)},
{2, 0, 0x02, DR_SOCKET_ASB2, str_F10_Asb2_L_Dual_Core_Processor, sizeof (str_F10_Asb2_L_Dual_Core_Processor)},
{2, 0, 0x04, DR_SOCKET_ASB2, str_F10_Asb2_H_Dual_Core_Processor, sizeof (str_F10_Asb2_H_Dual_Core_Processor)},
{1, 0, 0x0F, DR_SOCKET_ASB2, 0, 0}, //Size 0 for no suffix
{2, 0, 0x0F, DR_SOCKET_ASB2, 0, 0}, //Size 0 for no suffix
};
CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString1ArrayAsb2 = {
(sizeof (CpuF10BrandIdString1ArrayAsb2) / sizeof (AMD_CPU_BRAND)),
CpuF10BrandIdString1ArrayAsb2
};
CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayAsb2 = {
(sizeof (CpuF10BrandIdString2ArrayAsb2) / sizeof (AMD_CPU_BRAND)),
CpuF10BrandIdString2ArrayAsb2
};

135
src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10BrandIdC32.c
View File

@ -1,135 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD CPU BrandId related functions and structures for socket C32.
*
* Contains code that provides CPU BrandId information
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $
*
*/
/*
******************************************************************************
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "cpuRegisters.h"
#include "cpuEarlyInit.h"
CODE_GROUP (G2_PEI)
RDATA_GROUP (G2_PEI)
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
// PRIVATE FORMAT FOR BRAND TABLE ... FOR AMD USE ONLY
// String1
CONST CHAR8 ROMDATA str_F10_C32_Opteron_41[] = "AMD Opteron(tm) Processor 41";
CONST CHAR8 ROMDATA str_F10_C32_Embedded_Opteron[] = "Embedded AMD Opteron(tm) Processor ";
// String2
CONST CHAR8 ROMDATA str2_F10_C32_HE[] = " HE";
CONST CHAR8 ROMDATA str2_F10_C32_EE[] = " EE";
CONST CHAR8 ROMDATA str2_F10_C32_QS_HE[] = "QS HE";
CONST CHAR8 ROMDATA str2_F10_C32_LE_HE[] = "LE HE";
CONST CHAR8 ROMDATA str2_F10_C32_KX_HE[] = "KX HE";
CONST CHAR8 ROMDATA str2_F10_C32_GL_EE[] = "GL EE";
CONST CHAR8 ROMDATA str2_F10_C32_CL_EE[] = "CL EE";
/*---------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*---------------------------------------------------------------------------------------
*/
CONST AMD_CPU_BRAND ROMDATA CpuF10BrandIdString1ArrayC32[] =
{
// C32r1 string1:
{4, 0, 0x00, DR_SOCKET_C32, str_F10_C32_Opteron_41, sizeof (str_F10_C32_Opteron_41)},
{4, 1, 0x01, DR_SOCKET_C32, str_F10_C32_Embedded_Opteron, sizeof (str_F10_C32_Embedded_Opteron)},
{6, 0, 0x00, DR_SOCKET_C32, str_F10_C32_Opteron_41, sizeof (str_F10_C32_Opteron_41)},
{6, 1, 0x01, DR_SOCKET_C32, str_F10_C32_Embedded_Opteron, sizeof (str_F10_C32_Embedded_Opteron)}
}; //Cores, page, index, socket, stringstart, stringlength
CONST AMD_CPU_BRAND ROMDATA CpuF10BrandIdString2ArrayC32[] =
{
// C32r1 string2:
{4, 0, 0x00, DR_SOCKET_C32, str2_F10_C32_HE, sizeof (str2_F10_C32_HE)},
{4, 0, 0x01, DR_SOCKET_C32, str2_F10_C32_EE, sizeof (str2_F10_C32_EE)},
{4, 0, 0x0F, DR_SOCKET_C32, 0, 0}, //Size 0 for no suffix
{4, 1, 0x01, DR_SOCKET_C32, str2_F10_C32_QS_HE, sizeof (str2_F10_C32_QS_HE)},
{4, 1, 0x02, DR_SOCKET_C32, str2_F10_C32_LE_HE, sizeof (str2_F10_C32_LE_HE)},
{4, 1, 0x03, DR_SOCKET_C32, str2_F10_C32_CL_EE, sizeof (str2_F10_C32_CL_EE)},
{6, 0, 0x00, DR_SOCKET_C32, str2_F10_C32_HE, sizeof (str2_F10_C32_HE)},
{6, 0, 0x01, DR_SOCKET_C32, str2_F10_C32_EE, sizeof (str2_F10_C32_EE)},
{6, 0, 0x0F, DR_SOCKET_C32, 0, 0}, //Size 0 for no suffix
{6, 1, 0x01, DR_SOCKET_C32, str2_F10_C32_KX_HE, sizeof (str2_F10_C32_KX_HE)},
{6, 1, 0x02, DR_SOCKET_C32, str2_F10_C32_GL_EE, sizeof (str2_F10_C32_GL_EE)}
};
CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString1ArrayC32 = {
(sizeof (CpuF10BrandIdString1ArrayC32) / sizeof (AMD_CPU_BRAND)),
CpuF10BrandIdString1ArrayC32
};
CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayC32 = {
(sizeof (CpuF10BrandIdString2ArrayC32) / sizeof (AMD_CPU_BRAND)),
CpuF10BrandIdString2ArrayC32
};

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