soc/intel/skylake: Add function to clear PMCON status bits

This patch adds an SoC function to clear GEN_PMCON_A status bits to
align with other IA coreboot implementations.

Additionally, move the PMCON status bit clear operation to finalize.c
to cover any such chances where FSP-S NotifyPhase requested a global
reset and PMCON status bit remains set.

BUG=b:211954778
TEST=None.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ie786e6ba2daf88accb5d70be33de0abe593f8c53
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61650
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>

src/soc/intel/skylake/pmutil.c

@@ -265,3 +265,18 @@ void pmc_soc_set_afterg3_en(const bool on)
 		reg8 |= SLEEP_AFTER_POWER_FAIL;
 	pci_write_config8(dev, GEN_PMCON_B, reg8);
 }
+
+void pmc_clear_pmcon_sts(void)
+{
+	uint32_t reg_val;
+	const pci_devfn_t dev = PCH_DEV_PMC;
+
+	reg_val = pci_read_config32(dev, GEN_PMCON_A);
+	/*
+	 * Clear SUS_PWR_FLR, GBL_RST_STS, HOST_RST_STS, PWR_FLR bits
+	 * while retaining MS4V write-1-to-clear bit
+	 */
+	reg_val &= ~(MS4V);
+
+	pci_write_config32(dev, GEN_PMCON_A, reg_val);
+}