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mb/google/brox: Configure vGPIOs for NVMe

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This is needed for NVMe to work when PCIe device is connected to the
CPU side of RPL soc.

BUG=b:311450057,b:300690448, b:319058143
BRANCH=None
TEST=Tested on device and was able to boot to the OS

Change-Id: Ic8a1fdcedf2ec6c7bf1dd00e02ef7c13e9338aac
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79857
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
This commit is contained in:
Shelley Chen
2024-01-08 23:35:18 -08:00
parent c881c9ed2b
commit 1154bcd60c
1 changed files with 22 additions and 0 deletions
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22
src/mainboard/google/brox/variants/baseboard/brox/gpio.c
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@@ -395,6 +395,28 @@ static const struct pad_config early_gpio_table[] = {
PAD_CFG_NF(GPP_H11, NONE, PLTRST, NF2), PAD_CFG_NF(GPP_H11, NONE, PLTRST, NF2),
/* GPP_S0 : SNDW0_CLL/I2S1_SCLK ==> MEM_CH_SEL */ /* GPP_S0 : SNDW0_CLL/I2S1_SCLK ==> MEM_CH_SEL */
PAD_CFG_GPI(GPP_S0, NONE, DEEP), PAD_CFG_GPI(GPP_S0, NONE, DEEP),
/* CPU PCIe VGPIO for PEG60 */
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, PLTRST, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, PLTRST, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, PLTRST, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, PLTRST, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, PLTRST, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, PLTRST, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, PLTRST, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, PLTRST, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, PLTRST, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, PLTRST, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, PLTRST, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, PLTRST, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, PLTRST, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, PLTRST, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, PLTRST, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, PLTRST, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, PLTRST, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, PLTRST, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, PLTRST, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, PLTRST, NF1),
}; };
static const struct pad_config romstage_gpio_table[] = { static const struct pad_config romstage_gpio_table[] = {