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soc/intel/cnl: Configure FSP option PcieRpSlotImplemented

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Allow configuring FSP option PcieRpSlotImplemented. Also, update all
related devicetrees and configure PcieRpSlotImplemented to keep the
current behaviour.

Change-Id: I6c57ab0ae50a37cd9a90786134e9056851a86a3c
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Signed-off-by: Felix Singer <felix.singer@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Nico Huber
2019-10-02 16:02:06 +02:00
committed by Nico Huber
parent 2b9035ed6e
commit 119ace0908
23 changed files with 171 additions and 50 deletions
Download Patch File Download Diff File Expand all files Collapse all files

12
src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
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@@ -124,12 +124,18 @@ chip soc/intel/cannonlake
device pci 19.1 off end # I2C #5
device pci 19.2 on end # UART #2
device pci 1a.0 on end # eMMC
device pci 1c.0 on end # PCI Express Port 1 x4 SLOT1
device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN
device pci 1c.0 on # PCI Express Port 1 x4 SLOT1
register "PcieRpSlotImplemented[0]" = "1"
end
device pci 1c.4 on # PCI Express Port 5 x1 SLOT2/LAN
register "PcieRpSlotImplemented[4]" = "1"
end
device pci 1c.5 off end # PCI Express Port 6
device pci 1c.6 off end # PCI Express Port 7
device pci 1c.7 off end # PCI Express Port 8
device pci 1d.0 on end # PCI Express Port 9
device pci 1d.0 on # PCI Express Port 9
register "PcieRpSlotImplemented[8]" = "1"
end
device pci 1d.1 off end # PCI Express Port 10
device pci 1d.2 off end # PCI Express Port 11
device pci 1d.3 off end # PCI Express Port 12

12
src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
View File

@@ -140,12 +140,18 @@ chip soc/intel/cannonlake
device pci 19.1 off end # I2C #5
device pci 19.2 on end # UART #2
device pci 1a.0 on end # eMMC
device pci 1c.0 on end # PCI Express Port 1 x4 SLOT1
device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN
device pci 1c.0 on # PCI Express Port 1 x4 SLOT1
register "PcieRpSlotImplemented[0]" = "1"
end
device pci 1c.4 on # PCI Express Port 5 x1 SLOT2/LAN
register "PcieRpSlotImplemented[4]" = "1"
end
device pci 1c.5 off end # PCI Express Port 6
device pci 1c.6 off end # PCI Express Port 7
device pci 1c.7 off end # PCI Express Port 8
device pci 1d.0 on end # PCI Express Port 9
device pci 1d.0 on # PCI Express Port 9
register "PcieRpSlotImplemented[8]" = "1"
end
device pci 1d.1 off end # PCI Express Port 10
device pci 1d.2 off end # PCI Express Port 11
device pci 1d.3 off end # PCI Express Port 12

12
src/mainboard/intel/coffeelake_rvp/variants/cfl_h/overridetree.cb
View File

@@ -99,12 +99,18 @@ chip soc/intel/cannonlake
device pci 19.1 off end # I2C #5 (Not available on PCH-H)
device pci 19.2 on end # UART #2
device pci 1a.0 on end # eMMC
device pci 1c.0 on end # PCI Express Port 1 x4 SLOT1
device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN
device pci 1c.0 on # PCI Express Port 1 x4 SLOT1
register "PcieRpSlotImplemented[0]" = "1"
end
device pci 1c.4 on # PCI Express Port 5 x1 SLOT2/LAN
register "PcieRpSlotImplemented[4]" = "1"
end
device pci 1c.5 off end # PCI Express Port 6
device pci 1c.6 off end # PCI Express Port 7
device pci 1c.7 off end # PCI Express Port 8
device pci 1d.0 on end # PCI Express Port 9
device pci 1d.0 on # PCI Express Port 9
register "PcieRpSlotImplemented[8]" = "1"
end
device pci 1d.4 off end # PCI Express Port 13
device pci 1d.5 off end # PCI Express Port 14
device pci 1d.6 off end # PCI Express Port 15

32
src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb
View File

@@ -107,12 +107,18 @@ chip soc/intel/cannonlake
device pci 19.1 off end # I2C #5 (Not available on PCH-H)
device pci 19.2 on end # UART #2
device pci 1a.0 on end # eMMC
device pci 1c.0 on end # PCI Express Port 1
device pci 1c.4 on end # PCI Express Port 5
device pci 1c.0 on # PCI Express Port 1
register "PcieRpSlotImplemented[0]" = "1"
end
device pci 1c.4 on # PCI Express Port 5
register "PcieRpSlotImplemented[4]" = "1"
end
device pci 1c.5 off end # PCI Express Port 6
device pci 1c.6 off end # PCI Express Port 7
device pci 1c.7 off end # PCI Express Port 8
device pci 1d.0 on end # PCI Express Port 9 x4 SLOT 1
device pci 1d.0 on # PCI Express Port 9 x4 SLOT 1
register "PcieRpSlotImplemented[8]" = "1"
end
device pci 1d.1 off end # PCI Express Port 10
device pci 1d.2 off end # PCI Express Port 11
device pci 1d.3 off end # PCI Express Port 12
@@ -120,11 +126,21 @@ chip soc/intel/cannonlake
device pci 1d.5 off end # PCI Express Port 14
device pci 1d.6 off end # PCI Express Port 15
device pci 1d.7 off end # PCI Express Port 16
device pci 1b.0 on end # PCI Express Port 17
device pci 1b.1 on end # PCI Express Port 18
device pci 1b.2 on end # PCI Express Port 19
device pci 1b.3 on end # PCI Express Port 20
device pci 1b.4 on end # PCI Express Port 21 X4 SLOT 2
device pci 1b.0 on # PCI Express Port 17
register "PcieRpSlotImplemented[16]" = "1"
end
device pci 1b.1 on # PCI Express Port 18
register "PcieRpSlotImplemented[17]" = "1"
end
device pci 1b.2 on # PCI Express Port 19
register "PcieRpSlotImplemented[18]" = "1"
end
device pci 1b.3 on # PCI Express Port 20
register "PcieRpSlotImplemented[19]" = "1"
end
device pci 1b.4 on # PCI Express Port 21 X4 SLOT 2
register "PcieRpSlotImplemented[20]" = "1"
end
device pci 1e.1 off end # UART #1
device pci 1f.6 on end # GbE
end

12
src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb
View File

@@ -84,12 +84,18 @@ chip soc/intel/cannonlake
device pci 19.1 off end # I2C #5
device pci 19.2 on end # UART #2
device pci 1a.0 on end # eMMC
device pci 1c.0 on end # PCI Express Port 1 x4 SLOT1
device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN
device pci 1c.0 on # PCI Express Port 1 x4 SLOT1
register "PcieRpSlotImplemented[0]" = "1"
end
device pci 1c.4 on # PCI Express Port 5 x1 SLOT2/LAN
register "PcieRpSlotImplemented[4]" = "1"
end
device pci 1c.5 off end # PCI Express Port 6
device pci 1c.6 off end # PCI Express Port 7
device pci 1c.7 off end # PCI Express Port 8
device pci 1d.0 on end # PCI Express Port 9
device pci 1d.0 on # PCI Express Port 9
register "PcieRpSlotImplemented[8]" = "1"
end
device pci 1d.1 off end # PCI Express Port 10
device pci 1d.2 off end # PCI Express Port 11
device pci 1d.3 off end # PCI Express Port 12

12
src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb
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@@ -94,12 +94,18 @@ chip soc/intel/cannonlake
device pci 19.1 off end # I2C #5
device pci 19.2 on end # UART #2
device pci 1a.0 on end # eMMC
device pci 1c.0 on end # PCI Express Port 1 x4 SLOT1
device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN
device pci 1c.0 on # PCI Express Port 1 x4 SLOT1
register "PcieRpSlotImplemented[0]" = "1"
end
device pci 1c.4 on # PCI Express Port 5 x1 SLOT2/LAN
register "PcieRpSlotImplemented[4]" = "1"
end
device pci 1c.5 off end # PCI Express Port 6
device pci 1c.6 off end # PCI Express Port 7
device pci 1c.7 off end # PCI Express Port 8
device pci 1d.0 on end # PCI Express Port 9
device pci 1d.0 on # PCI Express Port 9
register "PcieRpSlotImplemented[8]" = "1"
end
device pci 1d.1 off end # PCI Express Port 10
device pci 1d.2 off end # PCI Express Port 11
device pci 1d.3 off end # PCI Express Port 12

12
src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb
View File

@@ -78,12 +78,18 @@ chip soc/intel/cannonlake
device pci 19.1 off end # I2C #5
device pci 19.2 on end # UART #2
device pci 1a.0 on end # eMMC
device pci 1c.0 on end # PCI Express Port 1 x4 SLOT1
device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN
device pci 1c.0 on # PCI Express Port 1 x4 SLOT1
register "PcieRpSlotImplemented[0]" = "1"
end
device pci 1c.4 on # PCI Express Port 5 x1 SLOT2/LAN
register "PcieRpSlotImplemented[4]" = "1"
end
device pci 1c.5 off end # PCI Express Port 6
device pci 1c.6 off end # PCI Express Port 7
device pci 1c.7 off end # PCI Express Port 8
device pci 1d.0 on end # PCI Express Port 9
device pci 1d.0 on # PCI Express Port 9
register "PcieRpSlotImplemented[8]" = "1"
end
device pci 1d.1 off end # PCI Express Port 10
device pci 1d.2 off end # PCI Express Port 11
device pci 1d.3 off end # PCI Express Port 12