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Replace some ENV_ROMSTAGE with ENV_RAMINIT

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With a combined bootblock+romstage ENV_ROMSTAGE might no
longer evaluate true.

Change-Id: I733cf4e4ab177e35cd260318556ece1e73d082dc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63376
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This commit is contained in:
Kyösti Mälkki
2022-04-07 07:16:48 +03:00
committed by Felix Held
parent 0310d34c2f
commit 11cac784ff
21 changed files with 26 additions and 25 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
src/drivers/amd/agesa/def_callouts.c
View File

@ -129,7 +129,7 @@ AGESA_STATUS agesa_GfxGetVbiosImage(UINT32 Func, UINTN FchData, VOID *ConfigPrt)
AGESA_STATUS agesa_ReadSpd (UINT32 Func, UINTN Data, VOID *ConfigPtr) AGESA_STATUS agesa_ReadSpd (UINT32 Func, UINTN Data, VOID *ConfigPtr)
{ {
if (!ENV_ROMSTAGE) if (!ENV_RAMINIT)
return AGESA_UNSUPPORTED; return AGESA_UNSUPPORTED;
return AmdMemoryReadSPD (Func, Data, ConfigPtr); return AmdMemoryReadSPD (Func, Data, ConfigPtr);
@ -139,7 +139,7 @@ AGESA_STATUS agesa_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *ConfigPtr)
{ {
AGESA_READ_SPD_PARAMS *info = ConfigPtr; AGESA_READ_SPD_PARAMS *info = ConfigPtr;
if (!ENV_ROMSTAGE) if (!ENV_RAMINIT)
return AGESA_UNSUPPORTED; return AGESA_UNSUPPORTED;
if (info->MemChannelId > 0) if (info->MemChannelId > 0)

4
src/drivers/amd/agesa/state_machine.c
View File

@ -18,7 +18,7 @@
#include "Dispatcher.h" #include "Dispatcher.h"
#endif #endif
#if ENV_ROMSTAGE #if ENV_RAMINIT
#include <PlatformMemoryConfiguration.h> #include <PlatformMemoryConfiguration.h>
CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {PSO_END}; CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {PSO_END};
#endif #endif
@ -262,7 +262,7 @@ int agesa_execute_state(struct sysinfo *cb, AGESA_STRUCT_NAME func)
if (CONFIG(AGESA_EXTRA_TIMESTAMPS) && task.ts_entry_id) if (CONFIG(AGESA_EXTRA_TIMESTAMPS) && task.ts_entry_id)
timestamp_add_now(task.ts_entry_id); timestamp_add_now(task.ts_entry_id);
if (ENV_ROMSTAGE) if (ENV_RAMINIT)
final = romstage_dispatch(cb, func, StdHeader); final = romstage_dispatch(cb, func, StdHeader);
if (ENV_RAMSTAGE) if (ENV_RAMSTAGE)

2
src/drivers/intel/fsp2_0/hand_off_block.c
View File

@ -115,7 +115,7 @@ const void *fsp_get_hob_list(void)
{ {
uint32_t *list_loc; uint32_t *list_loc;
if (ENV_ROMSTAGE) if (ENV_RAMINIT)
return fsp_hob_list_ptr; return fsp_hob_list_ptr;
list_loc = cbmem_find(CBMEM_ID_FSP_RUNTIME); list_loc = cbmem_find(CBMEM_ID_FSP_RUNTIME);
return (list_loc) ? (void *)(uintptr_t)(*list_loc) : NULL; return (list_loc) ? (void *)(uintptr_t)(*list_loc) : NULL;

4
src/drivers/intel/fsp2_0/util.c
View File

@ -77,7 +77,7 @@ enum cb_err fsp_validate_component(struct fsp_header *hdr, void *fsp_file, size_
return CB_ERR; return CB_ERR;
} }
if (ENV_ROMSTAGE) if (ENV_RAMINIT)
soc_validate_fspm_header(hdr); soc_validate_fspm_header(hdr);
return CB_SUCCESS; return CB_SUCCESS;
@ -118,7 +118,7 @@ void fsp_handle_reset(uint32_t status)
static inline bool fspm_env(void) static inline bool fspm_env(void)
{ {
if (ENV_ROMSTAGE) if (ENV_RAMINIT)
return true; return true;
return false; return false;
} }

1
src/include/rules.h
View File

@ -294,6 +294,7 @@
#define ENV_CREATES_CBMEM ENV_ROMSTAGE #define ENV_CREATES_CBMEM ENV_ROMSTAGE
#define ENV_HAS_CBMEM (ENV_ROMSTAGE | ENV_POSTCAR | ENV_RAMSTAGE) #define ENV_HAS_CBMEM (ENV_ROMSTAGE | ENV_POSTCAR | ENV_RAMSTAGE)
#define ENV_RAMINIT ENV_ROMSTAGE
#if ENV_X86 #if ENV_X86
#define ENV_HAS_SPINLOCKS !ENV_ROMSTAGE_OR_BEFORE #define ENV_HAS_SPINLOCKS !ENV_ROMSTAGE_OR_BEFORE

2
src/lib/cbfs.c
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@ -106,7 +106,7 @@ static inline bool fsps_env(void)
static inline bool fspm_env(void) static inline bool fspm_env(void)
{ {
/* FSP-M is assumed to be loaded in romstage. */ /* FSP-M is assumed to be loaded in romstage. */
if (ENV_ROMSTAGE) if (ENV_RAMINIT)
return true; return true;
return false; return false;
} }

2
src/mainboard/bap/ode_e20XX/BiosCallOuts.c
View File

@ -180,7 +180,7 @@ static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *Confi
AGESA_READ_SPD_PARAMS *info = ConfigPtr; AGESA_READ_SPD_PARAMS *info = ConfigPtr;
u8 index; u8 index;
if (!ENV_ROMSTAGE) if (!ENV_RAMINIT)
return AGESA_UNSUPPORTED; return AGESA_UNSUPPORTED;
if (CONFIG(BAP_E20_DDR3_1066)) if (CONFIG(BAP_E20_DDR3_1066))

2
src/mainboard/lippert/frontrunner-af/sema.c
View File

@ -53,7 +53,7 @@ int sema_send_alive(void)
char one_spd_byte; char one_spd_byte;
/* Fake read just to setup SMBUS controller. */ /* Fake read just to setup SMBUS controller. */
if (ENV_ROMSTAGE) if (ENV_RAMINIT)
smbus_readSpd(0xa0, &one_spd_byte, 1); smbus_readSpd(0xa0, &one_spd_byte, 1);
/* Notify the SMC we're alive and kicking, or after a while it will /* Notify the SMC we're alive and kicking, or after a while it will

2
src/mainboard/pcengines/apu1/BiosCallOuts.c
View File

@ -38,7 +38,7 @@ static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *Confi
{ {
AGESA_READ_SPD_PARAMS *info = ConfigPtr; AGESA_READ_SPD_PARAMS *info = ConfigPtr;
if (!ENV_ROMSTAGE) if (!ENV_RAMINIT)
return AGESA_UNSUPPORTED; return AGESA_UNSUPPORTED;
u8 index = get_spd_offset(); u8 index = get_spd_offset();

2
src/mainboard/pcengines/apu2/BiosCallOuts.c
View File

@ -107,7 +107,7 @@ static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *Confi
{ {
AGESA_READ_SPD_PARAMS *info = ConfigPtr; AGESA_READ_SPD_PARAMS *info = ConfigPtr;
if (!ENV_ROMSTAGE) if (!ENV_RAMINIT)
return AGESA_UNSUPPORTED; return AGESA_UNSUPPORTED;
u8 index = get_spd_offset(); u8 index = get_spd_offset();

4
src/soc/amd/common/pi/agesawrapper.c
View File

@ -68,7 +68,7 @@ static AGESA_STATUS amd_create_struct(AMD_INTERFACE_PARAMS *aip,
aip->NewStructPtr = buf; aip->NewStructPtr = buf;
aip->NewStructSize = len; aip->NewStructSize = len;
} else { } else {
if (ENV_ROMSTAGE) if (ENV_RAMINIT)
aip->AllocationMethod = PreMemHeap; aip->AllocationMethod = PreMemHeap;
if (ENV_RAMSTAGE) if (ENV_RAMSTAGE)
aip->AllocationMethod = PostMemDram; aip->AllocationMethod = PostMemDram;
@ -412,7 +412,7 @@ AGESA_STATUS agesa_execute_state(AGESA_STRUCT_NAME func)
StdHeader = aip->NewStructPtr; StdHeader = aip->NewStructPtr;
StdHeader->Func = func; StdHeader->Func = func;
if (ENV_ROMSTAGE) if (ENV_RAMINIT)
status = romstage_dispatch(StdHeader); status = romstage_dispatch(StdHeader);
if (ENV_RAMSTAGE) if (ENV_RAMSTAGE)
status = ramstage_dispatch(StdHeader); status = ramstage_dispatch(StdHeader);

2
src/soc/amd/common/pi/def_callouts.c
View File

@ -23,7 +23,7 @@ const BIOS_CALLOUT_STRUCT BiosCallouts[] = {
#else #else
const BIOS_CALLOUT_STRUCT BiosCallouts[] = { const BIOS_CALLOUT_STRUCT BiosCallouts[] = {
/* Required callouts */ /* Required callouts */
#if ENV_ROMSTAGE #if ENV_RAMINIT
{ AGESA_HALT_THIS_AP, agesa_HaltThisAp }, { AGESA_HALT_THIS_AP, agesa_HaltThisAp },
#endif #endif
{ AGESA_ALLOCATE_BUFFER, agesa_AllocateBuffer }, { AGESA_ALLOCATE_BUFFER, agesa_AllocateBuffer },

2
src/soc/amd/stoneyridge/BiosCallOuts.c
View File

@ -86,7 +86,7 @@ AGESA_STATUS agesa_ReadSpd(uint32_t Func, uintptr_t Data, void *ConfigPtr)
DEVTREE_CONST struct soc_amd_stoneyridge_config *conf; DEVTREE_CONST struct soc_amd_stoneyridge_config *conf;
AGESA_READ_SPD_PARAMS *info = ConfigPtr; AGESA_READ_SPD_PARAMS *info = ConfigPtr;
if (!ENV_ROMSTAGE) if (!ENV_RAMINIT)
return AGESA_UNSUPPORTED; return AGESA_UNSUPPORTED;
dev = pcidev_path_on_root(DCT_DEVFN); dev = pcidev_path_on_root(DCT_DEVFN);

2
src/soc/cavium/cn81xx/sdram.c
View File

@ -29,7 +29,7 @@ size_t sdram_size_mb(void)
#define BDK_RNM_CTL_STATUS 0 #define BDK_RNM_CTL_STATUS 0
#define BDK_RNM_RANDOM 0x100000 #define BDK_RNM_RANDOM 0x100000
#if ENV_ROMSTAGE #if ENV_RAMINIT
/* Enable RNG for DRAM init */ /* Enable RNG for DRAM init */
static void rnm_init(void) static void rnm_init(void)
{ {

2
src/soc/mediatek/mt8186/emi.c
View File

@ -15,7 +15,7 @@ size_t sdram_size(void)
const struct mem_chip_info *mc; const struct mem_chip_info *mc;
size_t size = 0; size_t size = 0;
if (ENV_ROMSTAGE) { if (ENV_RAMINIT) {
size = mtk_dram_size(); size = mtk_dram_size();
printk(BIOS_INFO, "dram size (romstage): %#lx\n", size); printk(BIOS_INFO, "dram size (romstage): %#lx\n", size);
return size; return size;

4
src/soc/sifive/fu540/clock.c
View File

@ -56,7 +56,7 @@ static struct prci_ctlr *prci = (void *)FU540_PRCI;
#define PRCI_DEVICESRESET_GEMGXL_RST_N(x) (((x) & 0x1) << 5) #define PRCI_DEVICESRESET_GEMGXL_RST_N(x) (((x) & 0x1) << 5)
/* Clock initialization should only be done in romstage. */ /* Clock initialization should only be done in romstage. */
#if ENV_ROMSTAGE #if ENV_RAMINIT
struct pll_settings { struct pll_settings {
unsigned int divr:6; unsigned int divr:6;
unsigned int divf:9; unsigned int divf:9;
@ -247,7 +247,7 @@ void clock_init(void)
asm volatile ("fence"); asm volatile ("fence");
} }
#endif /* ENV_ROMSTAGE */ #endif /* ENV_RAMINIT */
/* Get the core clock's frequency, in KHz */ /* Get the core clock's frequency, in KHz */
int clock_get_coreclk_khz(void) int clock_get_coreclk_khz(void)

2
src/southbridge/intel/bd82x6x/early_pch.c
View File

@ -310,6 +310,6 @@ void early_pch_init(void)
setup_pch_gpios(&mainboard_gpio_map); setup_pch_gpios(&mainboard_gpio_map);
if (ENV_ROMSTAGE) if (ENV_RAMINIT)
enable_smbus(); enable_smbus();
} }

2
src/southbridge/intel/i82801gx/early_init.c
View File

@ -57,7 +57,7 @@ void i82801gx_setup_bars(void)
#define TCO_BASE 0x60 #define TCO_BASE 0x60
#if ENV_ROMSTAGE #if ENV_RAMINIT
void i82801gx_early_init(void) void i82801gx_early_init(void)
{ {
enable_smbus(); enable_smbus();

2
src/southbridge/intel/i82801ix/early_init.c
View File

@ -47,7 +47,7 @@ void i82801ix_early_init(void)
{ {
const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0); const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0);
if (ENV_ROMSTAGE) if (ENV_RAMINIT)
enable_smbus(); enable_smbus();
/* Set up RCBA. */ /* Set up RCBA. */

2
src/southbridge/intel/i82801jx/early_init.c
View File

@ -69,7 +69,7 @@ void i82801jx_early_init(void)
{ {
const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0); const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0);
if (ENV_ROMSTAGE) if (ENV_RAMINIT)
enable_smbus(); enable_smbus();
printk(BIOS_DEBUG, "Setting up static southbridge registers..."); printk(BIOS_DEBUG, "Setting up static southbridge registers...");

2
src/vendorcode/amd/agesa/common/agesa-entry-cfg.h
View File

@ -2,7 +2,7 @@
#define AGESA_ENTRY_CFG_H #define AGESA_ENTRY_CFG_H
#if ENV_ROMSTAGE #if ENV_RAMINIT
#define AGESA_ENTRY_INIT_RESET TRUE #define AGESA_ENTRY_INIT_RESET TRUE
#define AGESA_ENTRY_INIT_EARLY TRUE #define AGESA_ENTRY_INIT_EARLY TRUE