sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

mb/gigabyte/ga-g41m-es2l: Add timestamps in romstage

Browse Source 
Change-Id: I93f43a0af41ae86f1b8ba33e28f3b9f060a5ab5e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19513
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Arthur Heymans
2017-05-01 18:33:39 +02:00
parent bd23bd62b4
commit 1222162d12
1 changed files with 6 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
src/mainboard/gigabyte/ga-g41m-es2l/romstage.c
View File

@@ -31,6 +31,7 @@
#include <arch/stages.h> #include <arch/stages.h>
#include <cbmem.h> #include <cbmem.h>
#include <northbridge/intel/x4x/iomap.h> #include <northbridge/intel/x4x/iomap.h>
#include <timestamp.h>
#define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) #define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1)
#define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO) #define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO)
@@ -135,6 +136,9 @@ void mainboard_romstage_entry(unsigned long bist)
u8 boot_path = 0; u8 boot_path = 0;
u8 s3_resume; u8 s3_resume;
timestamp_init(get_initial_timestamp());
timestamp_add_now(TS_START_ROMSTAGE);
/* Disable watchdog timer */ /* Disable watchdog timer */
RCBA32(0x3410) = RCBA32(0x3410) | 0x20; RCBA32(0x3410) = RCBA32(0x3410) | 0x20;
@@ -160,7 +164,9 @@ void mainboard_romstage_entry(unsigned long bist)
boot_path = BOOT_PATH_WARM_RESET; boot_path = BOOT_PATH_WARM_RESET;
printk(BIOS_DEBUG, "Initializing memory\n"); printk(BIOS_DEBUG, "Initializing memory\n");
timestamp_add_now(TS_BEFORE_INITRAM);
sdram_initialize(boot_path, spd_addrmap); sdram_initialize(boot_path, spd_addrmap);
timestamp_add_now(TS_AFTER_INITRAM);
quick_ram_check(); quick_ram_check();
printk(BIOS_DEBUG, "Memory initialized\n"); printk(BIOS_DEBUG, "Memory initialized\n");