soc/intel/common/block/fast_spi: Clean up header
Suffix `SPIBAR_HWSEQ_XFER_TIMEOUT` with its units, use lowercase for hex values and rename BIOS_CONTROL macros, as the register is not in SPIBAR. Change-Id: I3bc1f5a5ebc4c562536829e63550c0b562b67874 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50752 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Angel Pons
parent
405f229689
commit
122cc8c61d
@ -42,16 +42,16 @@ void fast_spi_init(void)
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const pci_devfn_t dev = PCH_DEV_SPI;
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uint8_t bios_cntl;
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bios_cntl = pci_read_config8(dev, SPIBAR_BIOS_CONTROL);
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bios_cntl = pci_read_config8(dev, SPI_BIOS_CONTROL);
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/* Disable the BIOS write protect so write commands are allowed. */
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bios_cntl &= ~SPIBAR_BIOS_CONTROL_EISS;
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bios_cntl |= SPIBAR_BIOS_CONTROL_WPD;
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bios_cntl &= ~SPI_BIOS_CONTROL_EISS;
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bios_cntl |= SPI_BIOS_CONTROL_WPD;
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/* Enable Prefetching and caching. */
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bios_cntl |= SPIBAR_BIOS_CONTROL_PREFETCH_ENABLE;
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bios_cntl &= ~SPIBAR_BIOS_CONTROL_CACHE_DISABLE;
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bios_cntl |= SPI_BIOS_CONTROL_PREFETCH_ENABLE;
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bios_cntl &= ~SPI_BIOS_CONTROL_CACHE_DISABLE;
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pci_write_config8(dev, SPIBAR_BIOS_CONTROL, bios_cntl);
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pci_write_config8(dev, SPI_BIOS_CONTROL, bios_cntl);
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}
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/*
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@ -63,9 +63,9 @@ static void fast_spi_set_bios_control_reg(uint32_t bios_cntl_bit)
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uint32_t bc_cntl;
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assert((bios_cntl_bit & (bios_cntl_bit - 1)) == 0);
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bc_cntl = pci_read_config32(dev, SPIBAR_BIOS_CONTROL);
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bc_cntl = pci_read_config32(dev, SPI_BIOS_CONTROL);
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bc_cntl |= bios_cntl_bit;
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pci_write_config32(dev, SPIBAR_BIOS_CONTROL, bc_cntl);
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pci_write_config32(dev, SPI_BIOS_CONTROL, bc_cntl);
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}
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/*
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@ -81,9 +81,9 @@ static void fast_spi_read_post_write(uint8_t reg)
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*/
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void fast_spi_set_bios_interface_lock_down(void)
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{
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fast_spi_set_bios_control_reg(SPIBAR_BIOS_CONTROL_BILD);
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fast_spi_set_bios_control_reg(SPI_BIOS_CONTROL_BILD);
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fast_spi_read_post_write(SPIBAR_BIOS_CONTROL);
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fast_spi_read_post_write(SPI_BIOS_CONTROL);
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}
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/*
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@ -91,9 +91,9 @@ void fast_spi_set_bios_interface_lock_down(void)
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*/
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void fast_spi_set_lock_enable(void)
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{
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fast_spi_set_bios_control_reg(SPIBAR_BIOS_CONTROL_LOCK_ENABLE);
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fast_spi_set_bios_control_reg(SPI_BIOS_CONTROL_LOCK_ENABLE);
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fast_spi_read_post_write(SPIBAR_BIOS_CONTROL);
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fast_spi_read_post_write(SPI_BIOS_CONTROL);
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}
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/*
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@ -104,9 +104,9 @@ void fast_spi_set_ext_bios_lock_enable(void)
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if (!CONFIG(FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW))
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return;
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fast_spi_set_bios_control_reg(SPIBAR_BIOS_CONTROL_EXT_BIOS_LOCK_ENABLE);
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fast_spi_set_bios_control_reg(SPI_BIOS_CONTROL_EXT_BIOS_LOCK_ENABLE);
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fast_spi_read_post_write(SPIBAR_BIOS_CONTROL);
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fast_spi_read_post_write(SPI_BIOS_CONTROL);
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}
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/*
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@ -114,9 +114,9 @@ void fast_spi_set_ext_bios_lock_enable(void)
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*/
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void fast_spi_set_eiss(void)
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{
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fast_spi_set_bios_control_reg(SPIBAR_BIOS_CONTROL_EISS);
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fast_spi_set_bios_control_reg(SPI_BIOS_CONTROL_EISS);
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fast_spi_read_post_write(SPIBAR_BIOS_CONTROL);
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fast_spi_read_post_write(SPI_BIOS_CONTROL);
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}
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/*
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@ -348,10 +348,10 @@ static void fast_spi_enable_ext_bios(void)
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(bios_region_top - 16MiB - MIN(extended_window_size, bios_size - 16MiB))
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to (bios_region_top - 16MiB).
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*/
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pci_or_config32(dev, SPIBAR_BIOS_CONTROL, SPIBAR_BIOS_CONTROL_EXT_BIOS_LIMIT(16 * MiB));
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pci_or_config32(dev, SPI_BIOS_CONTROL, SPI_BIOS_CONTROL_EXT_BIOS_LIMIT(16 * MiB));
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/* Program EXT_BIOS EN */
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pci_or_config32(dev, SPIBAR_BIOS_CONTROL, SPIBAR_BIOS_CONTROL_EXT_BIOS_ENABLE);
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pci_or_config32(dev, SPI_BIOS_CONTROL, SPI_BIOS_CONTROL_EXT_BIOS_ENABLE);
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}
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/*
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@ -390,8 +390,8 @@ void fast_spi_early_init(uintptr_t spi_base_address)
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/* Read SPI Write Protect disable status. */
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bool fast_spi_wpd_status(void)
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{
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return pci_read_config16(PCH_DEV_SPI, SPIBAR_BIOS_CONTROL) &
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SPIBAR_BIOS_CONTROL_WPD;
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return pci_read_config16(PCH_DEV_SPI, SPI_BIOS_CONTROL) &
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SPI_BIOS_CONTROL_WPD;
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}
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/* Enable SPI Write Protect. */
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@ -400,7 +400,7 @@ void fast_spi_enable_wp(void)
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const pci_devfn_t dev = PCH_DEV_SPI;
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uint8_t bios_cntl;
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bios_cntl = pci_read_config8(dev, SPIBAR_BIOS_CONTROL);
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bios_cntl &= ~SPIBAR_BIOS_CONTROL_WPD;
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pci_write_config8(dev, SPIBAR_BIOS_CONTROL, bios_cntl);
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bios_cntl = pci_read_config8(dev, SPI_BIOS_CONTROL);
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bios_cntl &= ~SPI_BIOS_CONTROL_WPD;
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pci_write_config8(dev, SPI_BIOS_CONTROL, bios_cntl);
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}
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@ -5,22 +5,21 @@
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/* PCI configuration registers */
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#define SPIDVID_OFFSET 0x0
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#define SPIBAR_BIOS_CONTROL 0xdc
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#define SPI_BIOS_CONTROL 0xdc
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/* Extended Bios Support Registers */
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#define SPI_CFG_BAR1 0xe0 /* SPI BAR1 MMIO */
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/* Bit definitions for BIOS_CONTROL */
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#define SPIBAR_BIOS_CONTROL_WPD (1 << 0)
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#define SPIBAR_BIOS_CONTROL_LOCK_ENABLE (1 << 1)
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#define SPIBAR_BIOS_CONTROL_EXT_BIOS_LOCK_ENABLE (1 << 28)
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#define SPIBAR_BIOS_CONTROL_CACHE_DISABLE (1 << 2)
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#define SPIBAR_BIOS_CONTROL_PREFETCH_ENABLE (1 << 3)
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#define SPIBAR_BIOS_CONTROL_EISS (1 << 5)
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#define SPIBAR_BIOS_CONTROL_BILD (1 << 7)
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#define SPIBAR_BIOS_CONTROL_EXT_BIOS_ENABLE (1 << 27)
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#define SPIBAR_BIOS_CONTROL_EXT_BIOS_LIMIT(x) ((x) & ~(0xfff))
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#define SPI_BIOS_CONTROL_WPD (1 << 0)
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#define SPI_BIOS_CONTROL_LOCK_ENABLE (1 << 1)
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#define SPI_BIOS_CONTROL_CACHE_DISABLE (1 << 2)
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#define SPI_BIOS_CONTROL_PREFETCH_ENABLE (1 << 3)
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#define SPI_BIOS_CONTROL_EISS (1 << 5)
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#define SPI_BIOS_CONTROL_BILD (1 << 7)
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#define SPI_BIOS_CONTROL_EXT_BIOS_ENABLE (1 << 27)
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#define SPI_BIOS_CONTROL_EXT_BIOS_LOCK_ENABLE (1 << 28)
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#define SPI_BIOS_CONTROL_EXT_BIOS_LIMIT(x) ((x) & ~(0xfff))
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/* Register offsets from the MMIO region base (PCI_BASE_ADDRESS_0) */
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@ -30,19 +29,19 @@
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#define SPIBAR_DLOCK 0x0c
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#define SPIBAR_FDATA(n) (0x10 + ((n) & 0xf) * 4)
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#define SPIBAR_FPR_BASE 0x84
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#define SPIBAR_FPR(n) 0x84 + (4 * n))
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#define SPIBAR_PREOP 0xA4
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#define SPIBAR_OPTYPE 0xA6
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#define SPIBAR_OPMENU_LOWER 0xA8
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#define SPIBAR_OPMENU_UPPER 0xAc
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#define SPIBAR_FDOC 0xB4
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#define SPIBAR_FDOD 0xB8
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#define SPIBAR_FPR(n) (0x84 + (4 * (n)))
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#define SPIBAR_PREOP 0xa4
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#define SPIBAR_OPTYPE 0xa6
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#define SPIBAR_OPMENU_LOWER 0xa8
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#define SPIBAR_OPMENU_UPPER 0xac
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#define SPIBAR_FDOC 0xb4
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#define SPIBAR_FDOD 0xb8
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#define SPIBAR_PTINX 0xcc
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#define SPIBAR_PTDATA 0xd0
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/* Bit definitions for BFPREG (0x00) register */
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#define SPIBAR_BFPREG_PRB_MASK (0x7fff)
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#define SPIBAR_BFPREG_PRL_SHIFT (16)
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#define SPIBAR_BFPREG_PRB_MASK 0x7fff
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#define SPIBAR_BFPREG_PRL_SHIFT 16
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#define SPIBAR_BFPREG_PRL_MASK (0x7fff << SPIBAR_BFPREG_PRL_SHIFT)
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#define SPIBAR_BFPREG_SBRS (1 << 31)
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@ -51,8 +50,8 @@
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#define SPIBAR_HSFSTS_FDBC(n) (((n) << 24) & SPIBAR_HSFSTS_FDBC_MASK)
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#define SPIBAR_HSFSTS_WET (1 << 21)
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#define SPIBAR_HSFSTS_FCYCLE_MASK (0xf << 17)
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#define SPIBAR_HSFSTS_FCYCLE(cyc) (((cyc) << 17) \
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& SPIBAR_HSFSTS_FCYCLE_MASK)
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#define SPIBAR_HSFSTS_FCYCLE(cyc) (((cyc) << 17) & SPIBAR_HSFSTS_FCYCLE_MASK)
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/* Supported flash cycle types */
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#define SPIBAR_HSFSTS_CYCLE_READ SPIBAR_HSFSTS_FCYCLE(0)
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#define SPIBAR_HSFSTS_CYCLE_WRITE SPIBAR_HSFSTS_FCYCLE(2)
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@ -74,12 +73,12 @@
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#define SPIBAR_HSFSTS_AEL (1 << 2)
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#define SPIBAR_HSFSTS_FCERR (1 << 1)
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#define SPIBAR_HSFSTS_FDONE (1 << 0)
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#define SPIBAR_HSFSTS_W1C_BITS (0xff)
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#define SPIBAR_HSFSTS_W1C_BITS 0xff
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/* Bit definitions for FADDR (0x08) register */
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#define SPIBAR_FADDR_MASK 0x7FFFFFF
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#define SPIBAR_FADDR_MASK 0x7ffffff
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/* Bit definitions for DLOCK (0x0C) register */
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/* Bit definitions for DLOCK (0x0c) register */
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#define SPIBAR_DLOCK_PR0LOCKDN (1 << 8)
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#define SPIBAR_DLOCK_PR1LOCKDN (1 << 9)
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#define SPIBAR_DLOCK_PR2LOCKDN (1 << 10)
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@ -89,12 +88,12 @@
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/* Maximum bytes of data that can fit in FDATAn (0x10) registers */
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#define SPIBAR_FDATA_FIFO_SIZE 0x40
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/* Bit definitions for FDOC (0xB4) register */
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/* Bit definitions for FDOC (0xb4) register */
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#define SPIBAR_FDOC_COMPONENT (1 << 12)
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#define SPIBAR_FDOC_FDSI_1 (1 << 2)
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/* Flash Descriptor Component Section - Component 0 Density Bit Settings */
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#define FLCOMP_C0DEN_MASK 0xF
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#define FLCOMP_C0DEN_MASK 0xf
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#define FLCOMP_C0DEN_8MB 4
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#define FLCOMP_C0DEN_16MB 5
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#define FLCOMP_C0DEN_32MB 6
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@ -103,7 +102,7 @@
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#define SPIBAR_FPR_WPE (1 << 31) /* Flash Write protected */
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#define SPIBAR_FPR_MAX 5
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/* Programmable values for OPMENU_LOWER(0xA8) & OPMENU_UPPER(0xAC) register */
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/* Programmable values for OPMENU_LOWER(0xa8) & OPMENU_UPPER(0xac) register */
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#define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */
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#define SPI_OPTYPE_0 0x01 /* Write, no address */
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#define SPI_OPMENU_1 0x02 /* BYPR: Byte Program */
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@ -130,7 +129,7 @@
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(SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0))
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#define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */
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/* Bit definitions for PTINX (0xCC) register */
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/* Bit definitions for PTINX (0xcc) register */
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#define SPIBAR_PTINX_COMP_0 (0 << 14)
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#define SPIBAR_PTINX_COMP_1 (1 << 14)
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#define SPIBAR_PTINX_HORD_SFDP (0 << 12)
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@ -139,9 +138,9 @@
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#define SPIBAR_PTINX_IDX_MASK 0xffc
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/* Register Offsets of BIOS Flash Program Registers */
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#define SPIBAR_RESET_LOCK 0xF0
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#define SPIBAR_RESET_CTRL 0xF4
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#define SPIBAR_RESET_DATA 0xF8
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#define SPIBAR_RESET_LOCK 0xf0
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#define SPIBAR_RESET_CTRL 0xf4
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#define SPIBAR_RESET_DATA 0xf8
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/* Programmable values of Bit0 (SSL) of Set STRAP MSG LOCK (0xF0) Register */
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#define SPIBAR_RESET_LOCK_DISABLE 0 /* Set_Strap Lock(SSL) Bit 0 = 0 */
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@ -150,7 +149,7 @@
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/* Programmable values of Bit0(SSMS) of Set STRAP MSG Control (0xF4) Register*/
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#define SPIBAR_RESET_CTRL_SSMC 1 /* Set_Strap Mux Select(SSMS) Bit=1*/
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#define SPIBAR_HWSEQ_XFER_TIMEOUT 5000 /* max 5s*/
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#define SPIBAR_HWSEQ_XFER_TIMEOUT_MS 5000
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void *fast_spi_get_bar(void);
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@ -110,7 +110,7 @@ static int wait_for_hwseq_xfer(struct fast_spi_flash_ctx *ctx,
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struct stopwatch sw;
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uint32_t hsfsts;
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stopwatch_init_msecs_expire(&sw, SPIBAR_HWSEQ_XFER_TIMEOUT);
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stopwatch_init_msecs_expire(&sw, SPIBAR_HWSEQ_XFER_TIMEOUT_MS);
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do {
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hsfsts = fast_spi_flash_ctrlr_reg_read(ctx, SPIBAR_HSFSTS_CTL);
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@ -125,7 +125,7 @@ static int wait_for_hwseq_xfer(struct fast_spi_flash_ctx *ctx,
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} while (!(stopwatch_expired(&sw)));
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printk(BIOS_ERR, "SPI Transaction Timeout (Exceeded %d ms) at Flash Offset %x HSFSTS = 0x%08x\n",
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SPIBAR_HWSEQ_XFER_TIMEOUT, flash_addr, hsfsts);
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SPIBAR_HWSEQ_XFER_TIMEOUT_MS, flash_addr, hsfsts);
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return E_TIMEOUT;
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}
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