mb/google/myst: Enable AP <-> GSC communication

Configure GSC I2C and Interrupt GPIOs during the early initialization.
Add devicetree configuration for GSC device and enable the required
config items.

BUG=b:275959717
TEST=builds

Change-Id: I6e235356b252a7b68a42da128ffd3189a829f117
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74111
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/google/myst/Kconfig

@@ -18,13 +18,24 @@ config BOARD_SPECIFIC_OPTIONS
 	select ELOG_GSMI
 	select FW_CONFIG
 	select FW_CONFIG_SOURCE_CHROMEEC_CBI
+	select I2C_TPM
 	select MAINBOARD_HAS_CHROMEOS
+	select MAINBOARD_HAS_TPM2
 	select SOC_AMD_COMMON_BLOCK_USE_ESPI
 	select SOC_AMD_PHOENIX
+	select TPM_GOOGLE_TI50
 
 config DEVICETREE
 	default "variants/baseboard/devicetree.cb"
 
+config DRIVER_TPM_I2C_BUS
+	hex
+	default 0x02
+
+config DRIVER_TPM_I2C_ADDR
+	hex
+	default 0x50
+
 config FMDFILE
 	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos.fmd"
 
@@ -52,4 +63,9 @@ config VBOOT
 	select VBOOT_SEPARATE_VERSTAGE
 	select VBOOT_STARTS_IN_BOOTBLOCK
 
+# TODO(b/277087492): Enable GSC CBFS verification
+config VBOOT_GSCVD
+	bool
+	default n
+
 endif # BOARD_GOOGLE_BASEBOARD_MYST

src/mainboard/google/myst/bootblock.c

@@ -18,7 +18,11 @@ void mb_set_up_early_espi(void)
 
 void bootblock_mainboard_early_init(void)
 {
-	/* TODO(b/275959717): Perform mainboard initialization */
+	size_t num_gpios;
+	const struct soc_amd_gpio *gpios;
+
+	variant_tpm_gpio_table(&gpios, &num_gpios);
+	gpio_configure_pads(gpios, num_gpios);
 }
 
 void bootblock_mainboard_init(void)

src/mainboard/google/myst/mainboard.c

@@ -5,6 +5,7 @@
 #include <baseboard/variants.h>
 #include <console/console.h>
 #include <device/device.h>
+#include <drivers/i2c/tpm/chip.h>
 #include <soc/acpi.h>
 #include <variant/ec.h>
 

src/mainboard/google/myst/variants/baseboard/devicetree.cb

@@ -186,6 +186,13 @@ chip soc/amd/phoenix
 	device ref uart_0 on end # UART0
 	device ref i2c_0 on end
 	device ref i2c_1 on end
-	device ref i2c_2 on end
+	device ref i2c_2 on
+		chip drivers/i2c/tpm
+			register "hid" = ""GOOG0005""
+			register "desc" = ""Ti50 TPM""
+			register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_84)"
+			device i2c 50 alias ti50 on end
+		end
+	end
 	device ref i2c_3 on end
 end	# chip soc/amd/phoenix

src/mainboard/google/myst/variants/baseboard/gpio.c

@@ -168,6 +168,15 @@ static const struct soc_amd_gpio base_gpio_table[] = {
 	PAD_GPO(GPIO_157, HIGH),
 };
 
+static const struct soc_amd_gpio tpm_gpio_table[] = {
+	/* I2C2_SCL */
+	PAD_NF(GPIO_113, I2C2_SCL, PULL_NONE),
+	/* I2C2_SDA */
+	PAD_NF(GPIO_114, I2C2_SDA, PULL_NONE),
+	/* GSC_SOC_INT_L */
+	PAD_INT(GPIO_84, PULL_NONE, EDGE_LOW, STATUS_DELIVERY),
+};
+
 /* GPIO configuration in bootblock */
 static const struct soc_amd_gpio bootblock_gpio_table[] = {
 	/* TODO(b/275965982): Fill bootblock gpio configuration */
@@ -208,6 +217,12 @@ void variant_espi_gpio_table(const struct soc_amd_gpio **gpio, size_t *size)
 	*gpio = espi_gpio_table;
 }
 
+__weak void variant_tpm_gpio_table(const struct soc_amd_gpio **gpio, size_t *size)
+{
+	*size = ARRAY_SIZE(tpm_gpio_table);
+	*gpio = tpm_gpio_table;
+}
+
 __weak void variant_override_gpio_table(const struct soc_amd_gpio **gpio, size_t *size)
 {
 	*size = 0;

src/mainboard/google/myst/variants/baseboard/include/baseboard/variants.h

@@ -21,4 +21,7 @@ void variant_espi_gpio_table(const struct soc_amd_gpio **gpio, size_t *size);
  */
 void variant_override_gpio_table(const struct soc_amd_gpio **gpio, size_t *size);
 
+/* This function provides GPIO settings for TPM i2c bus. */
+void variant_tpm_gpio_table(const struct soc_amd_gpio **gpio, size_t *size);
+
 #endif /* __BASEBOARD_VARIANTS_H__ */