diff --git a/3rdparty/vboot b/3rdparty/vboot index 304aa429c1..e7edff6653 160000 --- a/3rdparty/vboot +++ b/3rdparty/vboot @@ -1 +1 @@ -Subproject commit 304aa429c1a04cda3ab2ce37b9e31af84405bfca +Subproject commit e7edff6653e16ed915c3ad12234d133d1ef4dcc9 diff --git a/Documentation/Intel/index.html b/Documentation/Intel/index.html index b4daa960a9..9d8aad05e9 100644 --- a/Documentation/Intel/index.html +++ b/Documentation/Intel/index.html @@ -29,7 +29,6 @@
  • SoC support
  • Board support
    • -
  • Verified Boot (vboot) support
    • diff --git a/Documentation/Intel/vboot.html b/Documentation/Intel/vboot.html deleted file mode 100644 index ca49ac2e2d..0000000000 --- a/Documentation/Intel/vboot.html +++ /dev/null @@ -1,402 +0,0 @@ - - - - vboot - Verified Boot Support - - - -

    vboot - Verified Boot Support

    - -

    -Google's verified boot support consists of: -

    - - -Google's vboot verifies the firmware and places measurements -within the TPM. - -
    -

    Root of Trust

    -

    -When using vboot, the root-of-trust is basically the read-only portion of the -SPI flash. The following items factor into the trust equation: -

    - - -

    -The firmware is typically protected using the write-protect pin on the SPI -flash part and setting some of the write-protect bits in the status register -during manufacturing. The protected area is platform specific and for x86 -platforms is typically 1/4th of the SPI flash -part size. Because this portion of the SPI flash is hardware write protected, -it is not possible to update this portion of the SPI flash in the field, -without altering the system to eliminate the ground connection to the SPI flash -write-protect pin. Without hardware modifications, this portion of the SPI -flash maintains the manufactured state during the system's lifetime. -

    - -
    -

    Firmware Layout

    -

    -Several sections are added to the firmware layout to support vboot: -

    - -

    -The following sections describe the various portions of the flash layout. -

    - -

    Read-Only Section

    -

    -The read-only section contains a coreboot file system (CBFS) that contains all -of the boot firmware necessary to perform recovery for the system. This -firmware is typically protected using the write-protect pin on the SPI flash -part and setting some of the write-protect bits in the status register during -manufacturing. The protected area is typically 1/4th of the SPI flash part -size and must cover the entire read-only section which consists of: -

    - - -

    Google Binary Blob (GBB) Area

    -

    -The GBB area is part of the read-only section. This area contains a 4096 or -8192 bit public root RSA key that is used to verify the VBLOCK area to obtain -the firmware signing key. -

    - -

    Recovery Firmware

    -

    -The recovery firmware is contained within a coreboot file system and consists -of: -

    - - -

    -The recovery firmware is written during manufacturing and typically contains -code to write the storage device (eMMC device or hard disk). The recovery -image is usually contained on a socketed device such as a USB flash drive or -an SD card. Depending upon the payload firmware doing the recovery, it may -be possible for the user to interact with the system to specify the recovery -image path. Part of the recovery is also to write the A and B areas of the -SPI flash device to boot the system. -

    - - -

    Read/Write Section

    - -

    -The read/write sections contain an area which contains the firmware signing -key and signature and an area containing a coreboot file system with a subset -of the firmware. The firmware files in FW_MAIN_A and FW_MAIN_B are: -

    - - -

    -The firmware subset enables most issues to be fixed in the field with firmware -updates. The firmware files handle memory and most of silicon initialization. -These files also produce the tables which get passed to the operating system. -

    - -
    -

    Firmware Updates

    -

    -The read/write sections exist in one of three states: -

    - - - - - - -
    -Where is this state information written? -
    CMOS? -
    RW_NVRAM? -
    RW_FWID_* -
    - -

    -Firmware updates are handled by the operating system by writing any read/write -section that is not in the "successfully booted" state. Upon the next reboot, -vboot determines the section to boot. If it finds one in the "ready to boot" -state then it attempts to boot using that section. If the boot fails then -vboot marks the section as invalid and attempts to fall back to a read/write -section in the "successfully booted" state. If vboot is not able to find a -section in the "successfully booted" state then vboot enters recovery mode. -

    - -

    -Only the operating system is able to transition a section from the "ready to -boot" state to the "successfully booted" state. The transition is typically -done after the operating system has been running for a while indicating -that successful boot was possible and the operating system is stable. -

    - -

    -Note that as long as the SPI write protection is in place then the system is -always recoverable. If the flash update fails then the system will continue -to boot using the previous read/write area. The same is true if coreboot -passes control to the payload or the operating system and then the boot fails. -In the worst case, the SPI flash gets totally corrupted in which case vboot -fails the signature checks and enters recovery mode. There are no times where -the SPI flash is exposed and the reset vector or part of the recovery firmware -gets corrupted. -

    - -
    -

    Build Flags

    -

    -The following Kconfig values need to be selected to enable vboot: -

    - - -

    -The starting stage needs to be specified by selecting either -VBOOT_STARTS_IN_BOOTBLOCK or VBOOT_STARTS_IN_ROMSTAGE. -

    - -

    -If vboot starts in bootblock then vboot may be built as a separate stage by -selecting VBOOT_SEPARATE_VERSTAGE. Additionally, if static RAM is too small -to fit both verstage and romstage then selecting VBOOT_RETURN_FROM_VERSTAGE -enables bootblock to reuse the RAM occupied by verstage for romstage. -

    - -

    -Non-volatile flash is needed for vboot operation. This flash area may be in -CMOS, the EC, or in a read/write area of the SPI flash device. Select one of -the following: -

    - -

    -More non-volatile storage features may be found in src/vboot/Kconfig. -

    - -

    -A TPM is also required for vboot operation. TPMs are available in -drivers/i2c/tpm and drivers/pc80/tpm. -

    - -

    -In addition to adding the coreboot files into the read-only region, enabling -vboot causes the build script to add the read/write files into coreboot file -systems in FW_MAIN_A and FW_MAIN_B. -

    - -
    -

    Signing the coreboot Image

    -

    -The following command script is an example of how to sign the coreboot image file. -This script is used on the Intel Galileo board and creates the GBB area and -inserts it into the coreboot image. It also updates the VBLOCK areas with the -firmware signing key and the signature for the FW_MAIN firmware. More details -are available in 3rdparty/vboot/README. -

    - -
    #!/bin/sh
-#
-#  The necessary tools were built and installed using the following commands:
-#
-#        pushd 3rdparty/vboot
-#        make
-#        sudo make install
-#        popd
-#
-#  The keys were made using the following command
-#
-#        3rdparty/vboot/scripts/keygeneration/create_new_keys.sh  \
-#                --4k --4k-root --output $PWD/keys
-#
-#
-#  The "magic" numbers below are derived from the GBB section in
-#  src/mainboard/intel/galileo/vboot.fmd.
-#
-#  GBB Header Size:     0x80
-#  GBB Offset:      0x611000, 4KiB block number: 1553 (0x611)
-#  GBB Length:       0x7f000, 4KiB blocks:        127  (0x7f)
-#  COREBOOT Offset: 0x690000, 4KiB block number: 1680 (0x690)
-#  COREBOOT Length: 0x170000, 4KiB blocks:        368 (0x170)
-#
-#  0x7f000 (GBB Length) = 0x80 + 0x100 + 0x1000 + 0x7ce80 + 0x1000
-#
-#  Create the GBB area blob
-#  Parameters: hwid_size,rootkey_size,bmpfv_size,recoverykey_size
-#
-gbb_utility -c 0x100,0x1000,0x7ce80,0x1000 gbb.blob
-
-#
-#  Copy from the start of the flash to the GBB region into the signed flash
-#  image.
-#
-#  1553 * 4096 = 0x611 * 0x1000 = 0x611000, size of area before GBB
-#
-dd  conv=fdatasync  ibs=4096  obs=4096  count=1553  \
-    if=build/coreboot.rom  of=build/coreboot.signed.rom
-
-#
-#  Append the empty GBB area to the coreboot.rom image.
-#
-#  1553 * 4096 = 0x611 * 0x1000 = 0x611000, offset to GBB
-#
-dd  conv=fdatasync  obs=4096  obs=4096  seek=1553  if=gbb.blob  \
-    of=build/coreboot.signed.rom
-
-#
-#  Append the rest of the read-only region into the signed flash image.
-#
-#  1680 * 4096 = 0x690 * 0x1000 = 0x690000, offset to COREBOOT area
-#   368 * 4096 = 0x170 * 0x1000 = 0x170000, length of COREBOOT area
-#
-dd  conv=fdatasync  ibs=4096  obs=4096  skip=1680  seek=1680  count=368  \
-    if=build/coreboot.rom  of=build/coreboot.signed.rom
-
-#
-#  Insert the HWID and public root and recovery RSA keys into the GBB area.
-#
-gbb_utility                          \
-   --set --hwid='Galileo'            \
-   -r $PWD/keys/recovery_key.vbpubk  \
-   -k $PWD/keys/root_key.vbpubk      \
-   build/coreboot.signed.rom
-
-#
-#  Sign the read/write firmware areas with the private signing key and update
-#  the VBLOCK_A and VBLOCK_B regions.
-#
-3rdparty/vboot/scripts/image_signing/sign_firmware.sh  \
-   build/coreboot.signed.rom                           \
-   $PWD/keys                                           \
-   build/coreboot.signed.rom
-
    - -
    -

    Boot Flow

    -

    -The reset vector exist in the read-only area and points to the bootblock entry -point. The only copy of the bootblock exists in the read-only area of the SPI -flash. Verstage may be part of the bootblock or a separate stage. If separate -then the bootblock loads verstage from the read-only area and transfers control -to it. -

    - -

    -Upon first boot, verstage attempts to verify the read/write section A. It gets -the public root key from the GBB area and uses that to verify the VBLOCK area -in read-write section A. If the VBLOCK area is valid then it extracts the -firmware signing key (1024-8192 bits) and uses that to verify the FW_MAIN_A -area of read/write section A. If the verification is successful then verstage -instructs coreboot to use the coreboot file system in read/write section A for -the contents of the remaining boot firmware (romstage, postcar, ramstage and -the payload). -

    - -

    -If verification fails for the read/write area and the other read/write area is -not valid vboot falls back to the read-only area to boot into system recovery. -

    - -
    -

    Chromebook Special Features

    -

    -Google's Chromebooks have some special features: -

    - - -

    Developer Mode

    -

    -Developer mode allows the user to use coreboot to boot another operating system. -This may be a another (beta) version of Chrome OS, or another flavor of -GNU/Linux. Use of developer mode does not void the system warranty. Upon -entry into developer mode, all locally saved data on the system is lost. -This prevents someone from entering developer mode to subvert the system -security to access files on the local system or cloud. -

    - -

    Write Protect Screw

    -

    -Chromebooks have a write-protect screw which provides the ground to the -write-protect pin of the SPI flash. Google specifically did this to allow -the manufacturing line and advanced developers to re-write the entire SPI flash -part. Once the screw is removed, any firmware may be placed on the device. -However, accessing this screw requires opening the case and voids the system -warranty! -

    - -
    -

    Modified: 2 May 2017

    - - diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 7eaf425e20..9af5c80883 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -70,6 +70,10 @@ The boards in this section are not real mainboards, but emulators. - [T430 / T530 / X230 / W530 common](lenovo/xx30_series.md) - [T431s](lenovo/t431s.md) +## MSI + +- [MS-7707](msi/ms7707/ms7707.md) + ## SiFive - [SiFive HiFive Unleashed](sifive/hifive-unleashed.md) diff --git a/Documentation/mainboard/msi/ms7707/J1-flash-protect.jpg b/Documentation/mainboard/msi/ms7707/J1-flash-protect.jpg new file mode 100644 index 0000000000..b649d059a8 Binary files /dev/null and b/Documentation/mainboard/msi/ms7707/J1-flash-protect.jpg differ diff --git a/Documentation/mainboard/msi/ms7707/JSPI1-Winbond-W25Q32BVSIG.jpg b/Documentation/mainboard/msi/ms7707/JSPI1-Winbond-W25Q32BVSIG.jpg new file mode 100644 index 0000000000..7a0df71dd7 Binary files /dev/null and b/Documentation/mainboard/msi/ms7707/JSPI1-Winbond-W25Q32BVSIG.jpg differ diff --git a/Documentation/mainboard/msi/ms7707/JSPI1-connected.jpg b/Documentation/mainboard/msi/ms7707/JSPI1-connected.jpg new file mode 100644 index 0000000000..d1eed2760e Binary files /dev/null and b/Documentation/mainboard/msi/ms7707/JSPI1-connected.jpg differ diff --git a/Documentation/mainboard/msi/ms7707/JSPI1.png b/Documentation/mainboard/msi/ms7707/JSPI1.png new file mode 100644 index 0000000000..b1eadc28e6 Binary files /dev/null and b/Documentation/mainboard/msi/ms7707/JSPI1.png differ diff --git a/Documentation/mainboard/msi/ms7707/flashlayout.svg b/Documentation/mainboard/msi/ms7707/flashlayout.svg new file mode 100644 index 0000000000..2bd826b10c --- /dev/null +++ b/Documentation/mainboard/msi/ms7707/flashlayout.svg @@ -0,0 +1,34 @@ + + + + + + image/svg+xml + + + + + + + + IFD + + BIOS + + + + ME + + + GBE + + 0x000000 + 0x001000 + 0x003000 + 0x200000 + 0x400000 + + + + Flash + diff --git a/Documentation/mainboard/msi/ms7707/ms7707.md b/Documentation/mainboard/msi/ms7707/ms7707.md new file mode 100644 index 0000000000..789431872c --- /dev/null +++ b/Documentation/mainboard/msi/ms7707/ms7707.md @@ -0,0 +1,112 @@ +# MSI MS-7707 V1.1 + +* MSI MS-7707 V1.1 (Medion OEM Akoya P4385D MSN10014555) +* SandyBridge Intel P67 (BD82x6x) +* Winbond 25Q32BV (4MB) +* Fintek F71808A SuperIO +* Intel 82579V Gigabit +* NEC uPD720200 USB 3.0 Host Controller +* IME 7.0.4.1197 + +## Flash chip (Winbond 25Q32BV) +```eval_rst ++---------------------+--------------------+ +| Type | Value | ++=====================+====================+ +| Size | 4 MiB | ++---------------------+--------------------+ +| BIOS range | 2 MiB | ++---------------------+--------------------+ +| Write protection | Yes (via jumper) | ++---------------------+--------------------+ +| Header | Yes (JSPI1) | ++---------------------+--------------------+ +| Package | SOIC-8 | ++---------------------+--------------------+ +| In circuit flashing | Yes | ++---------------------+--------------------+ +| Internal flashing | Yes | ++---------------------+--------------------+ +| Socketed flash | No | ++---------------------+--------------------+ +| Dual BIOS feature | No | ++---------------------+--------------------+ +| ME removable | Yes | ++---------------------+--------------------+ +``` + +## Installation instructions +* The standard method is to only flash the 2MiB BIOS region. In that case it's +not needed to extract blobs from vendor firmware and internal flashing is +sufficient. +* To flash the whole chip (e.g. to disable ME) blobs are needed to build +coreboot. Blobs can be extracted with util/ifdtool from 4MiB full dump image +(see below). Its recommended to include the VGA BIOS as well (4MiB write only). +Kconfig is prepared already if it gets enabled (path and 8086,0102). +``` +coreboot/3rdparty/blobs/mainboard/msi/ms7707 +├── descriptor.bin +├── gbe.bin +├── me.bin +└── vgabios.bin +``` +* Never write a full 4MiB image if blobs are not included. The generated +coreboot.rom file is always 4MiB but the 2MiB flash command below will only +flash the last 2MiB (BIOS) block. +* The J1-Jumper sets the 'Flash Descriptor Override Strap-Pin' and enables +full 4MiB access for internal flasher (read and write). +* **Write BIOS-range** (2MiB) with J1-Jumper=off (as on picture/default + position): +``` +flashrom -p internal:ich_spi_force=yes --noverify-all --ifd -i bios -w coreboot.rom +``` +* **Read full dump** (4MiB) with J1-jumper=on: +``` +flashrom -p internal -r original.rom +``` +* **Write full dump** (4MiB) with J1-Jumper=on: +``` +flashrom -p internal -w coreboot.rom +``` +* After successful flashing turn main power off, wait some seconds to drain +the capacitors, pull the battery and set the JBAT (clrcmos) jumper for some +seconds. Setting the jumper alone is not enough (the Fintek is VBAT backed). +Put all back in place and restart the board. It might need 1-2 AC power cycles +to reinitialize (running at full fan speed - don't panic). +* External flashing has been tested with RPi2 without main power connected. +3.3V provided by RPi2. Read more about flashing methods [here](https://doc.coreboot.org/flash_tutorial/index.html). +* In case of going back to proprietary BIOS create/save cmos settings as early +as possible (do not leave BIOS on first start without saving settings). +The BIOS might corrupt nvram (not cmos!) and leave the system in a dead state +that needs an external flasher to revive. If stuck, reset the Fintek (see +above) and restart the system several times and/or try setting J1 to +temporarily disable ME. + +![](J1-flash-protect.jpg) + +* The JSPI1 header (5×2 2.0mm pitch pin header) for external flashing is +directly connected to the flash chip. Additional 3.3V to /HOLD and /WP is not +needed (internally re-routed already). + +![](JSPI1-Winbond-W25Q32BVSIG.jpg) + +![](JSPI1-connected.jpg) + +![](JSPI1.png) + +## Flash layout + +* The 4MiB flashrom is divided into 4 sections: + +![][flashlayout] + +## Links + +- [BIOS ROM] +- [Fintek F71808A datasheet] +- [Winbond 25Q32BV datasheet] + +[BIOS ROM]: https://www.medion.com/de/servicebackend/_lightbox/treiber_details.php?did=9744 +[Winbond 25Q32BV datasheet]: https://www.winbond.com/resource-files/w25q32bv_revi_100413_wo_automotive.pdf +[Fintek F71808A datasheet]: https://www.alldatasheet.com/datasheet-pdf/pdf/459069/FINTEK/F71808A.html +[flashlayout]: flashlayout.svg diff --git a/Documentation/security/index.md b/Documentation/security/index.md index 89db42ecee..9ad54866c2 100644 --- a/Documentation/security/index.md +++ b/Documentation/security/index.md @@ -4,4 +4,5 @@ This section describes documentation about the security architecture of coreboot ## Vendor +- [Verified Boot](vboot/index.md) - [Measured Boot](vboot/measured_boot.md) diff --git a/Documentation/security/vboot/index.md b/Documentation/security/vboot/index.md new file mode 100644 index 0000000000..97420893e5 --- /dev/null +++ b/Documentation/security/vboot/index.md @@ -0,0 +1,324 @@ +# vboot - Verified Boot Support + +Google's verified boot support consists of: + +* A root of trust +* Special firmware layout +* Firmware verification +* Firmware measurements +* A firmware update mechanism +* Specific build flags +* Signing the coreboot image + +Google's vboot verifies the firmware and places measurements within the TPM. + +*** + +## Root of Trust + +When using vboot, the root-of-trust is basically the read-only portion of the +SPI flash. The following items factor into the trust equation: + +* The GCC compiler must reliably translate the code into machine code + without inserting any additional code (virus, backdoor, etc.) +* The CPU must reliably execute the reset sequence and instructions as + documented by the CPU manufacturer. +* The SPI flash must provide only the code programmed into it to the CPU + without providing any alternative reset vector or code sequence. +* The SPI flash must honor the write-protect input and protect the specified + portion of the SPI flash from all erase and write accesses. + +The firmware is typically protected using the write-protect pin on the SPI +flash part and setting some of the write-protect bits in the status register +during manufacturing. The protected area is platform specific and for x86 +platforms is typically 1/4th of the SPI flash part size. +Because this portion of the SPI flash is hardware write protected, it is not +possible to update this portion of the SPI flash in the field, without altering +the system to eliminate the ground connection to the SPI flash write-protect pin. +Without hardware modifications, this portion of the SPI flash maintains the +manufactured state during the system's lifetime. + +*** + +## Firmware Layout + +Several sections are added to the firmware layout to support vboot: + +* Read-only section +* Google Binary Blob (GBB) area +* Read/write section A +* Read/write section B + +The following sections describe the various portions of the flash layout. + +### Read-Only Section + +The read-only section contains a coreboot file system (CBFS) that contains all +of the boot firmware necessary to perform recovery for the system. This firmware +is typically protected using the write-protect pin on the SPI flash part and +setting some of the write-protect bits in the status register during +manufacturing. +The protected area is typically 1/4th of the SPI flash part size and must cover +the entire read-only section which consists of: + +* Vital Product Data (VPD) area +* Firmware ID area +* Google Binary Blob (GBB) area +* coreboot file system containing read-only recovery firmware + +### Google Binary Blob (GBB) Area + +The GBB area is part of the read-only section. This area contains a 4096 or 8192 +bit public root RSA key that is used to verify the *VBLOCK* area to obtain the +firmware signing key. + +### Recovery Firmware + +The recovery firmware is contained within a coreboot file system and consists of: + +* reset vector +* bootblock +* verstage +* romstage +* postcar +* ramstage +* payload +* flash map file +* config file +* processor specific files: + * Microcode + * fspm.bin + * fsps.bin + +The recovery firmware is written during manufacturing and typically contains +code to write the storage device (eMMC device or hard disk). The recovery image +is usually contained on a socketed device such as a USB flash drive or an +SD card. Depending upon the payload firmware doing the recovery, it may be +possible for the user to interact with the system to specify the recovery +image path. Part of the recovery is also to write the A and B areas of the SPI +flash device to boot the system. + +### Read/Write Section + +The read/write sections contain an area which contains the firmware signing +key and signature and an area containing a coreboot file system with a subset +of the firmware. The firmware files in *FW_MAIN_A* and *FW_MAIN_B* are: + +* romstage +* postcar +* ramstage +* payload +* config file +* processor specific files: + * Microcode + * fspm.bin + * fsps.bin + +The firmware subset enables most issues to be fixed in the field with firmware +updates. The firmware files handle memory and most of silicon initialization. +These files also produce the tables which get passed to the operating system. + +*** + +## Firmware Updates + +The read/write sections exist in one of three states: + +* Invalid +* Ready to boot +* Successfully booted + + +Firmware updates are handled by the operating system by writing any read/write +section that is not in the "successfully booted" state. Upon the next reboot, +vboot determines the section to boot. If it finds one in the "ready to boot" +state then it attempts to boot using that section. If the boot fails then +vboot marks the section as invalid and attempts to fall back to a read/write +section in the "successfully booted" state. If vboot is not able to find a +section in the "successfully booted" state then vboot enters recovery mode. + +Only the operating system is able to transition a section from the +"ready to boot" state to the "successfully booted" state. +The transition is typically done after the operating system has been running +for a while indicating that successful boot was possible and the operating +system is stable. + +Note that as long as the SPI write protection is in place then the system +is always recoverable. If the flash update fails then the system will continue +to boot using the previous read/write area. The same is true if coreboot passes +control to the payload or the operating system and then the boot fails. In the +worst case, the SPI flash gets totally corrupted in which case vboot fails the +signature checks and enters recovery mode. There are no times where the SPI +flash is exposed and the reset vector or part of the recovery firmware gets +corrupted. + +*** + +## Build Flags + +The following *Kconfig* values need to be selected to enable vboot: + +* COLLECT_TIMESTAMPS +* VBOOT + +The starting stage needs to be specified by selecting either +VBOOT_STARTS_IN_BOOTBLOCK or VBOOT_STARTS_IN_ROMSTAGE. + +If vboot starts in bootblock then vboot may be built as a separate stage by +selecting `VBOOT_SEPARATE_VERSTAGE`. Additionally, if static RAM is too small +to fit both verstage and romstage then selecting `VBOOT_RETURN_FROM_VERSTAGE` +enables bootblock to reuse the RAM occupied by verstage for romstage. + +Non-volatile flash is needed for vboot operation. This flash area may be in +CMOS, the EC, or in a read/write area of the SPI flash device. +Select one of the following: + +* `VBOOT_VBNV_CMOS` +* `VBOOT_VBNV_EC` +* `VBOOT_VBNV_FLASH` + +More non-volatile storage features may be found in `security/vboot/Kconfig`. + +A TPM is also required for vboot operation. +TPMs are available in `drivers/i2c/tpm` and `drivers/pc80/tpm`. + +In addition to adding the coreboot files into the read-only region, +enabling vboot causes the build script to add the read/write files into +coreboot file systems in *FW_MAIN_A* and *FW_MAIN_B*. + +*** + +## Signing the coreboot Image + +The following command script is an example of how to sign the coreboot image +file. This script is used on the Intel Galileo board and creates the *GBB* area +and inserts it into the coreboot image. It also updates the *VBLOCK* areas with +the firmware signing key and the signature for the *FW_MAIN* firmware. +More details are available in `3rdparty/vboot/README`. + +```bash +#!/bin/sh +# +# The necessary tools were built and installed using the following commands: +# +# pushd 3rdparty/vboot +# make +# sudo make install +# popd +# +# The keys were made using the following command +# +# 3rdparty/vboot/scripts/keygeneration/create_new_keys.sh \ +# --4k --4k-root --output $PWD/keys +# +# +# The "magic" numbers below are derived from the GBB section in +# src/mainboard/intel/galileo/vboot.fmd. +# +# GBB Header Size: 0x80 +# GBB Offset: 0x611000, 4KiB block number: 1553 (0x611) +# GBB Length: 0x7f000, 4KiB blocks: 127 (0x7f) +# COREBOOT Offset: 0x690000, 4KiB block number: 1680 (0x690) +# COREBOOT Length: 0x170000, 4KiB blocks: 368 (0x170) +# +# 0x7f000 (GBB Length) = 0x80 + 0x100 + 0x1000 + 0x7ce80 + 0x1000 +# +# Create the GBB area blob +# Parameters: hwid_size,rootkey_size,bmpfv_size,recoverykey_size +# +gbb_utility -c 0x100,0x1000,0x7ce80,0x1000 gbb.blob + +# +# Copy from the start of the flash to the GBB region into the signed flash +# image. +# +# 1553 * 4096 = 0x611 * 0x1000 = 0x611000, size of area before GBB +# +dd conv=fdatasync ibs=4096 obs=4096 count=1553 \ +if=build/coreboot.rom of=build/coreboot.signed.rom + +# +# Append the empty GBB area to the coreboot.rom image. +# +# 1553 * 4096 = 0x611 * 0x1000 = 0x611000, offset to GBB +# +dd conv=fdatasync obs=4096 obs=4096 seek=1553 if=gbb.blob \ +of=build/coreboot.signed.rom + +# +# Append the rest of the read-only region into the signed flash image. +# +# 1680 * 4096 = 0x690 * 0x1000 = 0x690000, offset to COREBOOT area +# 368 * 4096 = 0x170 * 0x1000 = 0x170000, length of COREBOOT area +# +dd conv=fdatasync ibs=4096 obs=4096 skip=1680 seek=1680 count=368 \ +if=build/coreboot.rom of=build/coreboot.signed.rom + +# +# Insert the HWID and public root and recovery RSA keys into the GBB area. +# +gbb_utility \ +--set --hwid='Galileo' \ +-r $PWD/keys/recovery_key.vbpubk \ +-k $PWD/keys/root_key.vbpubk \ +build/coreboot.signed.rom + +# +# Sign the read/write firmware areas with the private signing key and update +# the VBLOCK_A and VBLOCK_B regions. +# +3rdparty/vboot/scripts/image_signing/sign_firmware.sh \ +build/coreboot.signed.rom \ +$PWD/keys \ + build/coreboot.signed.rom +``` + +*** + +## Boot Flow + +The reset vector exist in the read-only area and points to the bootblock +entry point. The only copy of the bootblock exists in the read-only area +of the SPI flash. Verstage may be part of the bootblock or a separate stage. +If separate then the bootblock loads verstage from the read-only area and +transfers control to it. + +Upon first boot, verstage attempts to verify the read/write section A. +It gets the public root key from the GBB area and uses that to verify the +*VBLOCK* area in read-write section A. If the *VBLOCK* area is valid then it +extracts the firmware signing key (1024-8192 bits) and uses that to verify +the *FW_MAIN_A* area of read/write section A. If the verification is successful +then verstage instructs coreboot to use the coreboot file system in read/write +section A for the contents of the remaining boot firmware (romstage, postcar, +ramstage and the payload). + +If verification fails for the read/write area and the other read/write area is +not valid vboot falls back to the read-only area to boot into system recovery. + +*** + +## Chromebook Special Features + +Google's Chromebooks have some special features: + +* Developer mode +* Write-protect screw + +### Developer Mode + +Developer mode allows the user to use coreboot to boot another operating system. +This may be a another (beta) version of Chrome OS, or another flavor of +GNU/Linux. Use of developer mode does not void the system warranty. Upon entry +into developer mode, all locally saved data on the system is lost. +This prevents someone from entering developer mode to subvert the system +security to access files on the local system or cloud. + +### Write Protect Screw + +Chromebooks have a write-protect screw which provides the ground to the +write-protect pin of the SPI flash. +Google specifically did this to allow the manufacturing line and advanced +developers to re-write the entire SPI flash part. Once the screw is removed, +any firmware may be placed on the device. +However, accessing this screw requires opening the case and voids the +system warranty! diff --git a/Makefile.inc b/Makefile.inc index fc04a16fad..a9aaaed783 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -196,14 +196,11 @@ ifeq ($(CONFIG_USE_BLOBS),y) # this is necessary because 3rdparty/blobs is update=none, and so is ignored # unless explicitly requested and enabled through --checkout forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/blobs)) -ifeq ($(CONFIG_PLATFORM_USES_FSP2_0),y) +ifeq ($(CONFIG_PLATFORM_USES_FSP1_0)$(CONFIG_PLATFORM_USES_FSP1_1)$(CONFIG_PLATFORM_USES_FSP2_0),y) +# this is necessary because 3rdparty/fsp is update=none, and so is ignored +# unless explicitly requested and enabled through --checkout forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/fsp)) endif -ifeq ($(CONFIG_PLATFORM_USES_FSP1_0),y) -ifeq ($(CONFIG_SOC_INTEL_FSP_BROADWELL_DE),y) -forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/fsp)) -endif -endif endif UPDATED_SUBMODULES:=1 COREBOOT_EXPORTS += UPDATED_SUBMODULES diff --git a/configs/config.lenovo_t420_static_option_table_no_mem_fuses b/configs/config.lenovo_t420_static_option_table_no_mem_fuses index a268d88b78..0a3513cfac 100644 --- a/configs/config.lenovo_t420_static_option_table_no_mem_fuses +++ b/configs/config.lenovo_t420_static_option_table_no_mem_fuses @@ -4,4 +4,6 @@ CONFIG_VENDOR_LENOVO=y CONFIG_BOARD_LENOVO_T420=y CONFIG_NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES=y CONFIG_NATIVE_RAMINIT_IGNORE_XMP_MAX_DIMMS=y +CONFIG_VBOOT=y +CONFIG_H8_FN_KEY_AS_VBOOT_RECOVERY_SW=y # CONFIG_INTEL_CHIPSET_LOCKDOWN is not set diff --git a/src/Kconfig b/src/Kconfig index 90c724ebb5..b4898bd456 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -370,8 +370,6 @@ source "src/superio/*/*/Kconfig" comment "Embedded Controllers" source "src/ec/acpi/Kconfig" source "src/ec/*/*/Kconfig" -# FIXME move to vendorcode -source "src/drivers/intel/fsp1_0/Kconfig" source "src/southbridge/intel/common/firmware/Kconfig" source "src/vendorcode/*/Kconfig" @@ -1155,7 +1153,6 @@ config GENERIC_SPD_BIN config DIMM_MAX int default 4 - depends on GENERIC_SPD_BIN help Total number of memory DIMM slots available on motherboard. It is multiplication of number of channel to number of DIMMs per diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index 7c87c693e1..589f4f0e30 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -999,6 +999,56 @@ static int smbios_write_type127(unsigned long *current, int handle) return len; } +/* Generate Type9 entries from devicetree */ +static int smbios_walk_device_tree_type9(struct device *dev, int *handle, + unsigned long *current) +{ + enum misc_slot_usage usage; + enum slot_data_bus_bandwidth bandwidth; + enum misc_slot_type type; + enum misc_slot_length length; + + if (dev->path.type != DEVICE_PATH_PCI) + return 0; + + if (!dev->smbios_slot_type && !dev->smbios_slot_data_width && + !dev->smbios_slot_designation && !dev->smbios_slot_length) + return 0; + + if (dev_is_active_bridge(dev)) + usage = SlotUsageInUse; + else if (dev->enabled) + usage = SlotUsageAvailable; + else + usage = SlotUsageUnknown; + + if (dev->smbios_slot_data_width) + bandwidth = dev->smbios_slot_data_width; + else + bandwidth = SlotDataBusWidthUnknown; + + if (dev->smbios_slot_type) + type = dev->smbios_slot_type; + else + type = SlotTypeUnknown; + + if (dev->smbios_slot_length) + length = dev->smbios_slot_length; + else + length = SlotLengthUnknown; + + return smbios_write_type9(current, handle, + dev->smbios_slot_designation, + type, + bandwidth, + usage, + length, + 1, + 0, + dev->bus->secondary, + dev->path.pci.devfn); +} + static int smbios_walk_device_tree(struct device *tree, int *handle, unsigned long *current) { @@ -1011,6 +1061,7 @@ static int smbios_walk_device_tree(struct device *tree, int *handle, dev_name(dev)); len += dev->ops->get_smbios_data(dev, handle, current); } + len += smbios_walk_device_tree_type9(dev, handle, current); } return len; } diff --git a/src/arch/x86/stages.c b/src/arch/x86/stages.c deleted file mode 100644 index b4d0723e16..0000000000 --- a/src/arch/x86/stages.c +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -static void skip_romstage(void) -{ - asm volatile ( - "jmp __main\n" - ); -} diff --git a/src/commonlib/cbfs.c b/src/commonlib/cbfs.c index 4379099ffe..a509bc9f61 100644 --- a/src/commonlib/cbfs.c +++ b/src/commonlib/cbfs.c @@ -18,6 +18,7 @@ #include #include #include +#include #if !defined(ERROR) #define ERROR(x...) printk(BIOS_ERR, "CBFS: " x) diff --git a/src/console/vtxprintf.c b/src/console/vtxprintf.c index 043a1dae37..f42ed6d077 100644 --- a/src/console/vtxprintf.c +++ b/src/console/vtxprintf.c @@ -56,8 +56,10 @@ static int number(void (*tx_byte)(unsigned char byte, void *data), int count = 0; #ifdef SUPPORT_64BIT_INTS unsigned long long num = inum; + long long snum = num; #else - unsigned long num = (long)inum; + unsigned long num = (unsigned long)inum; + long snum = (long)num; if (num != inum) { /* Alert user to an incorrect result by printing #^!. */ @@ -76,9 +78,9 @@ static int number(void (*tx_byte)(unsigned char byte, void *data), c = (type & ZEROPAD) ? '0' : ' '; sign = 0; if (type & SIGN) { - if ((signed long long)num < 0) { + if (snum < 0) { sign = '-'; - num = -num; + num = -snum; size--; } else if (type & PLUS) { sign = '+'; diff --git a/src/device/device_util.c b/src/device/device_util.c index 5c4f911b8b..47df3052e2 100644 --- a/src/device/device_util.c +++ b/src/device/device_util.c @@ -628,7 +628,7 @@ void disable_children(struct bus *bus) /* * Returns true if the device is an enabled bridge that has at least - * one enabled device on its secondary bus. + * one enabled device on its secondary bus that is not of type NONE. */ bool dev_is_active_bridge(struct device *dev) { @@ -643,6 +643,9 @@ bool dev_is_active_bridge(struct device *dev) for (link = dev->link_list; link; link = link->next) { for (child = link->children; child; child = child->sibling) { + if (child->path.type == DEVICE_PATH_NONE) + continue; + if (child->enabled) return 1; } diff --git a/src/drivers/intel/fsp1_1/Kconfig b/src/drivers/intel/fsp1_1/Kconfig index 2575577ba4..a8658ec7e6 100644 --- a/src/drivers/intel/fsp1_1/Kconfig +++ b/src/drivers/intel/fsp1_1/Kconfig @@ -25,8 +25,14 @@ if PLATFORM_USES_FSP1_1 comment "Intel FSP 1.1" +config FSP_USE_REPO + bool "Use FSP binary from 3rdparty/fsp repo" + select HAVE_FSP_BIN + depends on SOC_INTEL_BRASWELL && !USE_GOOGLE_FSP + default y + config HAVE_FSP_BIN - bool "Should the Intel FSP binary be added to the flash image" + bool "Add Intel FSP binary to flash image" help Select this option to add an Intel FSP binary to the resulting coreboot image. @@ -34,6 +40,25 @@ config HAVE_FSP_BIN Note: Without this binary, coreboot builds relying on the FSP will not boot +config FSP_FILE + string + prompt "Intel FSP binary path and filename" if !FSP_USE_REPO + depends on HAVE_FSP_BIN + default "3rdparty/fsp/BraswellFspBinPkg/FspBin/BSWFSP.fd" if FSP_USE_REPO + default "" + help + The path and filename of the Intel FSP binary for this platform. + +config FSP_LOC + hex "Intel FSP Binary location in CBFS" + default 0xfff6e000 if SOC_INTEL_BRASWELL && USE_GOOGLE_FSP + default 0xfff20000 if SOC_INTEL_BRASWELL + default 0xffee0000 if SOC_INTEL_SKYLAKE + help + The location in CBFS that the FSP is located. This must match the + value that is set in the FSP binary. If the FSP needs to be moved, + rebase the FSP with Intel's BCT (tool). + config CPU_MICROCODE_CBFS_LEN hex "Microcode update region length in bytes" default 0x0 @@ -47,19 +72,6 @@ config CPU_MICROCODE_CBFS_LOC The location (base address) in CBFS that contains the microcode update binary. -config FSP_FILE - string "Intel FSP binary path and filename" - help - The path and filename of the Intel FSP binary for this platform. - -config FSP_LOC - hex "Intel FSP Binary location in CBFS" - default 0xffee0000 - help - The location in CBFS that the FSP is located. This must match the - value that is set in the FSP binary. If the FSP needs to be moved, - rebase the FSP with Intel's BCT (tool). - config DISPLAY_HOBS bool "Display hand-off-blocks (HOBs)" default n diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.inc b/src/drivers/intel/fsp1_1/cache_as_ram.inc index 48fcb8f39f..fa5c40677b 100644 --- a/src/drivers/intel/fsp1_1/cache_as_ram.inc +++ b/src/drivers/intel/fsp1_1/cache_as_ram.inc @@ -24,9 +24,8 @@ * performs the final stage of initialization. */ - -#define LHLT_DELAY 0x50000 /* I/O delay between post codes on failure */ - +/* I/O delay between post codes on failure */ +#define LHLT_DELAY 0x50000 /* * Per FSP1.1 specs, following registers are preserved: * EBX, EDI, ESI, EBP, MM0, MM1 @@ -165,8 +164,8 @@ halt1: * 0x01 - FV signature, "_FVH" not present * 0x02 - FFS GUID not present * 0x03 - FSP INFO Header not found - * 0x04 - ImageBase does not equal CONFIG_FSP_LOC - Is the FSP rebased to - * a different location, or does it need to be? + * 0x04 - ImageBase does not equal CONFIG_FSP_LOC - Is the FSP rebased + * to a different location, or does it need to be? * 0x05 - FSP INFO Header signature "FSPH" not found * 0x06 - FSP Image ID is not the expected ID. */ @@ -181,7 +180,8 @@ halt2: * 0x02 - FSP_INVALID_PARAMETER: Input parameters are invalid. * 0x03 - FSP_UNSUPPORTED: The FSP calling conditions were not met. * 0x07 - FSP_DEVICE_ERROR: Temp RAM initialization failed - * 0x0E - FSP_NOT_FOUND: No valid microcode was found in the microcode region. + * 0x0E - FSP_NOT_FOUND: No valid microcode was found in the microcode + * region. * 0x14 - FSP_ALREADY_STARTED: Temp RAM initialization has been invoked */ movb $0xBB, %ah @@ -213,7 +213,7 @@ CAR_init_params: .long CONFIG_CPU_MICROCODE_CBFS_LOC /* Microcode Location */ .long CONFIG_CPU_MICROCODE_CBFS_LEN /* Microcode Length */ .long 0xFFFFFFFF - CONFIG_ROM_SIZE + 1 /* Firmware Location */ - .long CONFIG_ROM_SIZE /* Total Firmware Length */ + .long CONFIG_ROM_SIZE /* Firmware Length */ CAR_init_stack: .long CAR_init_done diff --git a/src/drivers/intel/fsp1_1/include/fsp/romstage.h b/src/drivers/intel/fsp1_1/include/fsp/romstage.h index d608484999..b01f11059c 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/romstage.h +++ b/src/drivers/intel/fsp1_1/include/fsp/romstage.h @@ -18,20 +18,28 @@ #ifndef _COMMON_ROMSTAGE_H_ #define _COMMON_ROMSTAGE_H_ +#include #include #include #include #include #include #include -#include #include /* chip_power_state */ struct romstage_params { uint32_t fsp_version; struct chipset_power_state *power_state; - struct pei_data *pei_data; void *chipset_context; + + /* Fast boot and S3 resume MRC data */ + size_t saved_data_size; + const void *saved_data; + bool disable_saved_data; + + /* New save data from MRC */ + size_t data_to_save_size; + const void *data_to_save; }; /* diff --git a/src/drivers/intel/fsp1_1/raminit.c b/src/drivers/intel/fsp1_1/raminit.c index 8405c943aa..726cc26a0c 100644 --- a/src/drivers/intel/fsp1_1/raminit.c +++ b/src/drivers/intel/fsp1_1/raminit.c @@ -28,6 +28,7 @@ void raminit(struct romstage_params *params) { + const bool s3wake = params->power_state->prev_sleep_state == ACPI_S3; const EFI_GUID bootldr_tolum_guid = FSP_BOOTLOADER_TOLUM_HOB_GUID; EFI_HOB_RESOURCE_DESCRIPTOR *cbmem_root; FSP_INFO_HEADER *fsp_header; @@ -46,7 +47,6 @@ void raminit(struct romstage_params *params) u32 *mrc_hob; u32 fsp_reserved_bytes; MEMORY_INIT_UPD *original_params; - struct pei_data *pei_ptr; EFI_STATUS status; VPD_DATA_REGION *vpd_ptr; UPD_DATA_REGION *upd_ptr; @@ -80,10 +80,9 @@ void raminit(struct romstage_params *params) /* Zero fill RT Buffer data and start populating fields. */ memset(&fsp_rt_common_buffer, 0, sizeof(fsp_rt_common_buffer)); - pei_ptr = params->pei_data; - if (pei_ptr->boot_mode == ACPI_S3) { + if (s3wake) { fsp_rt_common_buffer.BootMode = BOOT_ON_S3_RESUME; - } else if (pei_ptr->saved_data != NULL) { + } else if (params->saved_data != NULL) { fsp_rt_common_buffer.BootMode = BOOT_ASSUMING_NO_CONFIGURATION_CHANGES; } else { @@ -93,7 +92,7 @@ void raminit(struct romstage_params *params) fsp_rt_common_buffer.BootLoaderTolumSize = cbmem_overhead_size(); /* Get any board specific changes */ - fsp_memory_init_params.NvsBufferPtr = (void *)pei_ptr->saved_data; + fsp_memory_init_params.NvsBufferPtr = (void *)params->saved_data; fsp_memory_init_params.RtBufferPtr = &fsp_rt_common_buffer; fsp_memory_init_params.HobListPtr = &hob_list_ptr; @@ -158,7 +157,7 @@ void raminit(struct romstage_params *params) /* Migrate CAR data */ printk(BIOS_DEBUG, "0x%p: cbmem_top\n", cbmem_top()); - if (pei_ptr->boot_mode != ACPI_S3) { + if (!s3wake) { cbmem_initialize_empty_id_size(CBMEM_ID_FSP_RESERVED_MEMORY, fsp_reserved_bytes); } else if (cbmem_initialize_id_size(CBMEM_ID_FSP_RESERVED_MEMORY, @@ -220,7 +219,7 @@ void raminit(struct romstage_params *params) } hob_ptr.Raw = get_next_guid_hob(&mrc_guid, hob_list_ptr); if (hob_ptr.Raw == NULL) { - if (params->pei_data->saved_data == NULL) { + if (params->saved_data == NULL) { printk(BIOS_ERR, "7.3: FSP_NON_VOLATILE_STORAGE_HOB missing!\n"); fsp_verification_failure = 1; } @@ -294,8 +293,8 @@ void raminit(struct romstage_params *params) "Memory Configuration Data Hob not present\n"); else if (!vboot_recovery_mode_enabled()) { /* Do not save MRC data in recovery path */ - pei_ptr->data_to_save = GET_GUID_HOB_DATA(mrc_hob); - pei_ptr->data_to_save_size = ALIGN( + params->data_to_save = GET_GUID_HOB_DATA(mrc_hob); + params->data_to_save_size = ALIGN( ((u32)GET_HOB_LENGTH(mrc_hob)), 16); } } diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c index ebb6a6678b..433e16cf13 100644 --- a/src/drivers/intel/fsp1_1/romstage.c +++ b/src/drivers/intel/fsp1_1/romstage.c @@ -41,9 +41,7 @@ asmlinkage void *romstage_main(FSP_INFO_HEADER *fih) { void *top_of_stack; - struct pei_data pei_data; struct romstage_params params = { - .pei_data = &pei_data, .chipset_context = fih, }; @@ -55,8 +53,6 @@ asmlinkage void *romstage_main(FSP_INFO_HEADER *fih) if (CONFIG(SUPPORT_CPU_UCODE_IN_CBFS)) intel_update_microcode_from_cbfs(); - memset(&pei_data, 0, sizeof(pei_data)); - /* Display parameters */ if (!CONFIG(NO_MMCONF_SUPPORT)) printk(BIOS_SPEW, "CONFIG_MMCONF_BASE_ADDRESS: 0x%08x\n", @@ -94,14 +90,11 @@ void romstage_common(struct romstage_params *params) { bool s3wake; struct region_device rdev; - struct pei_data *pei_data; post_code(0x32); timestamp_add_now(TS_BEFORE_INITRAM); - pei_data = params->pei_data; - pei_data->boot_mode = params->power_state->prev_sleep_state; s3wake = params->power_state->prev_sleep_state == ACPI_S3; if (CONFIG(ELOG_BOOT_COUNT) && !s3wake) @@ -112,9 +105,9 @@ void romstage_common(struct romstage_params *params) post_code(0x33); /* Check recovery and MRC cache */ - params->pei_data->saved_data_size = 0; - params->pei_data->saved_data = NULL; - if (!params->pei_data->disable_saved_data) { + params->saved_data_size = 0; + params->saved_data = NULL; + if (!params->disable_saved_data) { if (vboot_recovery_mode_enabled()) { /* Recovery mode does not use MRC cache */ printk(BIOS_DEBUG, @@ -124,12 +117,11 @@ void romstage_common(struct romstage_params *params) params->fsp_version, &rdev))) { /* MRC cache found */ - params->pei_data->saved_data_size = - region_device_sz(&rdev); - params->pei_data->saved_data = rdev_mmap_full(&rdev); + params->saved_data_size = region_device_sz(&rdev); + params->saved_data = rdev_mmap_full(&rdev); /* Assume boot device is memory mapped. */ assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED)); - } else if (params->pei_data->boot_mode == ACPI_S3) { + } else if (s3wake) { /* Waking from S3 and no cache. */ printk(BIOS_DEBUG, "No MRC cache found in S3 resume path.\n"); @@ -147,15 +139,15 @@ void romstage_common(struct romstage_params *params) /* Save MRC output */ if (CONFIG(CACHE_MRC_SETTINGS)) { - printk(BIOS_DEBUG, "MRC data at %p %d bytes\n", - pei_data->data_to_save, pei_data->data_to_save_size); - if ((params->pei_data->boot_mode != ACPI_S3) - && (params->pei_data->data_to_save_size != 0) - && (params->pei_data->data_to_save != NULL)) + printk(BIOS_DEBUG, "MRC data at %p %zu bytes\n", + params->data_to_save, params->data_to_save_size); + if (!s3wake + && (params->data_to_save_size != 0) + && (params->data_to_save != NULL)) mrc_cache_stash_data(MRC_TRAINING_DATA, params->fsp_version, - params->pei_data->data_to_save, - params->pei_data->data_to_save_size); + params->data_to_save, + params->data_to_save_size); } /* Save DIMM information */ @@ -343,13 +335,6 @@ __weak int mrc_cache_stash_data(int type, uint32_t version, return -1; } -/* Transition RAM from off or self-refresh to active */ -__weak void raminit(struct romstage_params *params) -{ - post_code(POST_MEM_PREINIT_PREP_START); - die("ERROR - No RAM initialization specified!\n"); -} - /* Display the memory configuration */ __weak void report_memory_config(void) { diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index 985ee3a07f..b3afb98c4d 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -310,8 +310,6 @@ static void do_fsp_memory_init(struct fsp_header *hdr, bool s3wake, post_code(POST_FSP_MEMORY_EXIT); timestamp_add_now(TS_FSP_MEMORY_INIT_END); - fsp_debug_after_memory_init(status); - /* Handle any errors returned by FspMemoryInit */ fsp_handle_reset(status); if (status != FSP_SUCCESS) { @@ -320,6 +318,13 @@ static void do_fsp_memory_init(struct fsp_header *hdr, bool s3wake, } do_fsp_post_memory_init(s3wake, fsp_version); + + /* + * fsp_debug_after_memory_init() checks whether the end of the tolum + * region is the same as the top of cbmem, so must be called here + * after cbmem has been initialised in do_fsp_post_memory_init(). + */ + fsp_debug_after_memory_init(status); } /* Load the binary into the memory specified by the info header. */ diff --git a/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c b/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c index e26701b099..cdc98e06de 100644 --- a/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c +++ b/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c @@ -45,9 +45,6 @@ static efi_return_status_t mp_get_processor_info(const efi_uintn_t processor_number, efi_processor_information *processor_info_buffer) { - if (cpu_index() < 0) - return FSP_DEVICE_ERROR; - if (processor_info_buffer == NULL) return FSP_INVALID_PARAMETER; @@ -71,9 +68,6 @@ static efi_return_status_t mp_startup_all_aps(const efi_ap_procedure procedure, efi_boolean_t ignored3, efi_uintn_t timeout_usec, void *argument) { - if (cpu_index() < 0) - return FSP_DEVICE_ERROR; - if (procedure == NULL) return FSP_INVALID_PARAMETER; @@ -91,9 +85,6 @@ static efi_return_status_t mp_startup_this_ap(const efi_ap_procedure procedure, efi_uintn_t processor_number, efi_uintn_t timeout_usec, void *argument) { - if (cpu_index() < 0) - return FSP_DEVICE_ERROR; - if (processor_number > get_cpu_count()) return FSP_NOT_FOUND; diff --git a/src/drivers/pc80/rtc/mc146818rtc.c b/src/drivers/pc80/rtc/mc146818rtc.c index 99079b985e..6e37cd2f78 100644 --- a/src/drivers/pc80/rtc/mc146818rtc.c +++ b/src/drivers/pc80/rtc/mc146818rtc.c @@ -39,6 +39,9 @@ #define LB_CKS_LOC 0 #endif +/* Don't warn for checking >= LB_CKS_RANGE_START even though it may be 0. */ +#pragma GCC diagnostic ignored "-Wtype-limits" + #include #if (defined(__PRE_RAM__) && \ diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c index fc831c3e9c..ae1d2efb22 100644 --- a/src/drivers/spi/spi_flash.c +++ b/src/drivers/spi/spi_flash.c @@ -339,7 +339,7 @@ int spi_flash_generic_probe(const struct spi_slave *spi, printk(BIOS_INFO, "Manufacturer: %02x\n", *idp); /* search the table for matches in shift and id */ - for (i = 0; i < ARRAY_SIZE(flashes); ++i) + for (i = 0; i < (int)ARRAY_SIZE(flashes); ++i) if (flashes[i].shift == shift && flashes[i].idcode == *idp) { /* we have a match, call probe */ if (flashes[i].probe(spi, idp, flash) == 0) { diff --git a/src/ec/lenovo/h8/Kconfig b/src/ec/lenovo/h8/Kconfig index b109831105..d874975428 100644 --- a/src/ec/lenovo/h8/Kconfig +++ b/src/ec/lenovo/h8/Kconfig @@ -32,6 +32,14 @@ config H8_HAS_BAT_TRESHOLDS_IMPL bool default n +config H8_FN_KEY_AS_VBOOT_RECOVERY_SW + bool "Enable Fn-Key as VBOOT recovery switch" + depends on VBOOT + default n + help + If VBOOT is enabled, press Fn-Key at power on to force a recovery mode + boot instead of regular FW_MAIN_x boot. + endif config H8_DOCK_EARLY_INIT diff --git a/src/ec/lenovo/h8/Makefile.inc b/src/ec/lenovo/h8/Makefile.inc index ebf6d7d7a4..51c11be625 100644 --- a/src/ec/lenovo/h8/Makefile.inc +++ b/src/ec/lenovo/h8/Makefile.inc @@ -1,5 +1,18 @@ ifeq ($(CONFIG_EC_LENOVO_H8),y) +ramstage-y += sense.c +verstage-y += sense.c +romstage-y += sense.c +bootblock-y += sense.c +postcar-y += sense.c +smm-y += sense.c + +ramstage-$(CONFIG_VBOOT) += vboot.c +verstage-$(CONFIG_VBOOT) += vboot.c +romstage-$(CONFIG_VBOOT) += vboot.c +bootblock-$(CONFIG_VBOOT) += vboot.c +postcar-$(CONFIG_VBOOT) += vboot.c + ifneq ($(filter y,$(CONFIG_H8_BEEP_ON_DEATH) $(CONFIG_H8_FLASH_LEDS_ON_DEATH)),) romstage-y += panic.c ramstage-y += panic.c diff --git a/src/ec/lenovo/h8/h8.h b/src/ec/lenovo/h8/h8.h index a46ba1f5e0..14948c55ce 100644 --- a/src/ec/lenovo/h8/h8.h +++ b/src/ec/lenovo/h8/h8.h @@ -38,6 +38,9 @@ void h8_usb_always_on(void); void h8_mainboard_init_dock (void); +int h8_get_fn_key(void); +int h8_get_sense_ready(void); + void h8_bluetooth_enable(int on); bool h8_bluetooth_nv_enable(void); bool h8_has_bdc(struct device *dev); @@ -135,8 +138,10 @@ void h8_ssdt_generator(struct device *dev); #define H8_EVENT_FN_PRESS 0x39 #define H8_STATUS0 0x46 +#define H8_STATUS0_FN_KEY_DOWN 0x01 #define H8_STATUS1 0x47 #define H8_STATUS2 0x48 +#define H8_STATUS3 0x49 #define H8_EVENT_BAT0 0x4a #define H8_EVENT_BAT0_STATE 0x4b diff --git a/src/ec/lenovo/h8/sense.c b/src/ec/lenovo/h8/sense.c new file mode 100644 index 0000000000..b929d7ede3 --- /dev/null +++ b/src/ec/lenovo/h8/sense.c @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Patrick Rudolph + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +#include "h8.h" + +/** + * Return the EC sense status register state. + * + * Observations showed the sense registers are all zero until the EC populates + * them after some time. Likely the EC sets all bits to it's valid state at + * once, but there's no prove as the firmware isn't available. + * + * Wait for any register having at least one bit set. + * Unlikely that all register will be zero after booting has finished. + * + * @return 1 if the EC provides valid data in sense status registers + */ +int h8_get_sense_ready(void) +{ + static const u8 regs[] = { H8_STATUS0, H8_STATUS1, H8_STATUS2, + H8_STATUS3}; + + for (size_t i = 0; i < ARRAY_SIZE(regs); i++) { + if (ec_read(regs[i])) + return 1; + } + + return 0; +} + +/** + * Return the state of Fn key. + * Only valid if h8_get_sense_ready (see above) returns true. + * + * @return 1 if the key is pressed. + */ +int h8_get_fn_key(void) +{ + return ec_read(H8_STATUS0) & H8_STATUS0_FN_KEY_DOWN; +} diff --git a/src/ec/lenovo/h8/vboot.c b/src/ec/lenovo/h8/vboot.c new file mode 100644 index 0000000000..3b9f74a117 --- /dev/null +++ b/src/ec/lenovo/h8/vboot.c @@ -0,0 +1,55 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Patrick Rudolph + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include + +#include "h8.h" + +/** + * HACK: Use Fn-Key as recovery mode switch. + * Wait for sense register ready and read Fn-Key state. + */ +int get_recovery_mode_switch(void) +{ + struct stopwatch sw; + + if (!CONFIG(H8_FN_KEY_AS_VBOOT_RECOVERY_SW)) + return 0; + + /* Tests showed that it takes: + * - 700msec on Lenovo T500 from AC power on + * - less than 150msec on Lenovo T520 from AC power on + */ + stopwatch_init_msecs_expire(&sw, 1000); + while (!stopwatch_expired(&sw) && !h8_get_sense_ready()) + mdelay(1); + + if (!h8_get_sense_ready()) + return 0; + + return h8_get_fn_key(); +} + +/** + * Only used if CONFIG_CHROMEOS is set. + * Always zero as the #WP pin of the flash is tied high. + */ +int get_write_protect_state(void) +{ + return 0; +} diff --git a/src/include/assert.h b/src/include/assert.h index 6036635273..4575a29e44 100644 --- a/src/include/assert.h +++ b/src/include/assert.h @@ -19,6 +19,12 @@ #include #include +/* TODO: Fix vendorcode headers to not define macros coreboot uses or to be more + properly isolated. */ +#ifdef ASSERT +#undef ASSERT +#endif + /* GCC and CAR versions */ #define ASSERT(x) { \ if (!(x)) { \ diff --git a/src/include/device/device.h b/src/include/device/device.h index 39a4d567a2..32cf07282b 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -141,6 +141,12 @@ struct device { #if !DEVTREE_EARLY struct chip_operations *chip_ops; const char *name; +#if CONFIG(GENERATE_SMBIOS_TABLES) + u8 smbios_slot_type; + u8 smbios_slot_data_width; + u8 smbios_slot_length; + const char *smbios_slot_designation; +#endif #endif DEVTREE_CONST void *chip_info; }; diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 85bd6c3864..64539510ce 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2689,6 +2689,11 @@ #define PCI_DEVICE_ID_INTEL_SPT_LP_U_BASE 0x9d43 #define PCI_DEVICE_ID_INTEL_SPT_LP_U_PREMIUM 0x9d48 #define PCI_DEVICE_ID_INTEL_SPT_LP_Y_PREMIUM 0x9d46 +#define PCI_DEVICE_ID_INTEL_SPT_H_H170 0xa144 +#define PCI_DEVICE_ID_INTEL_SPT_H_Z170 0xa145 +#define PCI_DEVICE_ID_INTEL_SPT_H_Q170 0xa146 +#define PCI_DEVICE_ID_INTEL_SPT_H_Q150 0xa147 +#define PCI_DEVICE_ID_INTEL_SPT_H_B150 0xa148 #define PCI_DEVICE_ID_INTEL_SPT_H_C236 0xa150 #define PCI_DEVICE_ID_INTEL_SPT_H_PREMIUM 0xa14e #define PCI_DEVICE_ID_INTEL_SPT_H_H110 0xa143 diff --git a/src/mainboard/apple/macbook21/romstage.c b/src/mainboard/apple/macbook21/romstage.c index c056ac8fcb..468cffb7d9 100644 --- a/src/mainboard/apple/macbook21/romstage.c +++ b/src/mainboard/apple/macbook21/romstage.c @@ -26,7 +26,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/apple/macbookair4_2/Kconfig b/src/mainboard/apple/macbookair4_2/Kconfig index 82f120ab08..4b2ee8fdc8 100644 --- a/src/mainboard/apple/macbookair4_2/Kconfig +++ b/src/mainboard/apple/macbookair4_2/Kconfig @@ -12,7 +12,7 @@ config BOARD_SPECIFIC_OPTIONS select SERIRQ_CONTINUOUS_MODE select SOUTHBRIDGE_INTEL_BD82X6X select SYSTEM_TYPE_LAPTOP - select GFX_GMA_INTERNAL_IS_LVDS + select GFX_GMA_INTERNAL_IS_EDP select MAINBOARD_HAS_LIBGFXINIT config MAINBOARD_DIR diff --git a/src/mainboard/asus/p5gc-mx/romstage.c b/src/mainboard/asus/p5gc-mx/romstage.c index beb276c7da..08379f78a1 100644 --- a/src/mainboard/asus/p5gc-mx/romstage.c +++ b/src/mainboard/asus/p5gc-mx/romstage.c @@ -29,7 +29,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/asus/p5qpl-am/romstage.c b/src/mainboard/asus/p5qpl-am/romstage.c index 4174981ac2..bd6bfc6ee7 100644 --- a/src/mainboard/asus/p5qpl-am/romstage.c +++ b/src/mainboard/asus/p5qpl-am/romstage.c @@ -24,7 +24,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c index d643b12f8a..aaa3422c02 100644 --- a/src/mainboard/getac/p470/romstage.c +++ b/src/mainboard/getac/p470/romstage.c @@ -25,7 +25,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/google/beltino/mainboard.c b/src/mainboard/google/beltino/mainboard.c index e0fd105eb1..7bda2f6694 100644 --- a/src/mainboard/google/beltino/mainboard.c +++ b/src/mainboard/google/beltino/mainboard.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include #include #include #include @@ -25,8 +24,8 @@ #include #include #include -#include "onboard.h" +#include "onboard.h" void mainboard_suspend_resume(void) { diff --git a/src/mainboard/google/cheza/chromeos.fmd b/src/mainboard/google/cheza/chromeos.fmd index 71e85562d6..b0d2d99996 100644 --- a/src/mainboard/google/cheza/chromeos.fmd +++ b/src/mainboard/google/cheza/chromeos.fmd @@ -24,16 +24,15 @@ FLASH@0x0 8M { RO_FRID 0x100 } RO_VPD(PRESERVE) 16K - # TODO(hungte): Remove RO_PRESERVE. - RO_PRESERVE(PRESERVE) { - RO_DDR_TRAINING 8K - RO_FSG - } + RO_DDR_TRAINING(PRESERVE) 8K + RO_LIMITS_CFG(PRESERVE) 4K + RO_FSG(PRESERVE) } RW_VPD(PRESERVE) 32K RW_NVRAM(PRESERVE) 16K - RW_DDR_TRAINING 8K + RW_DDR_TRAINING(PRESERVE) 8K + RW_LIMITS_CFG(PRESERVE) 4K RW_ELOG(PRESERVE) 4K RW_SHARED 4K { SHARED_DATA diff --git a/src/mainboard/google/cheza/mainboard.c b/src/mainboard/google/cheza/mainboard.c index cb4f5d061a..42adf56c79 100644 --- a/src/mainboard/google/cheza/mainboard.c +++ b/src/mainboard/google/cheza/mainboard.c @@ -16,9 +16,23 @@ #include #include #include +#include +#include + +static struct usb_board_data usb1_board_data = { + .pll_bias_control_2 = 0x28, + .imp_ctrl1 = 0x08, + .port_tune1 = 0x20, +}; static void setup_usb(void) { + /* + * Primary USB is used only for DP functionality on cheza platform. + * Hence Setting up only Secondary USB DWC3 controller. + */ + setup_usb_host1(&usb1_board_data); + gpio_output(GPIO(120), 1); /* Deassert HUB_RST_L to enable hub. */ } diff --git a/src/mainboard/google/cheza/romstage.c b/src/mainboard/google/cheza/romstage.c index ad8506193d..de737b1159 100644 --- a/src/mainboard/google/cheza/romstage.c +++ b/src/mainboard/google/cheza/romstage.c @@ -14,7 +14,22 @@ */ #include +#include +#include + +static void prepare_usb(void) +{ + /* + * Do DWC3 core and phy reset. Kick these resets + * off early so they get at least 1ms to settle. + */ + reset_usb1(); +} void platform_romstage_main(void) { + prepare_usb(); + + /* QCLib: DDR init & train */ + qclib_load_and_run(); } diff --git a/src/mainboard/google/cyan/Kconfig b/src/mainboard/google/cyan/Kconfig index b3c6790e57..aac14c06c3 100644 --- a/src/mainboard/google/cyan/Kconfig +++ b/src/mainboard/google/cyan/Kconfig @@ -16,6 +16,7 @@ config BOARD_GOOGLE_BASEBOARD_CYAN select HAVE_ACPI_RESUME select PCIEXP_L1_SUB_STATE if !BOARD_GOOGLE_CYAN select SYSTEM_TYPE_LAPTOP + select USE_GOOGLE_FSP if BOARD_GOOGLE_BASEBOARD_CYAN diff --git a/src/mainboard/google/cyan/acpi/codec_maxim.asl b/src/mainboard/google/cyan/acpi/codec_maxim.asl index 81bec16ea5..b412551a4a 100644 --- a/src/mainboard/google/cyan/acpi/codec_maxim.asl +++ b/src/mainboard/google/cyan/acpi/codec_maxim.asl @@ -35,7 +35,7 @@ Scope (\_SB.PCI0.I2C2) } }) - Method(_CRS, 0x0, NotSerialized) + Method(_CRS, 0x0, Serialized) { Name(SBUF,ResourceTemplate () { diff --git a/src/mainboard/google/cyan/acpi/codec_realtek.asl b/src/mainboard/google/cyan/acpi/codec_realtek.asl index 4a1d48de7b..d697aace3e 100644 --- a/src/mainboard/google/cyan/acpi/codec_realtek.asl +++ b/src/mainboard/google/cyan/acpi/codec_realtek.asl @@ -26,7 +26,7 @@ Scope (\_SB.PCI0.I2C5) Name (_DDN, AUDIO_CODEC_DDN) Name (_UID, 1) - Method(_CRS, 0x0, NotSerialized) + Method(_CRS, 0x0, Serialized) { Name(SBUF,ResourceTemplate () { diff --git a/src/mainboard/google/cyan/romstage.c b/src/mainboard/google/cyan/romstage.c index aa20593d5f..c877e42055 100644 --- a/src/mainboard/google/cyan/romstage.c +++ b/src/mainboard/google/cyan/romstage.c @@ -16,15 +16,12 @@ #include #include -#include + +#include "spd/spd_util.h" /* All FSP specific code goes in this block */ void mainboard_romstage_entry(struct romstage_params *rp) { - struct pei_data *ps = rp->pei_data; - - mainboard_fill_spd_data(ps); - /* Call back into chipset code with platform values updated. */ romstage_common(rp); } @@ -32,16 +29,7 @@ void mainboard_romstage_entry(struct romstage_params *rp) void mainboard_memory_init_params(struct romstage_params *params, MEMORY_INIT_UPD *memory_params) { - /* Update SPD data */ - if (CONFIG(BOARD_GOOGLE_CYAN)) { - memory_params->PcdMemoryTypeEnable = MEM_DDR3; - memory_params->PcdMemorySpdPtr = - (u32)params->pei_data->spd_data_ch0; - } else - memory_params->PcdMemoryTypeEnable = MEM_LPDDR3; - - memory_params->PcdMemChannel0Config = params->pei_data->spd_ch0_config; - memory_params->PcdMemChannel1Config = params->pei_data->spd_ch1_config; + spd_memory_init_params(memory_params); /* Variant-specific memory params */ variant_memory_init_params(memory_params); diff --git a/src/mainboard/google/cyan/spd/spd.c b/src/mainboard/google/cyan/spd/spd.c index af694a4339..7c66e947fc 100644 --- a/src/mainboard/google/cyan/spd/spd.c +++ b/src/mainboard/google/cyan/spd/spd.c @@ -40,11 +40,24 @@ __weak uint8_t get_ramid(void) return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); } -static void *get_spd_pointer(char *spd_file_content, int total_spds, int *dual) +static void *get_spd_pointer(int *dual) { + char *spd_file; + size_t spd_file_len; + int total_spds; int ram_id = 0; int spd_index = 0; + /* Find the SPD data in CBFS. */ + spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, + &spd_file_len); + if (!spd_file) + die("SPD data not found."); + + if (spd_file_len < SPD_PAGE_LEN) + die("Missing SPD data."); + total_spds = spd_file_len / SPD_PAGE_LEN; + ram_id = get_ramid(); printk(BIOS_DEBUG, "ram_id=%d, total_spds: %d\n", ram_id, total_spds); @@ -54,33 +67,20 @@ static void *get_spd_pointer(char *spd_file_content, int total_spds, int *dual) return NULL; } /* Return the serial product data for the RAM */ - return &spd_file_content[SPD_PAGE_LEN * spd_index]; + return &spd_file[SPD_PAGE_LEN * spd_index]; } /* Copy SPD data for on-board memory */ -void mainboard_fill_spd_data(struct pei_data *ps) +void spd_memory_init_params(MEMORY_INIT_UPD *memory_params) { - char *spd_file; - size_t spd_file_len; void *spd_content; int dual_channel = 0; - /* Find the SPD data in CBFS. */ - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); - if (!spd_file) - die("SPD data not found."); - - if (spd_file_len < SPD_PAGE_LEN) - die("Missing SPD data."); - /* * Both channels are always present in SPD data. Always use matched * DIMMs so use the same SPD data for each DIMM. */ - spd_content = get_spd_pointer(spd_file, - spd_file_len / SPD_PAGE_LEN, - &dual_channel); + spd_content = get_spd_pointer(&dual_channel); if (CONFIG(DISPLAY_SPD_DATA) && spd_content != NULL) { printk(BIOS_DEBUG, "SPD Data:\n"); hexdump(spd_content, SPD_PAGE_LEN); @@ -94,21 +94,27 @@ void mainboard_fill_spd_data(struct pei_data *ps) * 2=DimmDisabled */ if (spd_content != NULL) { - ps->spd_data_ch0 = spd_content; - ps->spd_ch0_config = 1; + memory_params->PcdMemChannel0Config = 1; printk(BIOS_DEBUG, "Channel 0 DIMM soldered down\n"); if (dual_channel) { printk(BIOS_DEBUG, "Channel 1 DIMM soldered down\n"); - ps->spd_data_ch1 = spd_content; - ps->spd_ch1_config = 1; + memory_params->PcdMemChannel1Config = 1; } else { printk(BIOS_DEBUG, "Channel 1 DIMM not installed\n"); - ps->spd_ch1_config = 2; + memory_params->PcdMemChannel1Config = 2; } } + + /* Update SPD data */ + if (CONFIG(BOARD_GOOGLE_CYAN)) { + memory_params->PcdMemoryTypeEnable = MEM_DDR3; + memory_params->PcdMemorySpdPtr = (uintptr_t)spd_content; + } else { + memory_params->PcdMemoryTypeEnable = MEM_LPDDR3; + } } -static void set_dimm_info(uint8_t *spd, struct dimm_info *dimm) +static void set_dimm_info(const uint8_t *spd, struct dimm_info *dimm) { const int spd_capmb[8] = { 1, 2, 4, 8, 16, 32, 64, 0 }; const int spd_ranks[8] = { 1, 2, 3, 4, -1, -1, -1, -1 }; @@ -171,9 +177,15 @@ static void set_dimm_info(uint8_t *spd, struct dimm_info *dimm) void mainboard_save_dimm_info(struct romstage_params *params) { + const void *spd_content; + int dual_channel; struct dimm_info *dimm; struct memory_info *mem_info; + spd_content = get_spd_pointer(&dual_channel); + if (spd_content == NULL) + return; + /* * Allocate CBMEM area for DIMM information used to populate SMBIOS * table 17 @@ -186,13 +198,13 @@ void mainboard_save_dimm_info(struct romstage_params *params) /* Describe the first channel memory */ dimm = &mem_info->dimm[0]; - set_dimm_info(params->pei_data->spd_data_ch0, dimm); + set_dimm_info(spd_content, dimm); mem_info->dimm_cnt = 1; /* Describe the second channel memory */ - if (params->pei_data->spd_ch1_config == 1) { + if (dual_channel) { dimm = &mem_info->dimm[1]; - set_dimm_info(params->pei_data->spd_data_ch1, dimm); + set_dimm_info(spd_content, dimm); dimm->channel_num = 1; mem_info->dimm_cnt = 2; } diff --git a/src/mainboard/google/cyan/spd/spd_util.h b/src/mainboard/google/cyan/spd/spd_util.h index 11d6eaa16d..0c5b3265ef 100644 --- a/src/mainboard/google/cyan/spd/spd_util.h +++ b/src/mainboard/google/cyan/spd/spd_util.h @@ -16,7 +16,10 @@ #ifndef SPD_UTIL_H #define SPD_UTIL_H +#include + uint8_t get_ramid(void); int get_variant_spd_index(int ram_id, int *dual); +void spd_memory_init_params(MEMORY_INIT_UPD *memory_params); #endif /* SPD_UTIL_H */ diff --git a/src/mainboard/google/cyan/variants/celes/devicetree.cb b/src/mainboard/google/cyan/variants/celes/devicetree.cb index 2e708af0d6..a1ab510810 100644 --- a/src/mainboard/google/cyan/variants/celes/devicetree.cb +++ b/src/mainboard/google/cyan/variants/celes/devicetree.cb @@ -73,12 +73,6 @@ chip soc/intel/braswell register "ISPEnable" = "0" # Disable IUNIT register "ISPPciDevConfig" = "3" register "PcdSdDetectChk" = "0" # Disable SD card detect - # Follow Intel recommendation to set BSW D-stepping PERPORTRXISET 2 (low strength) - register "D0Usb2Port0PerPortRXISet" = "2" - register "D0Usb2Port1PerPortRXISet" = "2" - register "D0Usb2Port2PerPortRXISet" = "2" - register "D0Usb2Port3PerPortRXISet" = "2" - register "D0Usb2Port4PerPortRXISet" = "2" # LPE audio codec settings register "lpe_codec_clk_src" = "LPE_CLK_SRC_XTAL" # 19.2MHz clock diff --git a/src/mainboard/google/cyan/variants/celes/ramstage.c b/src/mainboard/google/cyan/variants/celes/ramstage.c index 88b17f5da7..6c522a1d0c 100644 --- a/src/mainboard/google/cyan/variants/celes/ramstage.c +++ b/src/mainboard/google/cyan/variants/celes/ramstage.c @@ -19,29 +19,36 @@ void board_silicon_USB2_override(SILICON_INIT_UPD *params) { if (SocStepping() >= SocD0) { + //Follow Intel recommendation to set + //BSW D-stepping PERPORTRXISET 2 (low strength) params->Usb2Port0PerPortPeTxiSet = 7; params->Usb2Port0PerPortTxiSet = 0; params->Usb2Port0IUsbTxEmphasisEn = 3; params->Usb2Port0PerPortTxPeHalf = 1; + params->D0Usb2Port0PerPortRXISet = 2; params->Usb2Port1PerPortPeTxiSet = 7; params->Usb2Port1PerPortTxiSet = 0; params->Usb2Port1IUsbTxEmphasisEn = 3; params->Usb2Port1PerPortTxPeHalf = 1; + params->D0Usb2Port1PerPortRXISet = 2; params->Usb2Port2PerPortPeTxiSet = 7; params->Usb2Port2PerPortTxiSet = 6; params->Usb2Port2IUsbTxEmphasisEn = 3; params->Usb2Port2PerPortTxPeHalf = 1; + params->D0Usb2Port2PerPortRXISet = 2; params->Usb2Port3PerPortPeTxiSet = 7; params->Usb2Port3PerPortTxiSet = 6; params->Usb2Port3IUsbTxEmphasisEn = 3; params->Usb2Port3PerPortTxPeHalf = 1; + params->D0Usb2Port3PerPortRXISet = 2; params->Usb2Port4PerPortPeTxiSet = 7; params->Usb2Port4PerPortTxiSet = 6; params->Usb2Port4IUsbTxEmphasisEn = 3; params->Usb2Port4PerPortTxPeHalf = 1; + params->D0Usb2Port4PerPortRXISet = 2; } } diff --git a/src/mainboard/google/cyan/variants/kefka/Makefile.inc b/src/mainboard/google/cyan/variants/kefka/Makefile.inc index 5e94e715fa..7799e8d2b3 100644 --- a/src/mainboard/google/cyan/variants/kefka/Makefile.inc +++ b/src/mainboard/google/cyan/variants/kefka/Makefile.inc @@ -18,6 +18,7 @@ romstage-y += romstage.c romstage-y += spd_util.c ramstage-y += gpio.c +ramstage-y += ramstage.c SPD_BIN = $(obj)/spd.bin diff --git a/src/mainboard/google/cyan/variants/kefka/devicetree.cb b/src/mainboard/google/cyan/variants/kefka/devicetree.cb index 1ce056f32e..807dbcb2fe 100644 --- a/src/mainboard/google/cyan/variants/kefka/devicetree.cb +++ b/src/mainboard/google/cyan/variants/kefka/devicetree.cb @@ -80,13 +80,6 @@ chip soc/intel/braswell register "I2C5Frequency" = "1" register "I2C6Frequency" = "1" - # Follow Intel recommendation to set BSW D-stepping PERPORTRXISET 2 (low strength) - register "D0Usb2Port0PerPortRXISet" = "2" - register "D0Usb2Port1PerPortRXISet" = "2" - register "D0Usb2Port2PerPortRXISet" = "2" - register "D0Usb2Port3PerPortRXISet" = "2" - register "D0Usb2Port4PerPortRXISet" = "2" - # LPE audio codec settings register "lpe_codec_clk_src" = "LPE_CLK_SRC_XTAL" # 19.2MHz clock diff --git a/src/soc/intel/skylake/include/soc/pei_wrapper.h b/src/mainboard/google/cyan/variants/kefka/ramstage.c similarity index 53% rename from src/soc/intel/skylake/include/soc/pei_wrapper.h rename to src/mainboard/google/cyan/variants/kefka/ramstage.c index d53fe8b769..d790708cce 100644 --- a/src/soc/intel/skylake/include/soc/pei_wrapper.h +++ b/src/mainboard/google/cyan/variants/kefka/ramstage.c @@ -1,8 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. + * Copyright (C) 2014 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -14,14 +13,18 @@ * GNU General Public License for more details. */ -#ifndef _SOC_PEI_WRAPPER_H_ -#define _SOC_PEI_WRAPPER_H_ +#include -#include +void board_silicon_USB2_override(SILICON_INIT_UPD *params) +{ + if (SocStepping() >= SocD0) { -typedef int ABI_X86(*pei_wrapper_entry_t)(struct pei_data *pei_data); - -void soc_fill_pei_data(struct pei_data *pei_data); -void mainboard_fill_pei_data(struct pei_data *pei_data); - -#endif + //Follow Intel recommendation to set + //BSW D-stepping PERPORTRXISET 2 (low strength) + params->D0Usb2Port0PerPortRXISet = 2; + params->D0Usb2Port1PerPortRXISet = 2; + params->D0Usb2Port2PerPortRXISet = 2; + params->D0Usb2Port3PerPortRXISet = 2; + params->D0Usb2Port4PerPortRXISet = 2; + } +} diff --git a/src/mainboard/google/cyan/variants/relm/devicetree.cb b/src/mainboard/google/cyan/variants/relm/devicetree.cb index 65e662c5dd..e1bbb0ac5b 100644 --- a/src/mainboard/google/cyan/variants/relm/devicetree.cb +++ b/src/mainboard/google/cyan/variants/relm/devicetree.cb @@ -80,13 +80,6 @@ chip soc/intel/braswell register "I2C5Frequency" = "1" register "I2C6Frequency" = "1" - # Follow Intel recommendation to set BSW D-stepping PERPORTRXISET 2 (low strength) - register "D0Usb2Port0PerPortRXISet" = "2" - register "D0Usb2Port1PerPortRXISet" = "2" - register "D0Usb2Port2PerPortRXISet" = "2" - register "D0Usb2Port3PerPortRXISet" = "2" - register "D0Usb2Port4PerPortRXISet" = "2" - # LPE audio codec settings register "lpe_codec_clk_src" = "LPE_CLK_SRC_XTAL" # 19.2MHz clock diff --git a/src/mainboard/google/cyan/variants/relm/ramstage.c b/src/mainboard/google/cyan/variants/relm/ramstage.c index 27f9dfa241..3fbd2aebd9 100644 --- a/src/mainboard/google/cyan/variants/relm/ramstage.c +++ b/src/mainboard/google/cyan/variants/relm/ramstage.c @@ -36,5 +36,13 @@ void board_silicon_USB2_override(SILICON_INIT_UPD *params) params->Usb2Port3PerPortTxiSet = 0; params->Usb2Port3IUsbTxEmphasisEn = 2; params->Usb2Port3PerPortTxPeHalf = 1; + + //Follow Intel recommendation to set + //BSW D-stepping PERPORTRXISET 2 (low strength) + params->D0Usb2Port0PerPortRXISet = 2; + params->D0Usb2Port1PerPortRXISet = 2; + params->D0Usb2Port2PerPortRXISet = 2; + params->D0Usb2Port3PerPortRXISet = 2; + params->D0Usb2Port4PerPortRXISet = 2; } } diff --git a/src/mainboard/google/eve/spd/spd.c b/src/mainboard/google/eve/spd/spd.c index 2f365a7b5c..077bed4bf1 100644 --- a/src/mainboard/google/eve/spd/spd.c +++ b/src/mainboard/google/eve/spd/spd.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include diff --git a/src/mainboard/google/foster/pmic.c b/src/mainboard/google/foster/pmic.c index e3efd34529..13e2a4743f 100644 --- a/src/mainboard/google/foster/pmic.c +++ b/src/mainboard/google/foster/pmic.c @@ -34,10 +34,6 @@ struct max77620_init_reg { u8 delay; }; -static struct max77620_init_reg init_list[] = { - /* TODO */ -}; - static void pmic_write_reg(unsigned bus, uint8_t reg, uint8_t val, int delay) { if (i2c_writeb(bus, MAX77620_I2C_ADDR, reg, val)) { @@ -51,20 +47,8 @@ static void pmic_write_reg(unsigned bus, uint8_t reg, uint8_t val, int delay) } } -static void pmic_slam_defaults(unsigned bus) -{ - int i; - for (i = 0; i < ARRAY_SIZE(init_list); i++) { - struct max77620_init_reg *reg = &init_list[i]; - pmic_write_reg(bus, reg->reg, reg->val, reg->delay); - } -} - void pmic_init(unsigned bus) { - /* Restore PMIC POR defaults, in case kernel changed 'em */ - pmic_slam_defaults(bus); - /* Setup/Enable GPIO5 - VDD_CPU_REG_EN */ pmic_write_reg(bus, MAX77620_GPIO5_REG, 0x09, 1); diff --git a/src/mainboard/google/glados/romstage.c b/src/mainboard/google/glados/romstage.c index 81f0866dd6..47524c28ba 100644 --- a/src/mainboard/google/glados/romstage.c +++ b/src/mainboard/google/glados/romstage.c @@ -15,16 +15,16 @@ * GNU General Public License for more details. */ -#include +#include #include #include -#include -#include #include -#include "spd/spd.h" #include #include +#include "spd/spd_util.h" +#include "spd/spd.h" + void mainboard_romstage_entry(struct romstage_params *params) { #ifdef EC_ENABLE_KEYBOARD_BACKLIGHT @@ -32,18 +32,6 @@ void mainboard_romstage_entry(struct romstage_params *params) if (params->power_state->prev_sleep_state != ACPI_S3) google_chromeec_kbbacklight(25); #endif - /* Get SPD index */ - gpio_t spd_gpios[] = { - GPIO_MEM_CONFIG_0, - GPIO_MEM_CONFIG_1, - GPIO_MEM_CONFIG_2, - GPIO_MEM_CONFIG_3, - }; - params->pei_data->mem_cfg_id = - gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); - /* Fill out PEI DATA */ - mainboard_fill_pei_data(params->pei_data); - mainboard_fill_spd_data(params->pei_data); /* Initialize memory */ romstage_common(params); } @@ -51,26 +39,18 @@ void mainboard_romstage_entry(struct romstage_params *params) void mainboard_memory_init_params(struct romstage_params *params, MEMORY_INIT_UPD *memory_params) { - if (params->pei_data->spd_data[0][0][0] != 0) { - memory_params->MemorySpdPtr00 = - (UINT32)(params->pei_data->spd_data[0][0]); - memory_params->MemorySpdPtr10 = - (UINT32)(params->pei_data->spd_data[1][0]); - } - memcpy(memory_params->DqByteMapCh0, params->pei_data->dq_map[0], - sizeof(params->pei_data->dq_map[0])); - memcpy(memory_params->DqByteMapCh1, params->pei_data->dq_map[1], - sizeof(params->pei_data->dq_map[1])); - memcpy(memory_params->DqsMapCpu2DramCh0, params->pei_data->dqs_map[0], - sizeof(params->pei_data->dqs_map[0])); - memcpy(memory_params->DqsMapCpu2DramCh1, params->pei_data->dqs_map[1], - sizeof(params->pei_data->dqs_map[1])); - memcpy(memory_params->RcompResistor, params->pei_data->RcompResistor, - sizeof(params->pei_data->RcompResistor)); - memcpy(memory_params->RcompTarget, params->pei_data->RcompTarget, - sizeof(params->pei_data->RcompTarget)); + /* Get SPD index */ + const gpio_t spd_gpios[] = { + GPIO_MEM_CONFIG_0, + GPIO_MEM_CONFIG_1, + GPIO_MEM_CONFIG_2, + GPIO_MEM_CONFIG_3, + }; + const int spd_idx = gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); + memory_params->MemorySpdDataLen = SPD_LEN; memory_params->DqPinsInterleaved = FALSE; - if (CONFIG(BOARD_GOOGLE_CAROLINE)) - memory_params->DdrFreqLimit = 1600; + + spd_memory_init_params(memory_params, spd_idx); + variant_memory_init_params(memory_params, spd_idx); } diff --git a/src/mainboard/google/glados/spd/spd.c b/src/mainboard/google/glados/spd/spd.c index 391b702172..b3cf3f9416 100644 --- a/src/mainboard/google/glados/spd/spd.c +++ b/src/mainboard/google/glados/spd/spd.c @@ -19,10 +19,11 @@ #include #include #include -#include #include #include #include + +#include "spd_util.h" #include "spd.h" static void mainboard_print_spd_info(uint8_t spd[]) @@ -83,13 +84,11 @@ __weak int is_dual_channel(const int spd_index) } /* Copy SPD data for on-board memory */ -void mainboard_fill_spd_data(struct pei_data *pei_data) +void spd_memory_init_params(MEMORY_INIT_UPD *const memory_params, int spd_index) { - char *spd_file; + uint8_t *spd_file; size_t spd_file_len; - int spd_index; - spd_index = pei_data->mem_cfg_id; printk(BIOS_INFO, "SPD index %d\n", spd_index); /* Load SPD data from CBFS */ @@ -108,15 +107,15 @@ void mainboard_fill_spd_data(struct pei_data *pei_data) spd_index = 1; } - /* Assume same memory in both channels */ - spd_index *= SPD_LEN; - memcpy(pei_data->spd_data[0][0], spd_file + spd_index, SPD_LEN); - if (is_dual_channel(spd_index)) - memcpy(pei_data->spd_data[1][0], spd_file + spd_index, SPD_LEN); - + const size_t spd_offset = spd_index * SPD_LEN; /* Make sure a valid SPD was found */ - if (pei_data->spd_data[0][0][0] == 0) + if (spd_file[spd_offset] == 0) die("Invalid SPD data."); - mainboard_print_spd_info(pei_data->spd_data[0][0]); + /* Assume same memory in both channels */ + memory_params->MemorySpdPtr00 = (uintptr_t)spd_file + spd_offset; + if (is_dual_channel(spd_index)) + memory_params->MemorySpdPtr10 = memory_params->MemorySpdPtr00; + + mainboard_print_spd_info(spd_file + spd_offset); } diff --git a/src/soc/intel/braswell/include/soc/pei_wrapper.h b/src/mainboard/google/glados/spd/spd_util.h similarity index 62% rename from src/soc/intel/braswell/include/soc/pei_wrapper.h rename to src/mainboard/google/glados/spd/spd_util.h index 3222328bef..90dbd5ff98 100644 --- a/src/soc/intel/braswell/include/soc/pei_wrapper.h +++ b/src/mainboard/google/glados/spd/spd_util.h @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -13,14 +11,11 @@ * GNU General Public License for more details. */ -#ifndef _SOC_PEI_WRAPPER_H_ -#define _SOC_PEI_WRAPPER_H_ +#ifndef SPD_UTIL_H +#define SPD_UTIL_H -#include +#include -typedef int ABI_X86(*pei_wrapper_entry_t)(struct pei_data *pei_data); +void spd_memory_init_params(MEMORY_INIT_UPD *, int spd_index); -void broadwell_fill_pei_data(struct pei_data *pei_data); -void mainboard_fill_pei_data(struct pei_data *pei_data); - -#endif +#endif /* SPD_UTIL_H */ diff --git a/src/mainboard/google/glados/variants/asuka/variant.c b/src/mainboard/google/glados/variants/asuka/variant.c index 13cfe4fecd..4c778970fe 100644 --- a/src/mainboard/google/glados/variants/asuka/variant.c +++ b/src/mainboard/google/glados/variants/asuka/variant.c @@ -17,10 +17,10 @@ #include #include #include -#include -#include +#include -void mainboard_fill_pei_data(struct pei_data *pei_data) +void variant_memory_init_params( + MEMORY_INIT_UPD *const memory_params, const int spd_index) { /* DQ byte map */ const u8 dq_map[2][12] = { @@ -39,12 +39,14 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) /* Rcomp target */ const u16 RcompTarget[5] = { 100, 40, 40, 23, 40 }; - memcpy(pei_data->dq_map, dq_map, sizeof(dq_map)); - memcpy(pei_data->dqs_map, dqs_map, sizeof(dqs_map)); - memcpy(pei_data->RcompResistor, RcompResistor, - sizeof(RcompResistor)); - memcpy(pei_data->RcompTarget, RcompTarget, - sizeof(RcompTarget)); + memcpy(memory_params->DqByteMapCh0, dq_map, + sizeof(memory_params->DqByteMapCh0) * 2); + memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map, + sizeof(memory_params->DqsMapCpu2DramCh0) * 2); + memcpy(memory_params->RcompResistor, RcompResistor, + sizeof(memory_params->RcompResistor)); + memcpy(memory_params->RcompTarget, RcompTarget, + sizeof(memory_params->RcompTarget)); } int is_dual_channel(const int spd_index) diff --git a/src/mainboard/google/glados/variants/baseboard/include/baseboard/variant.h b/src/mainboard/google/glados/variants/baseboard/include/baseboard/variant.h index bbab7fc1f5..72eef684b8 100644 --- a/src/mainboard/google/glados/variants/baseboard/include/baseboard/variant.h +++ b/src/mainboard/google/glados/variants/baseboard/include/baseboard/variant.h @@ -15,7 +15,10 @@ #ifndef GLADOS_VARIANT_H #define GLADOS_VARIANT_H +#include + int is_dual_channel(const int spd_index); void mainboard_gpio_smi_sleep(void); +void variant_memory_init_params(MEMORY_INIT_UPD *memory_params, int spd_index); #endif /* GLADOS_VARIANT_H */ diff --git a/src/mainboard/google/glados/variants/caroline/variant.c b/src/mainboard/google/glados/variants/caroline/variant.c index a00eacf0ed..d61a538d56 100644 --- a/src/mainboard/google/glados/variants/caroline/variant.c +++ b/src/mainboard/google/glados/variants/caroline/variant.c @@ -15,14 +15,14 @@ */ #include +#include #include #include #include -#include -#include #include -void mainboard_fill_pei_data(struct pei_data *pei_data) +void variant_memory_init_params( + MEMORY_INIT_UPD *const memory_params, const int spd_index) { /* DQ byte map */ const u8 dq_map[2][12] = { @@ -41,12 +41,15 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) /* Rcomp target */ const u16 RcompTarget[5] = { 100, 40, 40, 23, 40 }; - memcpy(pei_data->dq_map, dq_map, sizeof(dq_map)); - memcpy(pei_data->dqs_map, dqs_map, sizeof(dqs_map)); - memcpy(pei_data->RcompResistor, RcompResistor, - sizeof(RcompResistor)); - memcpy(pei_data->RcompTarget, RcompTarget, - sizeof(RcompTarget)); + memcpy(memory_params->DqByteMapCh0, dq_map, + sizeof(memory_params->DqByteMapCh0) * 2); + memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map, + sizeof(memory_params->DqsMapCpu2DramCh0) * 2); + memcpy(memory_params->RcompResistor, RcompResistor, + sizeof(memory_params->RcompResistor)); + memcpy(memory_params->RcompTarget, RcompTarget, + sizeof(memory_params->RcompTarget)); + memory_params->DdrFreqLimit = 1600; } void mainboard_gpio_smi_sleep(void) diff --git a/src/mainboard/google/glados/variants/cave/variant.c b/src/mainboard/google/glados/variants/cave/variant.c index 2ce0a9001c..fc27fb4b61 100644 --- a/src/mainboard/google/glados/variants/cave/variant.c +++ b/src/mainboard/google/glados/variants/cave/variant.c @@ -15,14 +15,14 @@ */ #include +#include #include #include #include -#include -#include #include -void mainboard_fill_pei_data(struct pei_data *pei_data) +void variant_memory_init_params( + MEMORY_INIT_UPD *const memory_params, const int spd_index) { /* DQ byte map */ const u8 dq_map[2][12] = { @@ -41,12 +41,14 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) /* Rcomp target */ const u16 RcompTarget[5] = { 100, 40, 40, 23, 40 }; - memcpy(pei_data->dq_map, dq_map, sizeof(dq_map)); - memcpy(pei_data->dqs_map, dqs_map, sizeof(dqs_map)); - memcpy(pei_data->RcompResistor, RcompResistor, - sizeof(RcompResistor)); - memcpy(pei_data->RcompTarget, RcompTarget, - sizeof(RcompTarget)); + memcpy(memory_params->DqByteMapCh0, dq_map, + sizeof(memory_params->DqByteMapCh0) * 2); + memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map, + sizeof(memory_params->DqsMapCpu2DramCh0) * 2); + memcpy(memory_params->RcompResistor, RcompResistor, + sizeof(memory_params->RcompResistor)); + memcpy(memory_params->RcompTarget, RcompTarget, + sizeof(memory_params->RcompTarget)); } void mainboard_gpio_smi_sleep(void) diff --git a/src/mainboard/google/glados/variants/chell/variant.c b/src/mainboard/google/glados/variants/chell/variant.c index da83ed0f7d..2d1b363cab 100644 --- a/src/mainboard/google/glados/variants/chell/variant.c +++ b/src/mainboard/google/glados/variants/chell/variant.c @@ -15,14 +15,14 @@ */ #include +#include #include #include #include -#include -#include #include -void mainboard_fill_pei_data(struct pei_data *pei_data) +void variant_memory_init_params( + MEMORY_INIT_UPD *const memory_params, const int spd_index) { /* DQ byte map */ const u8 dq_map[2][12] = { @@ -41,12 +41,14 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) /* Rcomp target */ const u16 RcompTarget[5] = { 100, 40, 40, 23, 40 }; - memcpy(pei_data->dq_map, dq_map, sizeof(dq_map)); - memcpy(pei_data->dqs_map, dqs_map, sizeof(dqs_map)); - memcpy(pei_data->RcompResistor, RcompResistor, - sizeof(RcompResistor)); - memcpy(pei_data->RcompTarget, RcompTarget, - sizeof(RcompTarget)); + memcpy(memory_params->DqByteMapCh0, dq_map, + sizeof(memory_params->DqByteMapCh0) * 2); + memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map, + sizeof(memory_params->DqsMapCpu2DramCh0) * 2); + memcpy(memory_params->RcompResistor, RcompResistor, + sizeof(memory_params->RcompResistor)); + memcpy(memory_params->RcompTarget, RcompTarget, + sizeof(memory_params->RcompTarget)); } void mainboard_gpio_smi_sleep(void) diff --git a/src/mainboard/google/glados/variants/glados/variant.c b/src/mainboard/google/glados/variants/glados/variant.c index 2ce0a9001c..fc27fb4b61 100644 --- a/src/mainboard/google/glados/variants/glados/variant.c +++ b/src/mainboard/google/glados/variants/glados/variant.c @@ -15,14 +15,14 @@ */ #include +#include #include #include #include -#include -#include #include -void mainboard_fill_pei_data(struct pei_data *pei_data) +void variant_memory_init_params( + MEMORY_INIT_UPD *const memory_params, const int spd_index) { /* DQ byte map */ const u8 dq_map[2][12] = { @@ -41,12 +41,14 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) /* Rcomp target */ const u16 RcompTarget[5] = { 100, 40, 40, 23, 40 }; - memcpy(pei_data->dq_map, dq_map, sizeof(dq_map)); - memcpy(pei_data->dqs_map, dqs_map, sizeof(dqs_map)); - memcpy(pei_data->RcompResistor, RcompResistor, - sizeof(RcompResistor)); - memcpy(pei_data->RcompTarget, RcompTarget, - sizeof(RcompTarget)); + memcpy(memory_params->DqByteMapCh0, dq_map, + sizeof(memory_params->DqByteMapCh0) * 2); + memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map, + sizeof(memory_params->DqsMapCpu2DramCh0) * 2); + memcpy(memory_params->RcompResistor, RcompResistor, + sizeof(memory_params->RcompResistor)); + memcpy(memory_params->RcompTarget, RcompTarget, + sizeof(memory_params->RcompTarget)); } void mainboard_gpio_smi_sleep(void) diff --git a/src/mainboard/google/glados/variants/lars/variant.c b/src/mainboard/google/glados/variants/lars/variant.c index 4fe88ef7c8..cff0096291 100644 --- a/src/mainboard/google/glados/variants/lars/variant.c +++ b/src/mainboard/google/glados/variants/lars/variant.c @@ -17,8 +17,7 @@ #include #include #include -#include -#include +#include #define K4E6E304EB_MEM_ID 0x5 @@ -29,7 +28,8 @@ #define MEM_SINGLE_CHANB 0xb #define MEM_SINGLE_CHANC 0xc -void mainboard_fill_pei_data(struct pei_data *pei_data) +void variant_memory_init_params( + MEMORY_INIT_UPD *const params, const int spd_index) { /* DQ byte map */ const u8 dq_map[2][12] = { @@ -54,17 +54,18 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) /* Default Rcomp Target assignment */ const u16 *targeted_rcomp = RcompTarget; - memcpy(pei_data->dq_map, dq_map, sizeof(dq_map)); - memcpy(pei_data->dqs_map, dqs_map, sizeof(dqs_map)); - memcpy(pei_data->RcompResistor, RcompResistor, - sizeof(RcompResistor)); - /* Override Rcomp Target assignment for specific SKU(s) */ - if (pei_data->mem_cfg_id == K4E6E304EB_MEM_ID) + if (spd_index == K4E6E304EB_MEM_ID) targeted_rcomp = StrengthendRcompTarget; - memcpy(pei_data->RcompTarget, targeted_rcomp, - sizeof(pei_data->RcompTarget)); + memcpy(params->DqByteMapCh0, dq_map, + sizeof(params->DqByteMapCh0) * 2); + memcpy(params->DqsMapCpu2DramCh0, dqs_map, + sizeof(params->DqsMapCpu2DramCh0) * 2); + memcpy(params->RcompResistor, RcompResistor, + sizeof(params->RcompResistor)); + memcpy(params->RcompTarget, targeted_rcomp, + sizeof(params->RcompTarget)); } int is_dual_channel(const int spd_index) diff --git a/src/mainboard/google/glados/variants/sentry/variant.c b/src/mainboard/google/glados/variants/sentry/variant.c index 00f49fecf7..4c7fa23f08 100644 --- a/src/mainboard/google/glados/variants/sentry/variant.c +++ b/src/mainboard/google/glados/variants/sentry/variant.c @@ -17,12 +17,12 @@ #include #include #include -#include -#include +#include #define K4E6E304EE_MEM_ID 0x3 -void mainboard_fill_pei_data(struct pei_data *pei_data) +void variant_memory_init_params( + MEMORY_INIT_UPD *const memory_params, const int spd_index) { /* DQ byte map */ const u8 dq_map[2][12] = { @@ -47,15 +47,16 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) /* Default Rcomp Target assignment */ const u16 *targeted_rcomp = RcompTarget; - memcpy(pei_data->dq_map, dq_map, sizeof(dq_map)); - memcpy(pei_data->dqs_map, dqs_map, sizeof(dqs_map)); - memcpy(pei_data->RcompResistor, RcompResistor, - sizeof(RcompResistor)); - /* Override Rcomp Target assignment for specific SKU(s) */ - if (pei_data->mem_cfg_id == K4E6E304EE_MEM_ID) + if (spd_index == K4E6E304EE_MEM_ID) targeted_rcomp = StrengthendRcompTarget; - memcpy(pei_data->RcompTarget, targeted_rcomp, - sizeof(pei_data->RcompTarget)); + memcpy(memory_params->DqByteMapCh0, dq_map, + sizeof(memory_params->DqByteMapCh0) * 2); + memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map, + sizeof(memory_params->DqsMapCpu2DramCh0) * 2); + memcpy(memory_params->RcompResistor, RcompResistor, + sizeof(memory_params->RcompResistor)); + memcpy(memory_params->RcompTarget, targeted_rcomp, + sizeof(memory_params->RcompTarget)); } diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 07ae7d214e..09f792128c 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -64,7 +64,7 @@ config GBB_HWID depends on CHROMEOS default "HATCH TEST 1823" if BOARD_GOOGLE_HATCH default "HATCH_WHL TEST 2374" if BOARD_GOOGLE_HATCH_WHL - default "KOHAKU TEST 1953" if BOARD_GOOGLE_HATCH_WHL + default "KOHAKU TEST 1953" if BOARD_GOOGLE_KOHAKU config MAINBOARD_DIR string diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index 198d930aba..32526cc74b 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -30,8 +30,8 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI_INT(GPP_A6, NONE, PLTRST, LEVEL), /* A7 : PP3300_SOC_A */ PAD_NC(GPP_A7, NONE), - /* A8 : EMR_GARAGE_DET */ - PAD_CFG_GPI_GPIO_DRIVER(GPP_A8, NONE, DEEP), + /* A8 : PEN_GARAGE_DET_L */ + PAD_CFG_GPI_GPIO_DRIVER_SCI(GPP_A8, NONE, DEEP, LEVEL, NONE), /* A9 : ESPI_CLK */ /* A10 : FPMCU_PCH_BOOT1 */ PAD_CFG_GPO(GPP_A10, 0, DEEP), diff --git a/src/mainboard/google/hatch/variants/hatch/overridetree.cb b/src/mainboard/google/hatch/variants/hatch/overridetree.cb index 4b1b8d85f2..562bb8b229 100644 --- a/src/mainboard/google/hatch/variants/hatch/overridetree.cb +++ b/src/mainboard/google/hatch/variants/hatch/overridetree.cb @@ -78,15 +78,17 @@ chip soc/intel/cannonlake register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" - register "generic.reset_delay_ms" = "30" - register "generic.reset_off_delay_ms" = "3" + register "generic.reset_delay_ms" = "10" + register "generic.reset_off_delay_ms" = "1" register "generic.has_power_resource" = "1" register "hid_desc_reg_offset" = "0x01" device i2c 5d on end end chip drivers/generic/gpio_keys register "name" = ""PENH"" - register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_HIGH(GPP_A8)" + register "gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A8)" + register "key.wake" = "GPE0_DW0_08" + register "key.wakeup_event_action" = "EV_ACT_ASSERTED" register "key.dev_name" = ""EJCT"" register "key.linux_code" = "SW_PEN_INSERTED" register "key.linux_input_type" = "EV_SW" diff --git a/src/mainboard/google/hatch/variants/hatch_whl/overridetree.cb b/src/mainboard/google/hatch/variants/hatch_whl/overridetree.cb index c5d5964663..eec7880752 100644 --- a/src/mainboard/google/hatch/variants/hatch_whl/overridetree.cb +++ b/src/mainboard/google/hatch/variants/hatch_whl/overridetree.cb @@ -63,15 +63,17 @@ chip soc/intel/cannonlake register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" - register "generic.reset_delay_ms" = "30" - register "generic.reset_off_delay_ms" = "3" + register "generic.reset_delay_ms" = "10" + register "generic.reset_off_delay_ms" = "1" register "generic.has_power_resource" = "1" register "hid_desc_reg_offset" = "0x01" device i2c 5d on end end chip drivers/generic/gpio_keys register "name" = ""PENH"" - register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_HIGH(GPP_A8)" + register "gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A8)" + register "key.wake" = "GPE0_DW0_08" + register "key.wakeup_event_action" = "EV_ACT_ASSERTED" register "key.dev_name" = ""EJCT"" register "key.linux_code" = "SW_PEN_INSERTED" register "key.linux_input_type" = "EV_SW" diff --git a/src/mainboard/google/kahlee/mainboard.c b/src/mainboard/google/kahlee/mainboard.c index 1bf6c07045..ad979a567f 100644 --- a/src/mainboard/google/kahlee/mainboard.c +++ b/src/mainboard/google/kahlee/mainboard.c @@ -145,13 +145,13 @@ static void mainboard_init(void *chip_info) pm_write8(PM_PCIB_CFG, pm_read8(PM_PCIB_CFG) | PM_GENINT_DISABLE); /* Set low-power mode for BayHub eMMC bridge's PCIe clock. */ - clrsetbits_le32((uint32_t *)(MISC_MMIO_BASE + GPP_CLK_CNTRL), + clrsetbits_le32((uint32_t *)(ACPIMMIO_MISC_BASE + GPP_CLK_CNTRL), GPP_CLK2_REQ_MAP_MASK, GPP_CLK2_REQ_MAP_CLK_REQ2 << GPP_CLK2_REQ_MAP_SHIFT); /* Same for the WiFi */ - clrsetbits_le32((uint32_t *)(MISC_MMIO_BASE + GPP_CLK_CNTRL), + clrsetbits_le32((uint32_t *)(ACPIMMIO_MISC_BASE + GPP_CLK_CNTRL), GPP_CLK0_REQ_MAP_MASK, GPP_CLK0_REQ_MAP_CLK_REQ0 << GPP_CLK0_REQ_MAP_SHIFT); diff --git a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/audio.asl b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/audio.asl index 6bb41ae6b3..87890daf36 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/audio.asl +++ b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/audio.asl @@ -35,7 +35,7 @@ Device (I2S) Name (RBUF, ResourceTemplate () { // Memory resource is for MISC FCH register set. // It is needed for enabling the clock. - Memory32Fixed(ReadWrite, MISC_MMIO_BASE, 0x100) + Memory32Fixed(ReadWrite, ACPIMMIO_MISC_BASE, 0x100) }) Return (RBUF) diff --git a/src/mainboard/google/kahlee/variants/baseboard/spd/micron-MT40A512M16TB-062E-J.spd.hex b/src/mainboard/google/kahlee/variants/baseboard/spd/micron-MT40A512M16TB-062E-J.spd.hex index d4afea7263..67640fe849 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/spd/micron-MT40A512M16TB-062E-J.spd.hex +++ b/src/mainboard/google/kahlee/variants/baseboard/spd/micron-MT40A512M16TB-062E-J.spd.hex @@ -6,7 +6,7 @@ 16 36 0B 35 00 00 16 36 0B 35 16 36 0B 35 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 9C B5 00 00 00 00 E7 00 60 5B +00 00 00 00 00 00 9C B5 00 00 00 00 E7 00 30 53 0F 01 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/kukui/chromeos.c b/src/mainboard/google/kukui/chromeos.c index 44e75e29f0..35395014d6 100644 --- a/src/mainboard/google/kukui/chromeos.c +++ b/src/mainboard/google/kukui/chromeos.c @@ -27,6 +27,7 @@ void setup_chromeos_gpios(void) gpio_input_pullup(EC_IRQ); gpio_input_pullup(CR50_IRQ); gpio_output(GPIO_RESET, 0); + gpio_output(GPIO_EN_SPK_AMP, 0); } void fill_lb_gpios(struct lb_gpios *gpios) @@ -38,6 +39,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) {EC_IN_RW.id, ACTIVE_HIGH, -1, "EC in RW"}, {EC_IRQ.id, ACTIVE_LOW, -1, "EC interrupt"}, {CR50_IRQ.id, ACTIVE_HIGH, -1, "TPM interrupt"}, + {GPIO_EN_SPK_AMP.id, ACTIVE_HIGH, -1, "speaker enable"}, }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } diff --git a/src/mainboard/google/kukui/gpio.h b/src/mainboard/google/kukui/gpio.h index 92d238ece2..977acc3739 100644 --- a/src/mainboard/google/kukui/gpio.h +++ b/src/mainboard/google/kukui/gpio.h @@ -23,6 +23,7 @@ #define EC_IN_RW GPIO(PERIPHERAL_EN14) #define CR50_IRQ GPIO(PERIPHERAL_EN3) #define GPIO_RESET GPIO(PERIPHERAL_EN8) +#define GPIO_EN_SPK_AMP GPIO(PERIPHERAL_EN12) void setup_chromeos_gpios(void); diff --git a/src/mainboard/google/kukui/mainboard.c b/src/mainboard/google/kukui/mainboard.c index e1d8f5fb8d..40b8a49c61 100644 --- a/src/mainboard/google/kukui/mainboard.c +++ b/src/mainboard/google/kukui/mainboard.c @@ -16,6 +16,7 @@ #include #include #include +#include #include static void configure_emmc(void) @@ -37,10 +38,22 @@ static void configure_usb(void) setup_usb_host(); } +static void configure_audio(void) +{ + /* Audio PWR*/ + mtcmos_audio_power_on(); + + /* SoC I2S */ + gpio_set_mode(GPIO(CAM_RST0), PAD_CAM_RST0_FUNC_I2S2_LRCK); + gpio_set_mode(GPIO(CAM_PDN1), PAD_CAM_PDN1_FUNC_I2S2_BCK); + gpio_set_mode(GPIO(CAM_PDN0), PAD_CAM_PDN0_FUNC_I2S2_MCK); + gpio_set_mode(GPIO(EINT3), PAD_EINT3_FUNC_I2S3_DO); +} static void mainboard_init(struct device *dev) { configure_emmc(); configure_usb(); + configure_audio(); } static void mainboard_enable(struct device *dev) diff --git a/src/mainboard/google/kukui/romstage.c b/src/mainboard/google/kukui/romstage.c index 81ae9c538d..baaca43b90 100644 --- a/src/mainboard/google/kukui/romstage.c +++ b/src/mainboard/google/kukui/romstage.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include "early_init.h" @@ -28,6 +29,7 @@ void platform_romstage_main(void) mainboard_early_init(); mt6358_init(); + mt_pll_raise_ca53_freq(1989 * MHz); rtc_boot(); mt_mem_init(get_sdram_config()); mtk_mmu_after_dram(); diff --git a/src/mainboard/google/link/i915.c b/src/mainboard/google/link/i915.c index e09785d825..12d424cde0 100644 --- a/src/mainboard/google/link/i915.c +++ b/src/mainboard/google/link/i915.c @@ -25,19 +25,18 @@ #include #include #include -#include "onboard.h" -#include "ec.h" #include #include -#include #include #include - #include #include #include #include #include + +#include "ec.h" +#include "onboard.h" #include "i915io.h" enum { diff --git a/src/mainboard/google/octopus/romstage.c b/src/mainboard/google/octopus/romstage.c index 9d8b94d0b9..ff0354dc10 100644 --- a/src/mainboard/google/octopus/romstage.c +++ b/src/mainboard/google/octopus/romstage.c @@ -44,7 +44,7 @@ void mainboard_save_dimm_info(void) if (!CONFIG(DRAM_PART_NUM_ALWAYS_IN_CBI)) { /* Fall back on part numbers encoded in lp4cfg array. */ - if (board_id() < CONFIG_DRAM_PART_IN_CBI_BOARD_ID_MIN) { + if ((int)board_id() < CONFIG_DRAM_PART_IN_CBI_BOARD_ID_MIN) { save_dimm_info_by_sku_config(); return; } diff --git a/src/mainboard/google/octopus/variants/baseboard/memory.c b/src/mainboard/google/octopus/variants/baseboard/memory.c index aec2ba2a4f..fc7c87dcb2 100644 --- a/src/mainboard/google/octopus/variants/baseboard/memory.c +++ b/src/mainboard/google/octopus/variants/baseboard/memory.c @@ -210,7 +210,7 @@ const struct lpddr4_cfg *__weak variant_lpddr4_config(void) if (!CONFIG(DRAM_PART_NUM_ALWAYS_IN_CBI)) { /* Fall back non cbi memory config. */ - if (board_id() < CONFIG_DRAM_PART_IN_CBI_BOARD_ID_MIN) + if ((int)board_id() < CONFIG_DRAM_PART_IN_CBI_BOARD_ID_MIN) return &non_cbi_lp4cfg; } diff --git a/src/mainboard/google/poppy/Kconfig b/src/mainboard/google/poppy/Kconfig index 419b10eb3d..6bc8269aa7 100644 --- a/src/mainboard/google/poppy/Kconfig +++ b/src/mainboard/google/poppy/Kconfig @@ -10,6 +10,7 @@ config BOARD_GOOGLE_BASEBOARD_POPPY select EC_GOOGLE_CHROMEEC_LPC select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES + select INTEL_GMA_HAVE_VBT if BOARD_GOOGLE_NAMI select INTEL_LPSS_UART_FOR_CONSOLE select MAINBOARD_HAS_CHROMEOS select MAINBOARD_USES_FSP2_0 @@ -151,6 +152,7 @@ config VARIANT_SPECIFIC_OPTIONS_ATLAS select DRIVERS_I2C_MAX98373 select DRIVERS_I2C_DA7219 select DRIVERS_SPI_ACPI + select DRIVERS_USB_ACPI select EXCLUDE_NATIVE_SD_INTERFACE select MAINBOARD_HAS_SPI_TPM_CR50 select VARIANT_HAS_CAMERA_ACPI diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb index ad79bcab0e..1ea28a0e5f 100644 --- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -265,7 +265,30 @@ chip soc/intel/skylake device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device device pci 13.0 off end # Integrated Sensor Hub - device pci 14.0 on end # USB xHCI + device pci 14.0 on + chip drivers/usb/acpi + register "desc" = ""Root Hub"" + register "type" = "UPC_TYPE_HUB" + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""USB Type C Port 1"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + device usb 2.0 on end + end + chip drivers/usb/acpi + register "desc" = ""Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E2)" + device usb 2.2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB Type C Port 2"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + device usb 2.4 on end + end + end + end + end # USB xHCI device pci 14.1 on end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem device pci 15.0 on diff --git a/src/mainboard/google/poppy/variants/nami/Makefile.inc b/src/mainboard/google/poppy/variants/nami/Makefile.inc index dc80357835..0033c60ee7 100644 --- a/src/mainboard/google/poppy/variants/nami/Makefile.inc +++ b/src/mainboard/google/poppy/variants/nami/Makefile.inc @@ -43,3 +43,6 @@ oem.bin-file := $(call strip_quotes,$(CONFIG_OEM_BIN_FILE)) oem.bin-type := raw $(call add_vbt_to_cbfs, vbt-bard.bin, bard-data.vbt) +$(call add_vbt_to_cbfs, vbt-akali.bin, akali-data.vbt) +$(call add_vbt_to_cbfs, vbt-pantheon.bin, pantheon-data.vbt) +$(call add_vbt_to_cbfs, vbt-vayne.bin, vayne-data.vbt) diff --git a/src/mainboard/google/poppy/variants/nami/vbt-akali.bin b/src/mainboard/google/poppy/variants/nami/akali-data.vbt similarity index 100% rename from src/mainboard/google/poppy/variants/nami/vbt-akali.bin rename to src/mainboard/google/poppy/variants/nami/akali-data.vbt diff --git a/src/mainboard/google/poppy/variants/nami/data.vbt b/src/mainboard/google/poppy/variants/nami/data.vbt new file mode 100644 index 0000000000..84063621d0 Binary files /dev/null and b/src/mainboard/google/poppy/variants/nami/data.vbt differ diff --git a/src/mainboard/google/poppy/variants/nami/pantheon-data.vbt b/src/mainboard/google/poppy/variants/nami/pantheon-data.vbt new file mode 100644 index 0000000000..7e4fb0afe5 Binary files /dev/null and b/src/mainboard/google/poppy/variants/nami/pantheon-data.vbt differ diff --git a/src/mainboard/google/poppy/variants/nami/vayne-data.vbt b/src/mainboard/google/poppy/variants/nami/vayne-data.vbt new file mode 100644 index 0000000000..7e4fb0afe5 Binary files /dev/null and b/src/mainboard/google/poppy/variants/nami/vayne-data.vbt differ diff --git a/src/mainboard/google/sarien/Kconfig b/src/mainboard/google/sarien/Kconfig index c48a908dc1..e6d1f1f60f 100644 --- a/src/mainboard/google/sarien/Kconfig +++ b/src/mainboard/google/sarien/Kconfig @@ -16,7 +16,6 @@ config BOARD_GOOGLE_BASEBOARD_SARIEN select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_I2C_TPM_CR50 select MAINBOARD_HAS_TPM2 - select SOC_INTEL_COMMON_ACPI_EC_PTS_WAK select SOC_INTEL_WHISKEYLAKE select SOC_INTEL_COMMON_BLOCK_HDA_VERB select SOC_INTEL_COMMON_BLOCK_SMM_ESPI_DISABLE diff --git a/src/mainboard/google/sarien/dsdt.asl b/src/mainboard/google/sarien/dsdt.asl index e5b0ccad2e..58e0704deb 100644 --- a/src/mainboard/google/sarien/dsdt.asl +++ b/src/mainboard/google/sarien/dsdt.asl @@ -40,6 +40,8 @@ DefinitionBlock( #include #include } + /* Per board variant mainboard hooks. */ + #include } #if CONFIG(CHROMEOS) diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index cf64c4bb89..27c61f3563 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -37,10 +37,10 @@ chip soc/intel/cannonlake register "tdp_pl2_override" = "51" register "Device4Enable" = "1" register "AcousticNoiseMitigation" = "1" - register "SlowSlewRateForIa" = "0" - register "SlowSlewRateForGt" = "0" + register "SlowSlewRateForIa" = "2" + register "SlowSlewRateForGt" = "2" register "SlowSlewRateForSa" = "0" - register "SlowSlewRateForFivr" = "0" + register "SlowSlewRateForFivr" = "2" # Enable eDP device register "DdiPortEdp" = "1" # Enable HPD for DDI ports B/C @@ -161,7 +161,7 @@ chip soc/intel/cannonlake #| I2C4 | H1 TPM | #+-------------------+---------------------------+ - register "tcc_offset" = "10" + register "tcc_offset" = "1" register "common_soc_config" = "{ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, @@ -349,11 +349,15 @@ chip soc/intel/cannonlake device pci 1c.5 off end # PCI Express Port 6 device pci 1c.6 off end # PCI Express Port 7 device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 on end # PCI Express Port 9 + device pci 1d.0 on + smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "2230" "SlotDataBusWidth1X" + end # PCI Express Port 9 device pci 1d.1 on end # PCI Express Port 10 device pci 1d.2 on end # PCI Express Port 11 device pci 1d.3 off end # PCI Express Port 12 - device pci 1d.4 on end # PCI Express Port 13 (x4) + device pci 1d.4 on + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "2280" "SlotDataBusWidth4X" + end # PCI Express Port 13 (x4) device pci 1e.0 off end # UART #0 device pci 1e.1 off end # UART #1 device pci 1e.2 off end # GSPI #0 diff --git a/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/dptf.asl b/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/dptf.asl index 6fa06c7d73..4d380713e2 100644 --- a/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/dptf.asl @@ -13,14 +13,14 @@ * GNU General Public License for more details. */ -#define DPTF_CPU_PASSIVE 96 -#define DPTF_CPU_CRITICAL 103 +#define DPTF_CPU_PASSIVE 90 +#define DPTF_CPU_CRITICAL 105 /* Skin Sensor for CPU VR temperature monitor */ #define DPTF_TSR0_SENSOR_ID 1 #define DPTF_TSR0_SENSOR_NAME "Skin" -#define DPTF_TSR0_PASSIVE 56 -#define DPTF_TSR0_CRITICAL 108 +#define DPTF_TSR0_PASSIVE 60 +#define DPTF_TSR0_CRITICAL 105 /* Memory Sensor for DDR temperature monitor */ #define DPTF_TSR1_SENSOR_ID 2 @@ -31,24 +31,24 @@ /* M.2 Sensor for Ambient temperature monitor */ #define DPTF_TSR2_SENSOR_ID 3 #define DPTF_TSR2_SENSOR_NAME "Ambient" -#define DPTF_TSR2_PASSIVE 50 -#define DPTF_TSR2_CRITICAL 95 +#define DPTF_TSR2_PASSIVE 37 +#define DPTF_TSR2_CRITICAL 80 #undef DPTF_ENABLE_FAN_CONTROL #undef DPTF_ENABLE_CHARGER Name (DTRT, Package () { /* CPU Throttle Effect on CPU */ - Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 10, 0, 0, 0, 0 }, + Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 500, 100, 0, 0, 0, 0 }, /* CPU Throttle Effect on Skin (TSR0) */ - Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 }, + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 500, 30, 0, 0, 0, 0 }, /* CPU Throttle Effect on DDR (TSR1) */ - Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 90, 0, 0, 0, 0 }, + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 50, 2, 0, 0, 0 }, /* CPU Throttle Effect on Ambient (TSR2) */ - Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 }, + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 1000, 100, 1, 0, 0, 0 }, }) Name (MPPC, Package () diff --git a/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl b/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl new file mode 100644 index 0000000000..41121d28fe --- /dev/null +++ b/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define CAM_EN GPP_B11 /* Active low */ +#define TS_PD GPP_E7 + +/* Method called from LPIT prior to enter s0ix state */ +Method (MS0X, 1) +{ + If (Arg0) { + /* Turn off camera power */ + \_SB.PCI0.STXS (CAM_EN) + } Else { + /* Turn on camera power */ + \_SB.PCI0.CTXS (CAM_EN) + } +} + +/* Method called from _PTS prior to enter sleep state */ +Method (MPTS, 1) +{ + \_SB.PCI0.LPCB.EC0.PTS (Arg0) + + /* Clear touch screen pd pin to avoid leakage */ + \_SB.PCI0.CTXS (TS_PD) +} + +/* Method called from _WAK prior to wakeup */ +Method (MWAK, 1) +{ + \_SB.PCI0.LPCB.EC0.WAK (Arg0) +} diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index e9786f14eb..3807047e0f 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -378,11 +378,15 @@ chip soc/intel/cannonlake device pci 1c.5 off end # PCI Express Port 6 device pci 1c.6 off end # PCI Express Port 7 device pci 1c.7 on end # PCI Express Port 8 - device pci 1d.0 on end # PCI Express Port 9 + device pci 1d.0 on + smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "2230" "SlotDataBusWidth1X" + end # PCI Express Port 9 device pci 1d.1 on end # PCI Express Port 10 device pci 1d.2 off end # PCI Express Port 11 device pci 1d.3 off end # PCI Express Port 12 - device pci 1d.4 on end # PCI Express Port 13 (x4) + device pci 1d.4 on + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "2280" "SlotDataBusWidth4X" + end # PCI Express Port 13 (x4) device pci 1e.0 off end # UART #0 device pci 1e.1 off end # UART #1 device pci 1e.2 off end # GSPI #0 diff --git a/src/mainboard/google/sarien/variants/sarien/gpio.c b/src/mainboard/google/sarien/variants/sarien/gpio.c index 53a937ff39..ec3b44d4a3 100644 --- a/src/mainboard/google/sarien/variants/sarien/gpio.c +++ b/src/mainboard/google/sarien/variants/sarien/gpio.c @@ -31,9 +31,9 @@ static const struct pad_config gpio_table[] = { /* CLKOUT_LPC1 */ PAD_NC(GPP_A10, NONE), /* PME# */ PAD_NC(GPP_A11, NONE), /* BM_BUSY# */ PAD_NC(GPP_A12, NONE), -/* SUSWARN# */ PAD_CFG_GPO(GPP_A13, 0, DEEP), /* Card reader D3 cold */ + /* ESPI_RESET# */ -/* SUSACK# */ PAD_CFG_GPO(GPP_A15, 0, DEEP), /* Card reader D3 cold */ + /* SD_1P8_SEL */ PAD_NC(GPP_A16, NONE), /* SD_PWR_EN# */ PAD_NC(GPP_A17, NONE), /* ISH_GP0 */ PAD_NC(GPP_A18, NONE), @@ -224,9 +224,12 @@ static const struct pad_config gpio_table[] = { /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { -/* M2_SKT2_CFG0 */ PAD_CFG_GPO(GPP_H12, 0, DEEP), /* D3 cold RST */ +/* SUSWARN# */ PAD_CFG_GPO(GPP_A13, 0, DEEP), /* Card reader D3 cold */ +/* SUSACK# */ PAD_CFG_GPO(GPP_A15, 0, DEEP), /* Card reader D3 cold */ /* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVOTX_UART */ /* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVORX_UART */ +/* SSD RESET pin will stay low first */ +/* M2_SKT2_CFG0 */ PAD_CFG_GPO(GPP_H12, 0, DEEP), /* D3 cold RST */ /* I2C4_SDA */ PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), /* I2C_SDA_H1 */ /* I2C4_SCL */ PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), /* I2C_SCL_H1 */ /* DMIC_DATA1 */ PAD_CFG_GPI_APIC(GPP_D18, NONE, PLTRST, @@ -236,9 +239,8 @@ static const struct pad_config early_gpio_table[] = { /* CPU_GP0 */ PAD_CFG_GPI(GPP_E3, NONE, DEEP), /* MEM_INTERLEAVED */ /* SATALED# */ PAD_CFG_GPI(GPP_E8, NONE, DEEP), /* RECOVERY# */ /* DDPD_HPD2 */ PAD_CFG_GPI(GPP_E15, NONE, DEEP), /* H1_FLASH_WP */ -/* SSD RESET need to stay low first */ -/* M2_SKT2_CFG0 */ PAD_CFG_GPO(GPP_H12, 1, DEEP), /* D3 cold RST */ /* PWRBTN# */ PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), /* SIO_PWRBTN# */ +/* M2_SKT2_CFG0 */ PAD_CFG_GPO(GPP_H12, 1, DEEP), /* D3 cold RST */ }; const struct pad_config *variant_gpio_table(size_t *num) diff --git a/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl b/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl new file mode 100644 index 0000000000..41121d28fe --- /dev/null +++ b/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define CAM_EN GPP_B11 /* Active low */ +#define TS_PD GPP_E7 + +/* Method called from LPIT prior to enter s0ix state */ +Method (MS0X, 1) +{ + If (Arg0) { + /* Turn off camera power */ + \_SB.PCI0.STXS (CAM_EN) + } Else { + /* Turn on camera power */ + \_SB.PCI0.CTXS (CAM_EN) + } +} + +/* Method called from _PTS prior to enter sleep state */ +Method (MPTS, 1) +{ + \_SB.PCI0.LPCB.EC0.PTS (Arg0) + + /* Clear touch screen pd pin to avoid leakage */ + \_SB.PCI0.CTXS (TS_PD) +} + +/* Method called from _WAK prior to wakeup */ +Method (MWAK, 1) +{ + \_SB.PCI0.LPCB.EC0.WAK (Arg0) +} diff --git a/src/mainboard/google/smaug/pmic.c b/src/mainboard/google/smaug/pmic.c index d9dacb7d08..9add211ccd 100644 --- a/src/mainboard/google/smaug/pmic.c +++ b/src/mainboard/google/smaug/pmic.c @@ -36,10 +36,6 @@ struct max77620_init_reg { u8 delay; }; -static struct max77620_init_reg init_list[] = { - /* TODO */ -}; - static void pmic_write_reg(unsigned bus, uint8_t chip, uint8_t reg, uint8_t val, int delay) { @@ -66,20 +62,8 @@ static inline void pmic_write_reg_77621(unsigned bus, uint8_t reg, uint8_t val, pmic_write_reg(bus, MAX77621_CPU_I2C_ADDR, reg, val, delay); } -static void pmic_slam_defaults(unsigned bus) -{ - int i; - for (i = 0; i < ARRAY_SIZE(init_list); i++) { - struct max77620_init_reg *reg = &init_list[i]; - pmic_write_reg_77620(bus, reg->reg, reg->val, reg->delay); - } -} - void pmic_init(unsigned bus) { - /* Restore PMIC POR defaults, in case kernel changed 'em */ - pmic_slam_defaults(bus); - /* MAX77620: Set SD0 to 1.0V - VDD_CORE */ pmic_write_reg_77620(bus, MAX77620_SD0_REG, 0x20, 1); pmic_write_reg_77620(bus, MAX77620_VDVSSD0_REG, 0x20, 1); diff --git a/src/mainboard/google/stout/mainboard.c b/src/mainboard/google/stout/mainboard.c index 5f51a6b8bc..05de8cb63d 100644 --- a/src/mainboard/google/stout/mainboard.c +++ b/src/mainboard/google/stout/mainboard.c @@ -22,14 +22,14 @@ #include #include #include -#include "onboard.h" -#include "ec.h" #include -#include #include #include #include +#include "ec.h" +#include "onboard.h" + void mainboard_suspend_resume(void) { /* Stout EC needs to be put back in ACPI mode */ diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c index 7e3b7dba68..9cb1144b80 100644 --- a/src/mainboard/ibase/mb899/romstage.c +++ b/src/mainboard/ibase/mb899/romstage.c @@ -16,7 +16,6 @@ // __PRE_RAM__ means: use "unsigned" for device, not a struct. #include -#include #include #include #include diff --git a/src/mainboard/intel/dcp847ske/early_southbridge.c b/src/mainboard/intel/dcp847ske/early_southbridge.c index 46f9a94e9e..778525f320 100644 --- a/src/mainboard/intel/dcp847ske/early_southbridge.c +++ b/src/mainboard/intel/dcp847ske/early_southbridge.c @@ -17,7 +17,6 @@ */ #include -#include #include #include #include diff --git a/src/mainboard/intel/kblrvp/spd/spd_util.c b/src/mainboard/intel/kblrvp/spd/spd_util.c index 10043843a2..f22dcaa3b7 100644 --- a/src/mainboard/intel/kblrvp/spd/spd_util.c +++ b/src/mainboard/intel/kblrvp/spd/spd_util.c @@ -16,8 +16,6 @@ #include #include #include -#include -#include #include "../board_id.h" #include "spd.h" diff --git a/src/mainboard/intel/kunimitsu/Makefile.inc b/src/mainboard/intel/kunimitsu/Makefile.inc index dc4b83c0bb..3330a0aab8 100644 --- a/src/mainboard/intel/kunimitsu/Makefile.inc +++ b/src/mainboard/intel/kunimitsu/Makefile.inc @@ -18,8 +18,6 @@ subdirs-y += spd bootblock-y += bootblock_mainboard.c -romstage-y += pei_data.c - bootblock-$(CONFIG_CHROMEOS) += chromeos.c verstage-$(CONFIG_CHROMEOS) += chromeos.c romstage-$(CONFIG_CHROMEOS) += chromeos.c @@ -28,7 +26,6 @@ ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c ramstage-y += mainboard.c -ramstage-y += pei_data.c ramstage-y += ramstage.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c diff --git a/src/mainboard/intel/kunimitsu/pei_data.c b/src/mainboard/intel/kunimitsu/pei_data.c deleted file mode 100644 index bfc40c2748..0000000000 --- a/src/mainboard/intel/kunimitsu/pei_data.c +++ /dev/null @@ -1,29 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include "boardid.h" -#include "spd/spd.h" - -void mainboard_fill_pei_data(struct pei_data *pei_data) -{ - mainboard_fill_dq_map_data(&pei_data->dq_map); - mainboard_fill_dqs_map_data(&pei_data->dqs_map); - mainboard_fill_rcomp_res_data(&pei_data->RcompResistor); - mainboard_fill_rcomp_strength_data(&pei_data->RcompTarget); -} diff --git a/src/mainboard/intel/kunimitsu/romstage.c b/src/mainboard/intel/kunimitsu/romstage.c index 1c6f5a2cd3..f25f88b4dd 100644 --- a/src/mainboard/intel/kunimitsu/romstage.c +++ b/src/mainboard/intel/kunimitsu/romstage.c @@ -15,20 +15,13 @@ * GNU General Public License for more details. */ -#include #include -#include -#include #include #include "gpio.h" #include "spd/spd.h" void mainboard_romstage_entry(struct romstage_params *params) { - params->pei_data->mem_cfg_id = get_spd_index(); - /* Fill out PEI DATA */ - mainboard_fill_pei_data(params->pei_data); - mainboard_fill_spd_data(params->pei_data); /* Initialize memory */ romstage_common(params); } @@ -36,24 +29,11 @@ void mainboard_romstage_entry(struct romstage_params *params) void mainboard_memory_init_params(struct romstage_params *params, MEMORY_INIT_UPD *memory_params) { - if (params->pei_data->spd_data[0][0][0] != 0) { - memory_params->MemorySpdPtr00 = - (UINT32)(params->pei_data->spd_data[0][0]); - memory_params->MemorySpdPtr10 = - (UINT32)(params->pei_data->spd_data[1][0]); - } - memcpy(memory_params->DqByteMapCh0, params->pei_data->dq_map[0], - sizeof(params->pei_data->dq_map[0])); - memcpy(memory_params->DqByteMapCh1, params->pei_data->dq_map[1], - sizeof(params->pei_data->dq_map[1])); - memcpy(memory_params->DqsMapCpu2DramCh0, params->pei_data->dqs_map[0], - sizeof(params->pei_data->dqs_map[0])); - memcpy(memory_params->DqsMapCpu2DramCh1, params->pei_data->dqs_map[1], - sizeof(params->pei_data->dqs_map[1])); - memcpy(memory_params->RcompResistor, params->pei_data->RcompResistor, - sizeof(params->pei_data->RcompResistor)); - memcpy(memory_params->RcompTarget, params->pei_data->RcompTarget, - sizeof(params->pei_data->RcompTarget)); + spd_memory_init_params(memory_params); + mainboard_fill_dq_map_data(&memory_params->DqByteMapCh0); + mainboard_fill_dqs_map_data(&memory_params->DqsMapCpu2DramCh0); + mainboard_fill_rcomp_res_data(&memory_params->RcompResistor); + mainboard_fill_rcomp_strength_data(&memory_params->RcompTarget); memory_params->MemorySpdDataLen = SPD_LEN; memory_params->DqPinsInterleaved = FALSE; } diff --git a/src/mainboard/intel/kunimitsu/spd/spd.c b/src/mainboard/intel/kunimitsu/spd/spd.c index 8656d4bc17..bebb544a4d 100644 --- a/src/mainboard/intel/kunimitsu/spd/spd.c +++ b/src/mainboard/intel/kunimitsu/spd/spd.c @@ -16,8 +16,9 @@ #include #include -#include +#include #include +#include #include #include "spd.h" @@ -73,20 +74,19 @@ static void mainboard_print_spd_info(uint8_t spd[]) } } -/* Copy SPD data for on-board memory */ -void mainboard_fill_spd_data(struct pei_data *pei_data) +/* Fill SPD pointers for on-board memory */ +void spd_memory_init_params(MEMORY_INIT_UPD *memory_params) { uintptr_t spd_data; spd_data = mainboard_get_spd_data(); - memcpy(pei_data->spd_data[0][0], (void *)spd_data, SPD_LEN); - - if (mainboard_has_dual_channel_mem()) - memcpy(pei_data->spd_data[1][0], (void *)spd_data, SPD_LEN); - /* Make sure a valid SPD was found */ - if (pei_data->spd_data[0][0][0] == 0) + if (*(uint8_t *)spd_data == 0) die("Invalid SPD data."); - mainboard_print_spd_info(pei_data->spd_data[0][0]); + memory_params->MemorySpdPtr00 = spd_data; + if (mainboard_has_dual_channel_mem()) + memory_params->MemorySpdPtr10 = spd_data; + + mainboard_print_spd_info((uint8_t *)spd_data); } diff --git a/src/mainboard/intel/kunimitsu/spd/spd.h b/src/mainboard/intel/kunimitsu/spd/spd.h index f53c9ec9fa..22d371f4bc 100644 --- a/src/mainboard/intel/kunimitsu/spd/spd.h +++ b/src/mainboard/intel/kunimitsu/spd/spd.h @@ -16,6 +16,7 @@ #ifndef MAINBOARD_SPD_H +#include #include #include "../gpio.h" @@ -53,6 +54,7 @@ static inline int get_spd_index(void) { }; return (gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios))); } +void spd_memory_init_params(MEMORY_INIT_UPD *memory_params); void mainboard_fill_dq_map_data(void *dq_map_ptr); void mainboard_fill_dqs_map_data(void *dqs_map_ptr); void mainboard_fill_rcomp_res_data(void *rcomp_ptr); diff --git a/src/mainboard/intel/kunimitsu/spd/spd_util.c b/src/mainboard/intel/kunimitsu/spd/spd_util.c index fc0581cb24..b173628e29 100644 --- a/src/mainboard/intel/kunimitsu/spd/spd_util.c +++ b/src/mainboard/intel/kunimitsu/spd/spd_util.c @@ -17,8 +17,6 @@ #include #include #include -#include -#include #include "boardid.h" #include "spd.h" diff --git a/src/mainboard/intel/saddlebrook/Makefile.inc b/src/mainboard/intel/saddlebrook/Makefile.inc index 63889af078..683462b9de 100644 --- a/src/mainboard/intel/saddlebrook/Makefile.inc +++ b/src/mainboard/intel/saddlebrook/Makefile.inc @@ -17,6 +17,5 @@ subdirs-y += spd bootblock-y += bootblock.c -romstage-y += pei_data.c ramstage-y += ramstage.c diff --git a/src/mainboard/intel/saddlebrook/romstage.c b/src/mainboard/intel/saddlebrook/romstage.c index d19629cf9e..48d39db309 100644 --- a/src/mainboard/intel/saddlebrook/romstage.c +++ b/src/mainboard/intel/saddlebrook/romstage.c @@ -19,8 +19,6 @@ #include #include #include -#include -#include #include #include #include "spd/spd.h" @@ -38,8 +36,6 @@ void car_mainboard_pre_console_init(void) void mainboard_romstage_entry(struct romstage_params *params) { post_code(0x31); - /* Fill out PEI DATA */ - mainboard_fill_pei_data(params->pei_data); romstage_common(params); } @@ -67,18 +63,10 @@ void mainboard_memory_init_params( * should be set in the FSP flash image and should not need to be * changed. */ - memcpy(memory_params->DqByteMapCh0, params->pei_data->dq_map[0], - sizeof(params->pei_data->dq_map[0])); - memcpy(memory_params->DqByteMapCh1, params->pei_data->dq_map[1], - sizeof(params->pei_data->dq_map[1])); - memcpy(memory_params->DqsMapCpu2DramCh0, params->pei_data->dqs_map[0], - sizeof(params->pei_data->dqs_map[0])); - memcpy(memory_params->DqsMapCpu2DramCh1, params->pei_data->dqs_map[1], - sizeof(params->pei_data->dqs_map[1])); - memcpy(memory_params->RcompResistor, params->pei_data->RcompResistor, - sizeof(params->pei_data->RcompResistor)); - memcpy(memory_params->RcompTarget, params->pei_data->RcompTarget, - sizeof(params->pei_data->RcompTarget)); + mainboard_fill_dq_map_data(&memory_params->DqByteMapCh0); + mainboard_fill_dqs_map_data(&memory_params->DqsMapCpu2DramCh0); + mainboard_fill_rcomp_res_data(&memory_params->RcompResistor); + mainboard_fill_rcomp_strength_data(&memory_params->RcompTarget); /* update spd length*/ memory_params->MemorySpdDataLen = blk.len; diff --git a/src/mainboard/intel/saddlebrook/spd/spd_util.c b/src/mainboard/intel/saddlebrook/spd/spd_util.c index 2c26d787d7..5055d9a3af 100644 --- a/src/mainboard/intel/saddlebrook/spd/spd_util.c +++ b/src/mainboard/intel/saddlebrook/spd/spd_util.c @@ -15,8 +15,6 @@ #include #include -#include -#include #include "spd.h" void mainboard_fill_dq_map_data(void *dq_map_ptr) diff --git a/src/mainboard/intel/strago/acpi/mainboard.asl b/src/mainboard/intel/strago/acpi/mainboard.asl index 68ac133eec..1d5437bbf2 100644 --- a/src/mainboard/intel/strago/acpi/mainboard.asl +++ b/src/mainboard/intel/strago/acpi/mainboard.asl @@ -74,7 +74,7 @@ Scope (\_SB.PCI0.I2C1) Name (_UID, 5) Name (ISTP, 0) /* TouchScreen */ - Method(_CRS, 0x0, NotSerialized) + Method(_CRS, 0x0, Serialized) { Name (BUF0, ResourceTemplate () { @@ -120,7 +120,7 @@ Scope (\_SB.PCI0.I2C5) Name (_DDN, AUDIO_CODEC_DDN) Name (_UID, 1) - Method(_CRS, 0x0, NotSerialized) + Method(_CRS, 0x0, Serialized) { Name(SBUF,ResourceTemplate () { diff --git a/src/mainboard/intel/strago/romstage.c b/src/mainboard/intel/strago/romstage.c index 0f3067ea81..ba0ff7b85e 100644 --- a/src/mainboard/intel/strago/romstage.c +++ b/src/mainboard/intel/strago/romstage.c @@ -17,7 +17,6 @@ #include #include #include -#include #include "onboard.h" #include diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c index 3d01eb1e0f..b85bd6883d 100644 --- a/src/mainboard/kontron/986lcd-m/romstage.c +++ b/src/mainboard/kontron/986lcd-m/romstage.c @@ -16,7 +16,6 @@ /* __PRE_RAM__ means: use "unsigned" for device, not a struct. */ #include -#include #include #include #include diff --git a/src/mainboard/lenovo/t400/devicetree.cb b/src/mainboard/lenovo/t400/devicetree.cb index 8e90431d5f..475c45ebbd 100644 --- a/src/mainboard/lenovo/t400/devicetree.cb +++ b/src/mainboard/lenovo/t400/devicetree.cb @@ -109,6 +109,7 @@ chip northbridge/intel/gm45 end # PCIe Port #3 device pci 1c.3 on subsystemid 0x17aa 0x20f3 # Expresscard + smbios_slot_desc "7" "3" "ExpressCard Slot" "8" end # PCIe Port #4 device pci 1c.4 off end # PCIe Port #5 device pci 1c.5 off end # PCIe Port #6 diff --git a/src/mainboard/lenovo/t420/Kconfig b/src/mainboard/lenovo/t420/Kconfig index ce81907ccb..3d3b56ae22 100644 --- a/src/mainboard/lenovo/t420/Kconfig +++ b/src/mainboard/lenovo/t420/Kconfig @@ -28,6 +28,26 @@ config BOARD_SPECIFIC_OPTIONS # Workaround for EC/KBC IRQ1. select SERIRQ_CONTINUOUS_MODE +config VBOOT + select VBOOT_VBNV_CMOS + select GBB_FLAG_DISABLE_LID_SHUTDOWN + select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_FWMP + select HAS_RECOVERY_MRC_CACHE + +config VBOOT_SLOTS_RW_A + default y + +config VBOOT_VBNV_OFFSET + hex + default 0x2a + +config FMDFILE + string + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-rwa.fmd" if VBOOT + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/board.fmd" + config MAINBOARD_DIR string default lenovo/t420 diff --git a/src/mainboard/lenovo/t420/board.fmd b/src/mainboard/lenovo/t420/board.fmd new file mode 100644 index 0000000000..04cf827a87 --- /dev/null +++ b/src/mainboard/lenovo/t420/board.fmd @@ -0,0 +1,16 @@ +FLASH@0xff800000 0x800000 { + SI_ALL@0x0 0x500000 { + SI_DESC@0x0 0x1000 + SI_GBE@0x1000 0x2000 + SI_ME@0x3000 0x4ed000 + } + SI_BIOS@0x500000 0x300000 { + RW_MRC_CACHE@0 0x10000 + SMMSTORE(PRESERVE)@0x10000 0x40000 + + WP_RO@0x50000 0x2a0000 { + FMAP@0x0 0x800 + COREBOOT(CBFS)@0x1000 0x29f000 + } + } +} diff --git a/src/mainboard/lenovo/t420/cmos.layout b/src/mainboard/lenovo/t420/cmos.layout index f55c2037d5..a9f5f5ff47 100644 --- a/src/mainboard/lenovo/t420/cmos.layout +++ b/src/mainboard/lenovo/t420/cmos.layout @@ -81,6 +81,9 @@ entries 440 8 h 0 volume +# VBOOT +448 128 r 0 vbnv + # SandyBridge MRC Scrambler Seed values 896 32 r 0 mrc_scrambler_seed 928 32 r 0 mrc_scrambler_seed_s3 diff --git a/src/mainboard/lenovo/t420/devicetree.cb b/src/mainboard/lenovo/t420/devicetree.cb index 47c14ef909..c4092fe901 100644 --- a/src/mainboard/lenovo/t420/devicetree.cb +++ b/src/mainboard/lenovo/t420/devicetree.cb @@ -94,6 +94,7 @@ chip northbridge/intel/sandybridge device pci 1c.2 off end # PCIe Port #3 device pci 1c.3 on subsystemid 0x17aa 0x21ce + smbios_slot_desc "7" "3" "ExpressCard Slot" "8" end # PCIe Port #4 ExpressCard device pci 1c.4 on subsystemid 0x17aa 0x21ce diff --git a/src/mainboard/lenovo/t420/vboot-rwa.fmd b/src/mainboard/lenovo/t420/vboot-rwa.fmd new file mode 100644 index 0000000000..8a4cd3b477 --- /dev/null +++ b/src/mainboard/lenovo/t420/vboot-rwa.fmd @@ -0,0 +1,29 @@ +FLASH@0xff800000 0x800000 { + SI_ALL@0x0 0x500000 { + SI_DESC@0x0 0x1000 + SI_GBE@0x1000 0x2000 + SI_ME@0x3000 0x4ed000 + } + SI_BIOS@0x500000 0x300000 { + RW_SECTION_A@0x00000 0x180000 { + VBLOCK_A@0x0 0x10000 + FW_MAIN_A(CBFS)@0x10000 0x16ffc0 + RW_FWID_A@0x17ffc0 0x40 + } + UNIFIED_MRC_CACHE@0x180000 0x20000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x10000 + } + RW_VPD(PRESERVE)@0x1a0000 0x1000 + SMMSTORE(PRESERVE)@0x1a1000 0x40000 + + WP_RO@0x1e1000 0x11f000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_PADDING@0x840 0x7c0 + RO_VPD(PRESERVE)@0x1000 0x1000 + GBB@0x2000 0x1e000 + COREBOOT(CBFS)@0x20000 0xff000 + } + } +} diff --git a/src/mainboard/lenovo/t420s/Kconfig b/src/mainboard/lenovo/t420s/Kconfig index c5efb55653..1383d4166c 100644 --- a/src/mainboard/lenovo/t420s/Kconfig +++ b/src/mainboard/lenovo/t420s/Kconfig @@ -27,6 +27,26 @@ config BOARD_SPECIFIC_OPTIONS # Workaround for EC/KBC IRQ1. select SERIRQ_CONTINUOUS_MODE +config VBOOT + select VBOOT_VBNV_CMOS + select GBB_FLAG_DISABLE_LID_SHUTDOWN + select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_FWMP + select HAS_RECOVERY_MRC_CACHE + +config VBOOT_SLOTS_RW_A + default y + +config VBOOT_VBNV_OFFSET + hex + default 0x2a + +config FMDFILE + string + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-rwa.fmd" if VBOOT + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/board.fmd" + config MAINBOARD_DIR string default lenovo/t420s diff --git a/src/mainboard/lenovo/t420s/board.fmd b/src/mainboard/lenovo/t420s/board.fmd new file mode 100644 index 0000000000..04cf827a87 --- /dev/null +++ b/src/mainboard/lenovo/t420s/board.fmd @@ -0,0 +1,16 @@ +FLASH@0xff800000 0x800000 { + SI_ALL@0x0 0x500000 { + SI_DESC@0x0 0x1000 + SI_GBE@0x1000 0x2000 + SI_ME@0x3000 0x4ed000 + } + SI_BIOS@0x500000 0x300000 { + RW_MRC_CACHE@0 0x10000 + SMMSTORE(PRESERVE)@0x10000 0x40000 + + WP_RO@0x50000 0x2a0000 { + FMAP@0x0 0x800 + COREBOOT(CBFS)@0x1000 0x29f000 + } + } +} diff --git a/src/mainboard/lenovo/t420s/cmos.layout b/src/mainboard/lenovo/t420s/cmos.layout index 2be55f67c7..172191a59a 100644 --- a/src/mainboard/lenovo/t420s/cmos.layout +++ b/src/mainboard/lenovo/t420s/cmos.layout @@ -81,6 +81,9 @@ entries 440 8 h 0 volume +# VBOOT +448 128 r 0 vbnv + # SandyBridge MRC Scrambler Seed values 896 32 r 0 mrc_scrambler_seed 928 32 r 0 mrc_scrambler_seed_s3 diff --git a/src/mainboard/lenovo/t420s/devicetree.cb b/src/mainboard/lenovo/t420s/devicetree.cb index 0f09db8fa9..d1e3f75499 100644 --- a/src/mainboard/lenovo/t420s/devicetree.cb +++ b/src/mainboard/lenovo/t420s/devicetree.cb @@ -93,6 +93,7 @@ chip northbridge/intel/sandybridge device pci 1c.2 off end # PCIe Port #3 device pci 1c.3 on subsystemid 0x17aa 0x21d2 + smbios_slot_desc "7" "3" "ExpressCard Slot" "8" end # PCIe Port #4 ExpressCard device pci 1c.4 off end # PCIe Port #5 device pci 1c.5 off end # PCIe Port #6 Intel Gigabit Ethernet PHY (not PCIe) diff --git a/src/mainboard/lenovo/t420s/vboot-rwa.fmd b/src/mainboard/lenovo/t420s/vboot-rwa.fmd new file mode 100644 index 0000000000..8a4cd3b477 --- /dev/null +++ b/src/mainboard/lenovo/t420s/vboot-rwa.fmd @@ -0,0 +1,29 @@ +FLASH@0xff800000 0x800000 { + SI_ALL@0x0 0x500000 { + SI_DESC@0x0 0x1000 + SI_GBE@0x1000 0x2000 + SI_ME@0x3000 0x4ed000 + } + SI_BIOS@0x500000 0x300000 { + RW_SECTION_A@0x00000 0x180000 { + VBLOCK_A@0x0 0x10000 + FW_MAIN_A(CBFS)@0x10000 0x16ffc0 + RW_FWID_A@0x17ffc0 0x40 + } + UNIFIED_MRC_CACHE@0x180000 0x20000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x10000 + } + RW_VPD(PRESERVE)@0x1a0000 0x1000 + SMMSTORE(PRESERVE)@0x1a1000 0x40000 + + WP_RO@0x1e1000 0x11f000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_PADDING@0x840 0x7c0 + RO_VPD(PRESERVE)@0x1000 0x1000 + GBB@0x2000 0x1e000 + COREBOOT(CBFS)@0x20000 0xff000 + } + } +} diff --git a/src/mainboard/lenovo/t430/devicetree.cb b/src/mainboard/lenovo/t430/devicetree.cb index 9e731f9fbd..2731b69ec0 100644 --- a/src/mainboard/lenovo/t430/devicetree.cb +++ b/src/mainboard/lenovo/t430/devicetree.cb @@ -88,6 +88,7 @@ chip northbridge/intel/sandybridge end device pci 1c.2 on # PCIe Port #3 subsystemid 0x17aa 0x21f3 + smbios_slot_desc "7" "3" "ExpressCard Slot" "8" end device pci 1c.3 off # PCIe Port #4 end diff --git a/src/mainboard/lenovo/t430s/devicetree.cb b/src/mainboard/lenovo/t430s/devicetree.cb index 2ecf05ee43..21d54acf11 100644 --- a/src/mainboard/lenovo/t430s/devicetree.cb +++ b/src/mainboard/lenovo/t430s/devicetree.cb @@ -99,6 +99,7 @@ chip northbridge/intel/sandybridge end # PCIe Port #2 Integrated Wireless LAN device pci 1c.2 on subsystemid 0x17aa 0x21fb + smbios_slot_desc "7" "3" "ExpressCard Slot" "8" end # PCIe Port #3 ExpressCard device pci 1c.3 off end # PCIe Port #4 device pci 1c.4 off end # PCIe Port #5 diff --git a/src/mainboard/lenovo/t520/Kconfig b/src/mainboard/lenovo/t520/Kconfig index 06f296bc6d..ba17e8092b 100644 --- a/src/mainboard/lenovo/t520/Kconfig +++ b/src/mainboard/lenovo/t520/Kconfig @@ -27,6 +27,21 @@ config BOARD_LENOVO_BASEBOARD_T520 if BOARD_LENOVO_BASEBOARD_T520 +config VBOOT + select VBOOT_VBNV_CMOS + select GBB_FLAG_DISABLE_LID_SHUTDOWN + select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_FWMP + select HAS_RECOVERY_MRC_CACHE + +config VBOOT_SLOTS_RW_A + default y + +config VBOOT_VBNV_OFFSET + hex + default 0x2a + config VARIANT_DIR string default "t520" if BOARD_LENOVO_T520 @@ -40,6 +55,11 @@ config DEVICETREE string default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" +config FMDFILE + string + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-rwa.fmd" if VBOOT + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/board.fmd" + config MAINBOARD_PART_NUMBER string default "ThinkPad T520" if BOARD_LENOVO_T520 diff --git a/src/mainboard/lenovo/t520/board.fmd b/src/mainboard/lenovo/t520/board.fmd new file mode 100644 index 0000000000..04cf827a87 --- /dev/null +++ b/src/mainboard/lenovo/t520/board.fmd @@ -0,0 +1,16 @@ +FLASH@0xff800000 0x800000 { + SI_ALL@0x0 0x500000 { + SI_DESC@0x0 0x1000 + SI_GBE@0x1000 0x2000 + SI_ME@0x3000 0x4ed000 + } + SI_BIOS@0x500000 0x300000 { + RW_MRC_CACHE@0 0x10000 + SMMSTORE(PRESERVE)@0x10000 0x40000 + + WP_RO@0x50000 0x2a0000 { + FMAP@0x0 0x800 + COREBOOT(CBFS)@0x1000 0x29f000 + } + } +} diff --git a/src/mainboard/lenovo/t520/cmos.layout b/src/mainboard/lenovo/t520/cmos.layout index 1a7943e5a4..ec6ce858eb 100644 --- a/src/mainboard/lenovo/t520/cmos.layout +++ b/src/mainboard/lenovo/t520/cmos.layout @@ -81,6 +81,9 @@ entries #437 3 r 0 unused 440 8 h 0 volume +# VBOOT +448 128 r 0 vbnv + # SandyBridge MRC Scrambler Seed values 896 32 r 0 mrc_scrambler_seed 928 32 r 0 mrc_scrambler_seed_s3 diff --git a/src/mainboard/lenovo/t520/variants/t520/devicetree.cb b/src/mainboard/lenovo/t520/variants/t520/devicetree.cb index cf8e7ce1d2..eff2d69304 100644 --- a/src/mainboard/lenovo/t520/variants/t520/devicetree.cb +++ b/src/mainboard/lenovo/t520/variants/t520/devicetree.cb @@ -80,12 +80,16 @@ chip northbridge/intel/sandybridge device pci 1c.0 off end # PCIe Port #1 device pci 1c.1 on end # PCIe Port #2 Integrated Wireless LAN device pci 1c.2 off end # PCIe Port #3 - device pci 1c.3 on end # PCIe Port #4 Express Card + device pci 1c.3 on + smbios_slot_desc "7" "3" "ExpressCard Slot" "8" + end # PCIe Port #4 Express Card device pci 1c.4 on end # PCIe Port #5 MMC/SDXC + IEEE1394 device pci 1c.5 off end # PCIe Port #6 Intel Ethernet PHY device pci 1c.6 off end # PCIe Port #7 USB 3.0 only W520 device pci 1c.7 off end # PCIe Port #8 device pci 1d.0 on end # USB2 EHCI #1 + device pci 1e.0 off end # PCI-2-PCI bridge + device pci 1f.0 on #LPC bridge chip ec/lenovo/pmh7 device pnp ff.1 on # dummy @@ -165,6 +169,8 @@ chip northbridge/intel/sandybridge device i2c 5f on end end end # SMBus + device pci 1f.5 off end # IDE controller + device pci 1f.6 off end # Thermal controller end end end diff --git a/src/mainboard/lenovo/t520/variants/w520/devicetree.cb b/src/mainboard/lenovo/t520/variants/w520/devicetree.cb index 1770ad9722..ceca46ea84 100644 --- a/src/mainboard/lenovo/t520/variants/w520/devicetree.cb +++ b/src/mainboard/lenovo/t520/variants/w520/devicetree.cb @@ -80,7 +80,9 @@ chip northbridge/intel/sandybridge device pci 1c.0 off end # PCIe Port #1 device pci 1c.1 on end # PCIe Port #2 Integrated Wireless LAN device pci 1c.2 off end # PCIe Port #3 - device pci 1c.3 on end # PCIe Port #4 Express Card + device pci 1c.3 on + smbios_slot_desc "7" "3" "ExpressCard Slot" "8" + end # PCIe Port #4 Express Card device pci 1c.4 on end # PCIe Port #5 MMC/SDXC + IEEE1394 device pci 1c.5 off end # PCIe Port #6 Intel Ethernet PHY device pci 1c.6 on end # PCIe Port #7 USB 3.0 only W520 diff --git a/src/mainboard/lenovo/t520/vboot-rwa.fmd b/src/mainboard/lenovo/t520/vboot-rwa.fmd new file mode 100644 index 0000000000..8a4cd3b477 --- /dev/null +++ b/src/mainboard/lenovo/t520/vboot-rwa.fmd @@ -0,0 +1,29 @@ +FLASH@0xff800000 0x800000 { + SI_ALL@0x0 0x500000 { + SI_DESC@0x0 0x1000 + SI_GBE@0x1000 0x2000 + SI_ME@0x3000 0x4ed000 + } + SI_BIOS@0x500000 0x300000 { + RW_SECTION_A@0x00000 0x180000 { + VBLOCK_A@0x0 0x10000 + FW_MAIN_A(CBFS)@0x10000 0x16ffc0 + RW_FWID_A@0x17ffc0 0x40 + } + UNIFIED_MRC_CACHE@0x180000 0x20000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x10000 + } + RW_VPD(PRESERVE)@0x1a0000 0x1000 + SMMSTORE(PRESERVE)@0x1a1000 0x40000 + + WP_RO@0x1e1000 0x11f000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_PADDING@0x840 0x7c0 + RO_VPD(PRESERVE)@0x1000 0x1000 + GBB@0x2000 0x1e000 + COREBOOT(CBFS)@0x20000 0xff000 + } + } +} diff --git a/src/mainboard/lenovo/t530/variants/t530/devicetree.cb b/src/mainboard/lenovo/t530/variants/t530/devicetree.cb index 1a1e7075f2..335543a8f7 100644 --- a/src/mainboard/lenovo/t530/variants/t530/devicetree.cb +++ b/src/mainboard/lenovo/t530/variants/t530/devicetree.cb @@ -83,7 +83,9 @@ chip northbridge/intel/sandybridge device pci 1b.0 on end # High Definition Audio device pci 1c.0 on end # PCIe Port #1 device pci 1c.1 on end # PCIe Port #2 - device pci 1c.2 on end # PCIe Port #3 (expresscard) + device pci 1c.2 on + smbios_slot_desc "7" "3" "ExpressCard Slot" "8" + end # PCIe Port #3 (expresscard) device pci 1c.3 off end # PCIe Port #4 device pci 1c.4 off end # PCIe Port #5 device pci 1c.5 off end # PCIe Port #6 diff --git a/src/mainboard/lenovo/t530/variants/w530/devicetree.cb b/src/mainboard/lenovo/t530/variants/w530/devicetree.cb index 253096c316..0a80fa1d8c 100644 --- a/src/mainboard/lenovo/t530/variants/w530/devicetree.cb +++ b/src/mainboard/lenovo/t530/variants/w530/devicetree.cb @@ -98,6 +98,7 @@ chip northbridge/intel/sandybridge end device pci 1c.2 on # PCIe Port #3 subsystemid 0x17aa 0x21f6 + smbios_slot_desc "7" "3" "ExpressCard Slot" "8" end device pci 1c.3 off # PCIe Port #4 end diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c index ea207e80a9..0c7c0cfb2d 100644 --- a/src/mainboard/lenovo/t60/romstage.c +++ b/src/mainboard/lenovo/t60/romstage.c @@ -28,7 +28,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/lenovo/x200/devicetree.cb b/src/mainboard/lenovo/x200/devicetree.cb index d800e4fdfe..2ed4308cfa 100644 --- a/src/mainboard/lenovo/x200/devicetree.cb +++ b/src/mainboard/lenovo/x200/devicetree.cb @@ -113,6 +113,7 @@ chip northbridge/intel/gm45 end # PCIe Port #3 device pci 1c.3 on subsystemid 0x17aa 0x20f3 # Expresscard + smbios_slot_desc "7" "3" "ExpressCard Slot" "8" end # PCIe Port #4 device pci 1c.4 off end # PCIe Port #5 device pci 1c.5 off end # PCIe Port #6 diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/x201/devicetree.cb index fa33aeb431..6ece08bee6 100644 --- a/src/mainboard/lenovo/x201/devicetree.cb +++ b/src/mainboard/lenovo/x201/devicetree.cb @@ -92,7 +92,9 @@ chip northbridge/intel/nehalem device pci 1c.0 on end # PCIe Port #1 device pci 1c.1 on end # PCIe Port #2 (wwan) - device pci 1c.3 on end # PCIe Port #4 (Expresscard) + device pci 1c.3 on + smbios_slot_desc "7" "3" "ExpressCard Slot" "8" + end # PCIe Port #4 (Expresscard) device pci 1c.4 on end # PCIe Port #5 (wlan) device pci 1d.0 on # USB2 EHCI diff --git a/src/mainboard/lenovo/x220/Kconfig b/src/mainboard/lenovo/x220/Kconfig index 16f42e850e..358cf8ec39 100644 --- a/src/mainboard/lenovo/x220/Kconfig +++ b/src/mainboard/lenovo/x220/Kconfig @@ -26,6 +26,21 @@ config BOARD_SPECIFIC_OPTIONS # Workaround for EC/KBC IRQ1. select SERIRQ_CONTINUOUS_MODE +config VBOOT + select VBOOT_VBNV_CMOS + select GBB_FLAG_DISABLE_LID_SHUTDOWN + select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_FWMP + select HAS_RECOVERY_MRC_CACHE + +config VBOOT_SLOTS_RW_A + default y + +config VBOOT_VBNV_OFFSET + hex + default 0x2a + config MAINBOARD_DIR string default lenovo/x220 @@ -35,6 +50,10 @@ config VARIANT_DIR default "x220" if BOARD_LENOVO_X220 || BOARD_LENOVO_X220I default "x1" if BOARD_LENOVO_X1 +config FMDFILE + string + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-rwa.fmd" if VBOOT + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/board.fmd" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/lenovo/x220/board.fmd b/src/mainboard/lenovo/x220/board.fmd new file mode 100644 index 0000000000..04cf827a87 --- /dev/null +++ b/src/mainboard/lenovo/x220/board.fmd @@ -0,0 +1,16 @@ +FLASH@0xff800000 0x800000 { + SI_ALL@0x0 0x500000 { + SI_DESC@0x0 0x1000 + SI_GBE@0x1000 0x2000 + SI_ME@0x3000 0x4ed000 + } + SI_BIOS@0x500000 0x300000 { + RW_MRC_CACHE@0 0x10000 + SMMSTORE(PRESERVE)@0x10000 0x40000 + + WP_RO@0x50000 0x2a0000 { + FMAP@0x0 0x800 + COREBOOT(CBFS)@0x1000 0x29f000 + } + } +} diff --git a/src/mainboard/lenovo/x220/cmos.layout b/src/mainboard/lenovo/x220/cmos.layout index d4a4ed3371..dc98010ea2 100644 --- a/src/mainboard/lenovo/x220/cmos.layout +++ b/src/mainboard/lenovo/x220/cmos.layout @@ -80,6 +80,9 @@ entries #435 549 r 0 unused 440 8 h 0 volume +# VBOOT +448 128 r 0 vbnv + # SandyBridge MRC Scrambler Seed values 896 32 r 0 mrc_scrambler_seed 928 32 r 0 mrc_scrambler_seed_s3 diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb index 0ec66f59b8..360de04943 100644 --- a/src/mainboard/lenovo/x220/devicetree.cb +++ b/src/mainboard/lenovo/x220/devicetree.cb @@ -98,6 +98,7 @@ chip northbridge/intel/sandybridge end # PCIe Port #3 device pci 1c.3 on subsystemid 0x17aa 0x21db + smbios_slot_desc "7" "3" "ExpressCard Slot" "8" end # PCIe Port #4 device pci 1c.4 on subsystemid 0x17aa 0x21db diff --git a/src/mainboard/lenovo/x220/vboot-rwa.fmd b/src/mainboard/lenovo/x220/vboot-rwa.fmd new file mode 100644 index 0000000000..8a4cd3b477 --- /dev/null +++ b/src/mainboard/lenovo/x220/vboot-rwa.fmd @@ -0,0 +1,29 @@ +FLASH@0xff800000 0x800000 { + SI_ALL@0x0 0x500000 { + SI_DESC@0x0 0x1000 + SI_GBE@0x1000 0x2000 + SI_ME@0x3000 0x4ed000 + } + SI_BIOS@0x500000 0x300000 { + RW_SECTION_A@0x00000 0x180000 { + VBLOCK_A@0x0 0x10000 + FW_MAIN_A(CBFS)@0x10000 0x16ffc0 + RW_FWID_A@0x17ffc0 0x40 + } + UNIFIED_MRC_CACHE@0x180000 0x20000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x10000 + } + RW_VPD(PRESERVE)@0x1a0000 0x1000 + SMMSTORE(PRESERVE)@0x1a1000 0x40000 + + WP_RO@0x1e1000 0x11f000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_PADDING@0x840 0x7c0 + RO_VPD(PRESERVE)@0x1000 0x1000 + GBB@0x2000 0x1e000 + COREBOOT(CBFS)@0x20000 0xff000 + } + } +} diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb index 68e2f8ea2c..4687e9ccc3 100644 --- a/src/mainboard/lenovo/x230/devicetree.cb +++ b/src/mainboard/lenovo/x230/devicetree.cb @@ -110,6 +110,7 @@ chip northbridge/intel/sandybridge end # PCIe Port #2 device pci 1c.2 on subsystemid 0x17aa 0x21fa + smbios_slot_desc "7" "3" "ExpressCard Slot" "8" end # PCIe Port #3 (expresscard) device pci 1c.3 off end # PCIe Port #4 device pci 1c.4 off end # PCIe Port #5 diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c index 95192f733b..ea93707ce9 100644 --- a/src/mainboard/lenovo/x60/romstage.c +++ b/src/mainboard/lenovo/x60/romstage.c @@ -19,6 +19,7 @@ #include #include +#include #include #include #include @@ -28,7 +29,6 @@ #include #include #include -#include #include #include #include @@ -198,8 +198,7 @@ void mainboard_romstage_entry(unsigned long bist) if (MCHBAR16(SSKPD) == 0xCAFE) { printk(BIOS_DEBUG, "Soft reset detected, rebooting properly.\n"); - outb(0x6, 0xcf9); - halt(); + system_reset(); } /* Perform some early chipset initialization required diff --git a/src/mainboard/lenovo/z61t/romstage.c b/src/mainboard/lenovo/z61t/romstage.c index 0d68faca2c..47a52db39b 100644 --- a/src/mainboard/lenovo/z61t/romstage.c +++ b/src/mainboard/lenovo/z61t/romstage.c @@ -29,7 +29,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/msi/ms7707/Kconfig b/src/mainboard/msi/ms7707/Kconfig index 45ff73e57a..4923bbfdea 100644 --- a/src/mainboard/msi/ms7707/Kconfig +++ b/src/mainboard/msi/ms7707/Kconfig @@ -22,14 +22,6 @@ config MAINBOARD_PART_NUMBER string default "MS-7707" -config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID - hex - default 0x7707 - -config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID - hex - default 0x1462 - config DRAM_RESET_GATE_GPIO int default 60 diff --git a/src/mainboard/purism/librem_skl/Kconfig b/src/mainboard/purism/librem_skl/Kconfig index 965318f565..2372b9d280 100644 --- a/src/mainboard/purism/librem_skl/Kconfig +++ b/src/mainboard/purism/librem_skl/Kconfig @@ -19,11 +19,8 @@ config IRQ_SLOT_COUNT config VARIANT_DIR string - default "librem13v2" if BOARD_PURISM_LIBREM13_V2 - default "librem13v2" if BOARD_PURISM_LIBREM13_V3 - default "librem15v3" if BOARD_PURISM_LIBREM15_V3 - default "librem13v2" if BOARD_PURISM_LIBREM13_V4 - default "librem15v3" if BOARD_PURISM_LIBREM15_V4 + default "librem13v2" if BOARD_PURISM_LIBREM13_V2 || BOARD_PURISM_LIBREM13_V4 + default "librem15v3" if BOARD_PURISM_LIBREM15_V3 || BOARD_PURISM_LIBREM15_V4 config MAINBOARD_VENDOR string @@ -31,28 +28,16 @@ config MAINBOARD_VENDOR config MAINBOARD_FAMILY string - default "Librem 13" if BOARD_PURISM_LIBREM13_V2 - default "Librem 13" if BOARD_PURISM_LIBREM13_V3 - default "Librem 15" if BOARD_PURISM_LIBREM15_V3 - default "Librem 13" if BOARD_PURISM_LIBREM13_V4 - default "Librem 15" if BOARD_PURISM_LIBREM15_V4 + default "Librem 13" if BOARD_PURISM_LIBREM13_V2 || BOARD_PURISM_LIBREM13_V4 + default "Librem 15" if BOARD_PURISM_LIBREM15_V3 || BOARD_PURISM_LIBREM15_V4 config MAINBOARD_PART_NUMBER string default "Librem 13 v2" if BOARD_PURISM_LIBREM13_V2 - default "Librem 13 v2" if BOARD_PURISM_LIBREM13_V3 default "Librem 15 v3" if BOARD_PURISM_LIBREM15_V3 default "Librem 13 v4" if BOARD_PURISM_LIBREM13_V4 default "Librem 15 v4" if BOARD_PURISM_LIBREM15_V4 -config MAINBOARD_VERSION - string - default "2.0" if BOARD_PURISM_LIBREM13_V2 - default "3.0" if BOARD_PURISM_LIBREM13_V3 - default "3.0" if BOARD_PURISM_LIBREM15_V3 - default "4.0" if BOARD_PURISM_LIBREM13_V4 - default "4.0" if BOARD_PURISM_LIBREM15_V4 - config MAINBOARD_DIR string default "purism/librem_skl" @@ -67,11 +52,8 @@ config MAX_CPUS config VGA_BIOS_ID string - default "8086,1916" if BOARD_PURISM_LIBREM13_V2 - default "8086,1916" if BOARD_PURISM_LIBREM13_V3 - default "8086,1916" if BOARD_PURISM_LIBREM15_V3 - default "8086,5916" if BOARD_PURISM_LIBREM13_V4 - default "8086,5916" if BOARD_PURISM_LIBREM15_V4 + default "8086,1916" if BOARD_PURISM_LIBREM13_V2 || BOARD_PURISM_LIBREM15_V3 + default "8086,5916" if BOARD_PURISM_LIBREM13_V4 || BOARD_PURISM_LIBREM15_V4 config DIMM_MAX int @@ -81,14 +63,6 @@ config DIMM_SPD_SIZE int default 512 -config CPU_MICROCODE_CBFS_LEN - hex - default 0x18000 - -config CPU_MICROCODE_CBFS_LOC - hex - default 0xFFE115A0 - config CBFS_SIZE hex default 0xe00000 diff --git a/src/mainboard/purism/librem_skl/Kconfig.name b/src/mainboard/purism/librem_skl/Kconfig.name index 5b82de7435..b0dac3e338 100644 --- a/src/mainboard/purism/librem_skl/Kconfig.name +++ b/src/mainboard/purism/librem_skl/Kconfig.name @@ -1,9 +1,5 @@ config BOARD_PURISM_LIBREM13_V2 - bool "Librem 13 v2" - select BOARD_PURISM_BASEBOARD_LIBREM_SKL - -config BOARD_PURISM_LIBREM13_V3 - bool "Librem 13 v3" + bool "Librem 13 v2/v3" select BOARD_PURISM_BASEBOARD_LIBREM_SKL config BOARD_PURISM_LIBREM15_V3 diff --git a/src/mainboard/purism/librem_skl/Makefile.inc b/src/mainboard/purism/librem_skl/Makefile.inc index 5a7131f1ba..35f0f6cbde 100644 --- a/src/mainboard/purism/librem_skl/Makefile.inc +++ b/src/mainboard/purism/librem_skl/Makefile.inc @@ -13,8 +13,5 @@ ## GNU General Public License for more details. ## -romstage-y += pei_data.c - -ramstage-y += pei_data.c ramstage-y += ramstage.c ramstage-y += hda_verb.c diff --git a/src/mainboard/purism/librem_skl/pei_data.c b/src/mainboard/purism/librem_skl/pei_data.c deleted file mode 100644 index 0be917d3c7..0000000000 --- a/src/mainboard/purism/librem_skl/pei_data.c +++ /dev/null @@ -1,65 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Google Inc. - * Copyright (C) 2015 Intel Corporation - * Copyright (C) 2017 Purism SPC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include "pei_data.h" - -void mainboard_fill_dq_map_data(void *dq_map_ptr) -{ - /* DQ byte map */ - const u8 dq_map[2][12] = { - { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, - 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }, - { 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC, - 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } }; - memcpy(dq_map_ptr, dq_map, sizeof(dq_map)); -} - -void mainboard_fill_dqs_map_data(void *dqs_map_ptr) -{ - /* DQS CPU<>DRAM map */ - const u8 dqs_map[2][8] = { - { 0, 1, 3, 2, 4, 5, 6, 7 }, - { 1, 0, 4, 5, 2, 3, 6, 7 } }; - memcpy(dqs_map_ptr, dqs_map, sizeof(dqs_map)); -} - -void mainboard_fill_rcomp_res_data(void *rcomp_ptr) -{ - /* Rcomp resistor */ - const u16 RcompResistor[3] = { 121, 81, 100 }; - memcpy(rcomp_ptr, RcompResistor, - sizeof(RcompResistor)); -} - -void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr) -{ - /* Rcomp target */ - const u16 RcompTarget[5] = { 100, 40, 20, 20, 26 }; - memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget)); -} - -void mainboard_fill_pei_data(struct pei_data *pei_data) -{ - mainboard_fill_dq_map_data(&pei_data->dq_map); - mainboard_fill_dqs_map_data(&pei_data->dqs_map); - mainboard_fill_rcomp_res_data(&pei_data->RcompResistor); - mainboard_fill_rcomp_strength_data(&pei_data->RcompTarget); -} diff --git a/src/mainboard/purism/librem_skl/romstage.c b/src/mainboard/purism/librem_skl/romstage.c index 63d148a98e..faf4090ae1 100644 --- a/src/mainboard/purism/librem_skl/romstage.c +++ b/src/mainboard/purism/librem_skl/romstage.c @@ -19,7 +19,41 @@ #include #include #include -#include "pei_data.h" +#include + +static void mainboard_fill_dq_map_data(void *dq_map_ptr) +{ + /* DQ byte map */ + const u8 dq_map[2][12] = { + { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, + 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }, + { 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC, + 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } }; + memcpy(dq_map_ptr, dq_map, sizeof(dq_map)); +} + +static void mainboard_fill_dqs_map_data(void *dqs_map_ptr) +{ + /* DQS CPU<>DRAM map */ + const u8 dqs_map[2][8] = { + { 0, 1, 3, 2, 4, 5, 6, 7 }, + { 1, 0, 4, 5, 2, 3, 6, 7 } }; + memcpy(dqs_map_ptr, dqs_map, sizeof(dqs_map)); +} + +static void mainboard_fill_rcomp_res_data(void *rcomp_ptr) +{ + /* Rcomp resistor */ + const u16 RcompResistor[3] = { 121, 81, 100 }; + memcpy(rcomp_ptr, RcompResistor, sizeof(RcompResistor)); +} + +static void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr) +{ + /* Rcomp target */ + const u16 RcompTarget[5] = { 100, 40, 20, 20, 26 }; + memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget)); +} void mainboard_memory_init_params(FSPM_UPD *mupd) { diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c index e85da1f480..2bdad276c1 100644 --- a/src/mainboard/roda/rk886ex/romstage.c +++ b/src/mainboard/roda/rk886ex/romstage.c @@ -27,7 +27,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c index 0c2418ad27..f52091bced 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c @@ -23,6 +23,11 @@ #include #include #include +#include + +#define SD_CAP_BYP 0x810 +#define SD_CAP_BYP_EN 0x5A +#define SD_CAP_BYP_REG1 0x814 void variant_mainboard_final(void) { @@ -36,6 +41,21 @@ void variant_mainboard_final(void) cmd |= PCI_COMMAND_MASTER; pci_write_config16(dev, PCI_COMMAND, cmd); } + + /* Reduce SD-Card speed to DDR50 because of PCB constraints. */ + dev = pcidev_path_on_root(PCH_DEVFN_SDCARD); + if (dev) { + uint32_t reg; + struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (!res) + return; + + write32(res2mmio(res, SD_CAP_BYP, 0), SD_CAP_BYP_EN); + reg = read32(res2mmio(res, SD_CAP_BYP_REG1, 0)); + /* Disable HS400 and SDR104, keep SDR50 and DDR50 modes. */ + reg &= ~0x20005800; + write32(res2mmio(res, SD_CAP_BYP_REG1, 0), reg); + } } static void wait_for_legacy_dev(void *unused) diff --git a/src/northbridge/intel/gm45/early_reset.c b/src/northbridge/intel/gm45/early_reset.c index 9f919cfbcd..3f095a256f 100644 --- a/src/northbridge/intel/gm45/early_reset.c +++ b/src/northbridge/intel/gm45/early_reset.c @@ -16,8 +16,9 @@ #include #include +#include #include -#include + #include "gm45.h" void gm45_early_reset(void/*const timings_t *const timings*/) @@ -63,8 +64,5 @@ void gm45_early_reset(void/*const timings_t *const timings*/) /* Normally, we would set this after successful raminit. */ MCHBAR32(DCC_MCHBAR) |= (1 << 19); - /* Perform system reset through CF9 interface. */ - outb(0x02, 0xcf9); /* Set system reset bit. */ - outb(0x06, 0xcf9); /* Set CPU reset bit, too. */ - halt(); + system_reset(); } diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig index 8c1e0b18f7..e1067c5949 100644 --- a/src/northbridge/intel/haswell/Kconfig +++ b/src/northbridge/intel/haswell/Kconfig @@ -37,7 +37,7 @@ config HASWELL_VBOOT_IN_BOOTBLOCK Haswell can either start verstage in a separate stage right after the bootblock has run or it can start it after romstage for compatibility reasons. - Haswell however uses a mrc.bin to initialse memory which + Haswell however uses a mrc.bin to initialize memory which needs to be located at a fixed offset. Therefore even with a separate verstage starting after the bootblock that same binary is used meaning a jump is made from RW to the RO region diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c index fddada4ba0..96dc94e7d2 100644 --- a/src/northbridge/intel/haswell/raminit.c +++ b/src/northbridge/intel/haswell/raminit.c @@ -20,7 +20,6 @@ #include #include #include -#include #include #include #include diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index a9de844f15..84d9c105d6 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -21,7 +21,6 @@ #include #include #include -#include #include #include "i945.h" #include @@ -159,10 +158,10 @@ static void i945_setup_bars(void) printk(BIOS_DEBUG, "Setting up static southbridge registers..."); pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44, 0x80); /* ACPI_CNTL: Enable ACPI BAR */ + pci_write_config8(PCI_DEV(0, 0x1f, 0), ACPI_CNTL, ACPI_EN); pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIOBASE, DEFAULT_GPIOBASE | 1); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x4c, 0x10); /* GC: Enable GPIOs */ + pci_write_config8(PCI_DEV(0, 0x1f, 0), GPIO_CNTL, GPIO_EN); setup_pch_gpios(&mainboard_gpio_map); printk(BIOS_DEBUG, " done.\n"); diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index 1e8cf65581..74407c14ff 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -26,7 +26,6 @@ #include #include #include -#include #include "raminit.h" #include "i945.h" #include "chip.h" @@ -248,13 +247,13 @@ static void sdram_detect_errors(struct sys_info *sysinfo) u8 reg8; u8 do_reset = 0; - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2); if (reg8 & ((1<<7)|(1<<2))) { if (reg8 & (1<<2)) { printk(BIOS_DEBUG, "SLP S4# Assertion Width Violation.\n"); /* Write back clears bit 2 */ - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8); + pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2, reg8); do_reset = 1; } @@ -262,14 +261,14 @@ static void sdram_detect_errors(struct sys_info *sysinfo) if (reg8 & (1<<7)) { printk(BIOS_DEBUG, "DRAM initialization was interrupted.\n"); reg8 &= ~(1<<7); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8); + pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2, reg8); do_reset = 1; } /* Set SLP_S3# Assertion Stretch Enable */ - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); /* GEN_PMCON_3 */ + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3); reg8 |= (1 << 3); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); + pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8); if (do_reset) { printk(BIOS_DEBUG, "Reset required.\n"); @@ -278,9 +277,9 @@ static void sdram_detect_errors(struct sys_info *sysinfo) } /* Set DRAM initialization bit in ICH7 */ - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2); reg8 |= (1<<7); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8); + pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2, reg8); /* clear self refresh status if check is disabled or not a resume */ if (!CONFIG(CHECK_SLFRCS_ON_RESUME) @@ -1808,9 +1807,9 @@ static void sdram_program_memory_frequency(struct sys_info *sysinfo) */ goto cache_code; vco_update: - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2); reg8 &= ~(1 << 7); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8); + pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2, reg8); clkcfg &= ~(1 << 10); MCHBAR32(CLKCFG) = clkcfg; @@ -2814,9 +2813,9 @@ void sdram_initialize(int boot_path, const u8 *spd_addresses) sdram_enable_rcomp(); /* Tell ICH7 that we're done */ - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2); reg8 &= ~(1 << 7); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8); + pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2, reg8); printk(BIOS_DEBUG, "RAM initialization finished.\n"); diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c index 48bca36faa..144905fb92 100644 --- a/src/northbridge/intel/pineview/raminit.c +++ b/src/northbridge/intel/pineview/raminit.c @@ -15,6 +15,7 @@ */ #include +#include #include #include #include @@ -1744,10 +1745,8 @@ static void sdram_checkreset(void) } pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, pmcon2); pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, pmcon3); - if (reset) { - printk(BIOS_DEBUG, "Power cycle reset...\n"); - outb(0xe, 0xcf9); - } + if (reset) + full_reset(); } static void sdram_dradrb(struct sysinfo *s) diff --git a/src/northbridge/intel/pineview/romstage.c b/src/northbridge/intel/pineview/romstage.c index bdb685b252..a3e6c39172 100644 --- a/src/northbridge/intel/pineview/romstage.c +++ b/src/northbridge/intel/pineview/romstage.c @@ -23,7 +23,6 @@ #include #include #include -#include #include #include #include diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index cea3f2cd70..e60c37875b 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -25,7 +25,6 @@ #include #include #include -#include #include #include #include diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index cbbd2317ed..5347c5c493 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -23,7 +23,7 @@ #include #include #include -#include + #include "raminit_native.h" #include "raminit_common.h" #include "sandybridge.h" diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index a68ae49c7c..ea3590f78d 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -28,7 +28,6 @@ #include #include #include -#include #include #include "raminit.h" #include "pei_data.h" diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index 3fab3be85d..43316a2f22 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -47,10 +48,8 @@ void mainboard_romstage_entry(unsigned long bist) { int s3resume = 0; - if (MCHBAR16(SSKPD) == 0xCAFE) { - outb(0x6, 0xcf9); - halt (); - } + if (MCHBAR16(SSKPD) == 0xCAFE) + system_reset(); if (bist == 0) enable_lapic(); diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c index 4d5bdce9ac..60d3b55531 100644 --- a/src/northbridge/intel/x4x/raminit.c +++ b/src/northbridge/intel/x4x/raminit.c @@ -22,7 +22,6 @@ #include #include #include -#include #if CONFIG(SOUTHBRIDGE_INTEL_I82801GX) #include /* smbus_read_byte */ #else @@ -624,9 +623,7 @@ static void checkreset_ddr2(int boot_path) reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf0); pci_write_config8(PCI_DEV(0, 0, 0), 0xf0, reg8 | (1 << 2)); - printk(BIOS_DEBUG, "Reset...\n"); - outb(0xe, 0xcf9); - asm ("hlt"); + full_reset(); } pmcon2 |= 0x80; pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, pmcon2); diff --git a/src/security/tpm/tspi/tspi.c b/src/security/tpm/tspi/tspi.c index e466eb87aa..4698a4dc8c 100644 --- a/src/security/tpm/tspi/tspi.c +++ b/src/security/tpm/tspi/tspi.c @@ -22,6 +22,7 @@ #include #if CONFIG(VBOOT) #include +#include #include #endif diff --git a/src/security/vboot/antirollback.h b/src/security/vboot/antirollback.h index 6ea2c13a97..62d2e20f03 100644 --- a/src/security/vboot/antirollback.h +++ b/src/security/vboot/antirollback.h @@ -37,6 +37,7 @@ #include #include +#include struct vb2_context; enum vb2_pcr_digest; diff --git a/src/security/vboot/gbb.c b/src/security/vboot/gbb.c index 8f57c798b2..5293033666 100644 --- a/src/security/vboot/gbb.c +++ b/src/security/vboot/gbb.c @@ -13,17 +13,19 @@ * GNU General Public License for more details. */ +#define NEED_VB20_INTERNALS /* Peeking into vb2_gbb_header */ + #include #include #include -#include #include #include +#include #define GBB_FMAP_REGION_NAME "GBB" /* Copy of GBB header read from boot media. */ -static GoogleBinaryBlockHeader gbb_header; +static struct vb2_gbb_header gbb_header; /* * Read "GBB" region from SPI flash to obtain GBB header and validate @@ -45,13 +47,14 @@ static int gbb_init(void) return 1; if (rdev_readat(&gbb_rdev, &gbb_header, 0, - sizeof(GoogleBinaryBlockHeader)) != - sizeof(GoogleBinaryBlockHeader)) { + sizeof(struct vb2_gbb_header)) != + sizeof(struct vb2_gbb_header)) { printk(BIOS_ERR, "%s: Failure to read GBB header!\n", __func__); return 1; } - if (memcmp(gbb_header.signature, GBB_SIGNATURE, GBB_SIGNATURE_SIZE)) { + if (memcmp(gbb_header.signature, VB2_GBB_SIGNATURE, + VB2_GBB_SIGNATURE_SIZE)) { printk(BIOS_ERR, "%s: Signature check failed!\n", __func__); return 1; } diff --git a/src/security/vboot/gbb.h b/src/security/vboot/gbb.h index 550548d613..389242a3a2 100644 --- a/src/security/vboot/gbb.h +++ b/src/security/vboot/gbb.h @@ -18,7 +18,7 @@ #include -/* In order to use GBB_FLAG_* macros from vboot, include gbb_header.h. */ +/* In order to use VB2_GBB_FLAG_* macros from vboot, include vb2_api.h. */ /* * Read flags field from GBB header. diff --git a/src/security/vboot/misc.h b/src/security/vboot/misc.h index b4fae19d74..23159c8a0d 100644 --- a/src/security/vboot/misc.h +++ b/src/security/vboot/misc.h @@ -16,6 +16,8 @@ #ifndef __VBOOT_MISC_H__ #define __VBOOT_MISC_H__ +#include +#include #include struct vb2_context; @@ -65,14 +67,63 @@ int vboot_is_slot_selected(void); */ void vboot_fill_handoff(void); -/* - * Source: security/vboot/vboot_loader.c - */ -int vboot_logic_executed(void); - /* * Source: security/vboot/bootmode.c */ void vboot_save_recovery_reason_vbnv(void); +/* + * The stage loading code is compiled and entered from multiple stages. The + * helper functions below attempt to provide more clarity on when certain + * code should be called. They are implemented inline for better compile-time + * code elimination. + */ + +static inline int verification_should_run(void) +{ + if (CONFIG(VBOOT_SEPARATE_VERSTAGE)) + return ENV_VERSTAGE; + else if (CONFIG(VBOOT_STARTS_IN_ROMSTAGE)) + return ENV_ROMSTAGE; + else if (CONFIG(VBOOT_STARTS_IN_BOOTBLOCK)) + return ENV_BOOTBLOCK; + else + dead_code(); +} + +static inline int verstage_should_load(void) +{ + if (CONFIG(VBOOT_SEPARATE_VERSTAGE)) + return ENV_BOOTBLOCK; + else + return 0; +} + +static inline int vboot_logic_executed(void) +{ + extern int vboot_executed; /* should not be globally accessible */ + + /* If we are in the stage that runs verification, or in the stage that + both loads the verstage and is returned to from it afterwards, we + need to check a global to see if verfication has run. */ + if (verification_should_run() || + (verstage_should_load() && CONFIG(VBOOT_RETURN_FROM_VERSTAGE))) + return car_get_var(vboot_executed); + + if (CONFIG(VBOOT_STARTS_IN_BOOTBLOCK)) { + /* All other stages are "after the bootblock" */ + return !ENV_BOOTBLOCK; + } else if (CONFIG(VBOOT_STARTS_IN_ROMSTAGE)) { + /* Post-RAM stages are "after the romstage" */ +#ifdef __PRE_RAM__ + return 0; +#else + return 1; +#endif + } else { + dead_code(); + } +} + + #endif /* __VBOOT_MISC_H__ */ diff --git a/src/security/vboot/vboot_common.c b/src/security/vboot/vboot_common.c index 3dddc76556..14f154c438 100644 --- a/src/security/vboot/vboot_common.c +++ b/src/security/vboot/vboot_common.c @@ -18,12 +18,12 @@ #include #include #include -#include #include #include #include #include #include +#include int vboot_named_region_device(const char *name, struct region_device *rdev) { @@ -42,7 +42,7 @@ int vboot_can_enable_udc(void) if (!vboot_developer_mode_enabled()) return 0; /* Enable if GBB flag is set */ - if (gbb_is_flag_set(GBB_FLAG_ENABLE_UDC)) + if (gbb_is_flag_set(VB2_GBB_FLAG_ENABLE_UDC)) return 1; /* Enable if VBNV flag is set */ if (vbnv_udc_enable_flag()) @@ -85,7 +85,7 @@ static int vboot_get_handoff_flag(uint32_t flag) if (vboot_get_handoff_info((void **)&vbho, NULL)) return 0; - return !!(vbho->init_params.out_flags & flag); + return !!(vbho->out_flags & flag); } int vboot_handoff_check_developer_flag(void) diff --git a/src/security/vboot/vboot_common.h b/src/security/vboot/vboot_common.h index 768b29d4fc..9a02303d12 100644 --- a/src/security/vboot/vboot_common.h +++ b/src/security/vboot/vboot_common.h @@ -39,7 +39,8 @@ int vboot_check_recovery_request(void); * vboot shared data as well as the flags from VbInit. */ struct vboot_handoff { - VbInitParams init_params; + uint32_t reserved0; /* originally from VbInitParams */ + uint32_t out_flags; uint32_t selected_firmware; char shared_data[VB_SHARED_DATA_MIN_SIZE]; } __packed; diff --git a/src/security/vboot/vboot_handoff.c b/src/security/vboot/vboot_handoff.c index 178877d847..fccbdfc0b7 100644 --- a/src/security/vboot/vboot_handoff.c +++ b/src/security/vboot/vboot_handoff.c @@ -40,7 +40,7 @@ static void fill_vboot_handoff(struct vboot_handoff *vboot_handoff, { VbSharedDataHeader *vb_sd = (VbSharedDataHeader *)vboot_handoff->shared_data; - uint32_t *oflags = &vboot_handoff->init_params.out_flags; + uint32_t *oflags = &vboot_handoff->out_flags; vb_sd->flags |= VBSD_BOOT_FIRMWARE_VBOOT2; @@ -61,23 +61,18 @@ static void fill_vboot_handoff(struct vboot_handoff *vboot_handoff, vb_sd->flags |= VBSD_BOOT_REC_SWITCH_ON; *oflags |= VB_INIT_OUT_ENABLE_RECOVERY; *oflags |= VB_INIT_OUT_CLEAR_RAM; - *oflags |= VB_INIT_OUT_ENABLE_USB_STORAGE; } if (vb2_sd->flags & VB2_SD_FLAG_DEV_MODE_ENABLED) { *oflags |= VB_INIT_OUT_ENABLE_DEVELOPER; *oflags |= VB_INIT_OUT_CLEAR_RAM; - *oflags |= VB_INIT_OUT_ENABLE_USB_STORAGE; vb_sd->flags |= VBSD_BOOT_DEV_SWITCH_ON; vb_sd->flags |= VBSD_LF_DEV_SWITCH_ON; } - /* Inform vboot if the display was requested by vboot kernel phase - or enabled by dev/rec mode. */ + /* TODO(chromium:948529): Remove these two flags after downstream + vboot code longer reads them. */ if (vboot_wants_oprom() || vb2_sd->recovery_reason || - vb2_sd->flags & VB2_SD_FLAG_DEV_MODE_ENABLED) { - vboot_get_working_data()->flags |= VBOOT_WD_FLAG_DISPLAY_INIT; + vb2_sd->flags & VB2_SD_FLAG_DEV_MODE_ENABLED) vb_sd->flags |= VBSD_OPROM_LOADED; - } - /* TODO: Remove when depthcharge no longer reads this flag. */ if (CONFIG(VBOOT_MUST_REQUEST_DISPLAY)) vb_sd->flags |= VBSD_OPROM_MATTERS; diff --git a/src/security/vboot/vboot_loader.c b/src/security/vboot/vboot_loader.c index 0640ebd173..1350307425 100644 --- a/src/security/vboot/vboot_loader.c +++ b/src/security/vboot/vboot_loader.c @@ -36,53 +36,7 @@ _Static_assert(!CONFIG(VBOOT_RETURN_FROM_VERSTAGE) || CONFIG(VBOOT_SEPARATE_VERSTAGE), "return from verstage only makes sense for separate verstages"); -/* The stage loading code is compiled and entered from multiple stages. The - * helper functions below attempt to provide more clarity on when certain - * code should be called. */ - -static int verification_should_run(void) -{ - if (CONFIG(VBOOT_SEPARATE_VERSTAGE)) - return ENV_VERSTAGE; - else if (CONFIG(VBOOT_STARTS_IN_ROMSTAGE)) - return ENV_ROMSTAGE; - else if (CONFIG(VBOOT_STARTS_IN_BOOTBLOCK)) - return ENV_BOOTBLOCK; - else - die("impossible!"); -} - -static int verstage_should_load(void) -{ - if (CONFIG(VBOOT_SEPARATE_VERSTAGE)) - return ENV_BOOTBLOCK; - else - return 0; -} - -static int vboot_executed CAR_GLOBAL; - -int vboot_logic_executed(void) -{ - /* If we are in a stage that would load the verstage or execute the - vboot logic directly, we store the answer in a global. */ - if (verstage_should_load() || verification_should_run()) - return car_get_var(vboot_executed); - - if (CONFIG(VBOOT_STARTS_IN_BOOTBLOCK)) { - /* All other stages are "after the bootblock" */ - return !ENV_BOOTBLOCK; - } else if (CONFIG(VBOOT_STARTS_IN_ROMSTAGE)) { - /* Post-RAM stages are "after the romstage" */ -#ifdef __PRE_RAM__ - return 0; -#else - return 1; -#endif - } else { - die("impossible!"); - } -} +int vboot_executed CAR_GLOBAL; static void vboot_prepare(void) { diff --git a/src/security/vboot/vboot_logic.c b/src/security/vboot/vboot_logic.c index 2a8e619289..df34490f98 100644 --- a/src/security/vboot/vboot_logic.c +++ b/src/security/vboot/vboot_logic.c @@ -336,6 +336,10 @@ void verstage_main(void) if (CONFIG(VBOOT_LID_SWITCH) && !get_lid_switch()) ctx.flags |= VB2_CONTEXT_NOFAIL_BOOT; + /* Mainboard/SoC always initializes display. */ + if (!CONFIG(VBOOT_MUST_REQUEST_DISPLAY)) + ctx.flags |= VB2_CONTEXT_DISPLAY_INIT; + /* Do early init (set up secdata and NVRAM, load GBB) */ printk(BIOS_INFO, "Phase 1\n"); rv = vb2api_fw_phase1(&ctx); @@ -360,6 +364,11 @@ void verstage_main(void) vboot_reboot(); } + /* Is vboot declaring that display is available? If so, we should mark + it down, so that the mainboard/SoC knows to initialize display. */ + if (ctx.flags & VB2_CONTEXT_DISPLAY_INIT) + vboot_get_working_data()->flags |= VBOOT_WD_FLAG_DISPLAY_INIT; + /* Determine which firmware slot to boot (based on NVRAM) */ printk(BIOS_INFO, "Phase 2\n"); rv = vb2api_fw_phase2(&ctx); diff --git a/src/soc/amd/common/block/pi/agesawrapper.c b/src/soc/amd/common/block/pi/agesawrapper.c index 0570b5a3ee..5f58346625 100644 --- a/src/soc/amd/common/block/pi/agesawrapper.c +++ b/src/soc/amd/common/block/pi/agesawrapper.c @@ -41,8 +41,34 @@ static void *AcpiAlib; static void *AcpiIvrs; static void *AcpiCrat; +static AGESA_STATUS module_dispatch(AGESA_STRUCT_NAME func, + AMD_CONFIG_PARAMS *StdHeader) +{ + MODULE_ENTRY dispatcher = agesa_get_dispatcher(); + + if (!dispatcher) + return AGESA_UNSUPPORTED; + + StdHeader->Func = func; + return dispatcher(StdHeader); +} + +static AGESA_STATUS amd_dispatch(void *Params) +{ + AMD_CONFIG_PARAMS *StdHeader = Params; + return module_dispatch(StdHeader->Func, StdHeader); +} + +AGESA_STATUS amd_late_run_ap_task(AP_EXE_PARAMS *ApExeParams) +{ + AMD_CONFIG_PARAMS *StdHeader = (void *)ApExeParams; + return module_dispatch(AMD_LATE_RUN_AP_TASK, StdHeader); +} + static void *create_struct(AMD_INTERFACE_PARAMS *interface_struct) { + AMD_CONFIG_PARAMS *StdHeader; + /* Should clone entire StdHeader here. */ interface_struct->StdHeader.CalloutPtr = &GetBiosCallout; @@ -57,7 +83,9 @@ static void *create_struct(AMD_INTERFACE_PARAMS *interface_struct) if (!interface_struct->NewStructPtr) /* Avoid NULL pointer usage */ die("No AGESA structure created"); - return interface_struct->NewStructPtr; + StdHeader = interface_struct->NewStructPtr; + StdHeader->Func = interface_struct->AgesaFunctionName; + return StdHeader; } static AGESA_STATUS amd_init_reset(void) @@ -76,7 +104,7 @@ static AGESA_STATUS amd_init_reset(void) SetFchResetParams(&ResetParams->FchInterface); timestamp_add_now(TS_AGESA_INIT_RESET_START); - status = AmdInitReset(ResetParams); + status = amd_dispatch(ResetParams); timestamp_add_now(TS_AGESA_INIT_RESET_DONE); AmdReleaseStruct(&AmdParamStruct); @@ -97,7 +125,7 @@ static AGESA_STATUS amd_init_early(void) OemCustomizeInitEarly(EarlyParams); timestamp_add_now(TS_AGESA_INIT_EARLY_START); - status = AmdInitEarly(EarlyParams); + status = amd_dispatch(EarlyParams); timestamp_add_now(TS_AGESA_INIT_EARLY_DONE); AmdReleaseStruct(&AmdParamStruct); @@ -162,7 +190,7 @@ static AGESA_STATUS amd_init_post(void) ); timestamp_add_now(TS_AGESA_INIT_POST_START); - status = AmdInitPost(PostParams); + status = amd_dispatch(PostParams); timestamp_add_now(TS_AGESA_INIT_POST_DONE); /* @@ -205,7 +233,7 @@ static AGESA_STATUS amd_init_env(void) SetNbEnvParams(&EnvParams->GnbEnvConfiguration); timestamp_add_now(TS_AGESA_INIT_ENV_START); - status = AmdInitEnv(EnvParams); + status = amd_dispatch(EnvParams); timestamp_add_now(TS_AGESA_INIT_ENV_DONE); AmdReleaseStruct(&AmdParamStruct); @@ -256,7 +284,7 @@ static AGESA_STATUS amd_init_mid(void) SetNbMidParams(&MidParams->GnbMidConfiguration); timestamp_add_now(TS_AGESA_INIT_MID_START); - status = AmdInitMid(MidParams); + status = amd_dispatch(MidParams); timestamp_add_now(TS_AGESA_INIT_MID_DONE); AmdReleaseStruct(&AmdParamStruct); @@ -286,7 +314,7 @@ static AGESA_STATUS amd_init_late(void) } timestamp_add_now(TS_AGESA_INIT_LATE_START); - Status = AmdInitLate(LateParams); + Status = amd_dispatch(LateParams); timestamp_add_now(TS_AGESA_INIT_LATE_DONE); DmiTable = LateParams->DmiTable; @@ -309,11 +337,6 @@ static AGESA_STATUS amd_init_late(void) return Status; } -AGESA_STATUS amd_late_run_ap_task(AP_EXE_PARAMS *ApExeParams) -{ - return AmdLateRunApTask(ApExeParams); -} - static AGESA_STATUS amd_init_rtb(void) { AGESA_STATUS Status; @@ -325,7 +348,7 @@ static AGESA_STATUS amd_init_rtb(void) AMD_RTB_PARAMS *RtbParams = create_struct(&AmdParamStruct); timestamp_add_now(TS_AGESA_INIT_RTB_START); - Status = AmdInitRtb(RtbParams); + Status = amd_dispatch(RtbParams); timestamp_add_now(TS_AGESA_INIT_RTB_DONE); if (save_s3_info(RtbParams->S3DataBlock.NvStorage, @@ -354,7 +377,7 @@ static AGESA_STATUS amd_init_resume(void) InitResumeParams->S3DataBlock.NvStorageSize = nv_size; timestamp_add_now(TS_AGESA_INIT_RESUME_START); - status = AmdInitResume(InitResumeParams); + status = amd_dispatch(InitResumeParams); timestamp_add_now(TS_AGESA_INIT_RESUME_DONE); AmdReleaseStruct(&AmdParamStruct); @@ -382,7 +405,7 @@ static AGESA_STATUS amd_s3late_restore(void) S3LateParams->S3DataBlock.VolatileStorageSize = vol_size; timestamp_add_now(TS_AGESA_S3_LATE_START); - Status = AmdS3LateRestore(S3LateParams); + Status = amd_dispatch(S3LateParams); timestamp_add_now(TS_AGESA_S3_LATE_DONE); AmdReleaseStruct(&AmdParamStruct); @@ -408,7 +431,7 @@ static AGESA_STATUS amd_s3final_restore(void) S3FinalParams->S3DataBlock.VolatileStorageSize = vol_size; timestamp_add_now(TS_AGESA_S3_FINAL_START); - Status = AmdS3FinalRestore(S3FinalParams); + Status = amd_dispatch(S3FinalParams); timestamp_add_now(TS_AGESA_S3_FINAL_DONE); AmdReleaseStruct(&AmdParamStruct); diff --git a/src/soc/amd/stoneyridge/acpi/gpio_lib.asl b/src/soc/amd/stoneyridge/acpi/gpio_lib.asl index d18b147d71..8185c35ac5 100644 --- a/src/soc/amd/stoneyridge/acpi/gpio_lib.asl +++ b/src/soc/amd/stoneyridge/acpi/gpio_lib.asl @@ -19,7 +19,7 @@ Method (GPAD, 0x1) { /* Arg0 - GPIO pin number */ - Return (Add(Multiply(Arg0, 4), GPIO_CONTROL_MMIO_BASE)) + Return (Add(Multiply(Arg0, 4), ACPIMMIO_GPIO0_BASE)) } /* Read pin control dword */ diff --git a/src/soc/amd/stoneyridge/acpi/sb_fch.asl b/src/soc/amd/stoneyridge/acpi/sb_fch.asl index 114401e24b..4c1196dad6 100644 --- a/src/soc/amd/stoneyridge/acpi/sb_fch.asl +++ b/src/soc/amd/stoneyridge/acpi/sb_fch.asl @@ -144,7 +144,7 @@ Device (MISC) Name (_HID, "AMD0040") Name (_UID, 0x3) Name (_CRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, MISC_MMIO_BASE, 0x100) + Memory32Fixed(ReadWrite, ACPIMMIO_MISC_BASE, 0x100) }) Method (_STA, 0x0, NotSerialized) { diff --git a/src/soc/amd/stoneyridge/enable_usbdebug.c b/src/soc/amd/stoneyridge/enable_usbdebug.c index ce84a47929..90bd6e8f33 100644 --- a/src/soc/amd/stoneyridge/enable_usbdebug.c +++ b/src/soc/amd/stoneyridge/enable_usbdebug.c @@ -26,10 +26,7 @@ pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx) { - /* Enable all of the USB controllers */ - outb(PM_USB_ENABLE, PM_INDEX); - outb(PM_USB_ALL_CONTROLLERS, PM_DATA); - + pm_io_write8(PM_USB_ENABLE, PM_USB_ALL_CONTROLLERS); return SOC_EHCI1_DEV; } diff --git a/src/soc/amd/stoneyridge/gpio.c b/src/soc/amd/stoneyridge/gpio.c index da1ba0bb74..285fedd238 100644 --- a/src/soc/amd/stoneyridge/gpio.c +++ b/src/soc/amd/stoneyridge/gpio.c @@ -221,14 +221,13 @@ uint16_t gpio_acpi_pin(gpio_t gpio) void sb_program_gpios(const struct soc_amd_gpio *gpio_list_ptr, size_t size) { - uint8_t *mux_ptr; uint32_t *gpio_ptr, *inter_master; uint32_t control, control_flags, edge_level, direction; uint32_t mask, bit_edge, bit_level; uint8_t mux, index, gpio; int gevent_num; - inter_master = (uint32_t *)(uintptr_t)(GPIO_CONTROL_MMIO_BASE + inter_master = (uint32_t *)(uintptr_t)(ACPIMMIO_GPIO0_BASE + GPIO_MASTER_SWITCH); direction = 0; edge_level = 0; @@ -252,9 +251,8 @@ void sb_program_gpios(const struct soc_amd_gpio *gpio_list_ptr, size_t size) control = gpio_list_ptr[index].control; control_flags = gpio_list_ptr[index].flags; - mux_ptr = (uint8_t *)(uintptr_t)(gpio + GPIO_IOMUX_MMIO_BASE); - write8(mux_ptr, mux & AMD_GPIO_MUX_MASK); - read8(mux_ptr); /* Flush posted write */ + iomux_write8(gpio, mux & AMD_GPIO_MUX_MASK); + iomux_read8(gpio); /* Flush posted write */ /* special case if pin 2 is assigned to wake */ if ((gpio == 2) && !(mux & AMD_GPIO_MUX_MASK)) route_sci(GPIO_2_EVENT); @@ -316,11 +314,13 @@ void sb_program_gpios(const struct soc_amd_gpio *gpio_list_ptr, size_t size) mem_read_write32(inter_master, GPIO_INTERRUPT_EN, GPIO_INTERRUPT_EN); /* Set all SCI trigger direction (high/low) */ - mem_read_write32((uint32_t *)(uintptr_t)(APU_SMI_BASE + SMI_SCI_TRIG), + mem_read_write32((uint32_t *) + (uintptr_t)(ACPIMMIO_SMI_BASE + SMI_SCI_TRIG), direction, mask); /* Set all SCI trigger level (edge/level) */ - mem_read_write32((uint32_t *)(uintptr_t)(APU_SMI_BASE + SMI_SCI_LEVEL), + mem_read_write32((uint32_t *) + (uintptr_t)(ACPIMMIO_SMI_BASE + SMI_SCI_LEVEL), edge_level, mask); } @@ -346,11 +346,9 @@ static void save_i2c_pin_registers(uint8_t gpio, struct soc_amd_i2c_save *save_table) { uint32_t *gpio_ptr; - uint8_t *mux_ptr; - mux_ptr = (uint8_t *)(uintptr_t)(gpio + GPIO_IOMUX_MMIO_BASE); gpio_ptr = (uint32_t *)gpio_get_address(gpio); - save_table->mux_value = read8(mux_ptr); + save_table->mux_value = iomux_read8(gpio); save_table->control_value = read32(gpio_ptr); } @@ -358,12 +356,10 @@ static void restore_i2c_pin_registers(uint8_t gpio, struct soc_amd_i2c_save *save_table) { uint32_t *gpio_ptr; - uint8_t *mux_ptr; - mux_ptr = (uint8_t *)(uintptr_t)(gpio + GPIO_IOMUX_MMIO_BASE); gpio_ptr = (uint32_t *)gpio_get_address(gpio); - write8(mux_ptr, save_table->mux_value); - read8(mux_ptr); + iomux_write8(gpio, save_table->mux_value); + iomux_read8(gpio); write32(gpio_ptr, save_table->control_value); read32(gpio_ptr); } diff --git a/src/soc/amd/stoneyridge/include/soc/iomap.h b/src/soc/amd/stoneyridge/include/soc/iomap.h index 613dd044f6..e6327dc6db 100644 --- a/src/soc/amd/stoneyridge/include/soc/iomap.h +++ b/src/soc/amd/stoneyridge/include/soc/iomap.h @@ -32,19 +32,29 @@ #endif #define HPET_BASE_ADDRESS 0xfed00000 -/* Register blocks at fixed offsets from FED8_0000h and enabled in PMx04[1] */ +/* AcpiMmio blocks are at fixed offsets from FED8_0000h, enabled in PMx04[1] */ #define AMD_SB_ACPI_MMIO_ADDR 0xfed80000 -#define APU_SMI_BASE 0xfed80200 -#define PM_MMIO_BASE 0xfed80300 -#define BIOSRAM_MMIO_BASE 0xfed80500 -#define ACPI_REG_MMIO_BASE 0xfed80800 -#define ASF_MMIO_BASE 0xfed80900 -#define SMBUS_MMIO_BASE 0xfed80a00 -#define GPIO_IOMUX_MMIO_BASE 0xfed80d00 -#define MISC_MMIO_BASE 0xfed80e00 -#define XHCI_ACPI_PM_MMIO_BASE 0xfed81c00 -#define GPIO_CONTROL_MMIO_BASE 0xfed81500 -#define AOAC_MMIO_BASE 0xfed81e00 +#define ACPIMMIO_SM_PCI_BASE 0xfed80000 +#define ACPIMMIO_SMI_BASE 0xfed80200 +#define ACPIMMIO_PMIO_BASE 0xfed80300 +#define ACPIMMIO_PMIO2_BASE 0xfed80400 +#define ACPIMMIO_BIOSRAM_BASE 0xfed80500 +#define ACPIMMIO_CMOSRAM_BASE 0xfed80600 +#define ACPIMMIO_CMOS_BASE 0xfed80700 +#define ACPIMMIO_ACPI_BASE 0xfed80800 +#define ACPIMMIO_ASF_BASE 0xfed80900 +#define ACPIMMIO_SMBUS_BASE 0xfed80a00 +#define ACPIMMIO_WDT_BASE 0xfed80b00 +#define ACPIMMIO_HPET_BASE 0xfed80c00 +#define ACPIMMIO_IOMUX_BASE 0xfed80d00 +#define ACPIMMIO_MISC_BASE 0xfed80e00 +#define ACPIMMIO_DPVGA_BASE 0xfed81400 +#define ACPIMMIO_GPIO0_BASE 0xfed81500 +#define ACPIMMIO_GPIO1_BASE 0xfed81600 +#define ACPIMMIO_GPIO2_BASE 0xfed81700 +#define ACPIMMIO_XHCIPM_BASE 0xfed81c00 +#define ACPIMMIO_ACDCTMR_BASE 0xfed81d00 +#define ACPIMMIO_AOAC_BASE 0xfed81e00 #define APU_UART0_BASE 0xfedc6000 #define APU_UART1_BASE 0xfedc8000 diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 9fa93c8245..618a5deff7 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -491,6 +491,12 @@ void sb_tpm_decode(void); void sb_tpm_decode_spi(void); void lpc_wideio_512_window(uint16_t base); void lpc_wideio_16_window(uint16_t base); +uint8_t pm_io_read8(uint8_t reg); +uint16_t pm_io_read16(uint8_t reg); +uint32_t pm_io_read32(uint8_t reg); +void pm_io_write8(uint8_t reg, uint8_t value); +void pm_io_write16(uint8_t reg, uint16_t value); +void pm_io_write32(uint8_t reg, uint32_t value); u8 pm_read8(u8 reg); u16 pm_read16(u8 reg); u32 pm_read32(u8 reg); @@ -503,7 +509,11 @@ u32 acpi_read32(u8 reg); void acpi_write8(u8 reg, u8 value); void acpi_write16(u8 reg, u16 value); void acpi_write32(u8 reg, u32 value); +u8 misc_read8(u8 reg); +u16 misc_read16(u8 reg); u32 misc_read32(u8 reg); +void misc_write8(u8 reg, u8 value); +void misc_write16(u8 reg, u16 value); void misc_write32(u8 reg, u32 value); uint8_t smi_read8(uint8_t offset); uint16_t smi_read16(uint8_t offset); @@ -525,8 +535,22 @@ void xhci_pm_write16(uint8_t reg, uint16_t value); uint16_t xhci_pm_read16(uint8_t reg); void xhci_pm_write32(uint8_t reg, uint32_t value); uint32_t xhci_pm_read32(uint8_t reg); -void smbus_write8(uint32_t mmio, uint8_t reg, uint8_t value); -uint8_t smbus_read8(uint32_t mmio, uint8_t reg); +u8 iomux_read8(u8 reg); +u16 iomux_read16(u8 reg); +u32 iomux_read32(u8 reg); +void iomux_write8(u8 reg, u8 value); +void iomux_write16(u8 reg, u16 value); +void iomux_write32(u8 reg, u32 value); +uint8_t asf_read8(uint8_t offset); +uint16_t asf_read16(uint8_t offset); +void asf_write8(uint8_t offset, uint8_t value); +void asf_write16(uint8_t offset, uint16_t value); +uint8_t smbus_read8(uint8_t offset); +uint16_t smbus_read16(uint8_t offset); +void smbus_write8(uint8_t offset, uint8_t value); +void smbus_write16(uint8_t offset, uint16_t value); +uint8_t aoac_read8(uint8_t reg); +void aoac_write8(uint8_t reg, uint8_t value); void bootblock_fch_early_init(void); void bootblock_fch_init(void); /** diff --git a/src/soc/amd/stoneyridge/lpc.c b/src/soc/amd/stoneyridge/lpc.c index 87da9f1271..a838146c84 100644 --- a/src/soc/amd/stoneyridge/lpc.c +++ b/src/soc/amd/stoneyridge/lpc.c @@ -25,7 +25,6 @@ #include #include #include -#include #include #include #include @@ -36,31 +35,22 @@ static void lpc_init(struct device *dev) { u8 byte; - u32 dword; - - /* - * Enable the LPC Controller - * SMBus register 0x64 is not defined in public datasheet. - */ - dword = pci_read_config32(SOC_SMBUS_DEV, 0x64); - dword |= 1 << 20; - pci_write_config32(SOC_SMBUS_DEV, 0x64, dword); /* Initialize isa dma */ isa_dma_init(); /* Enable DMA transaction on the LPC bus */ - byte = pci_read_config8(SOC_SMBUS_DEV, LPC_PCI_CONTROL); + byte = pci_read_config8(dev, LPC_PCI_CONTROL); byte |= LEGACY_DMA_EN; - pci_write_config8(SOC_SMBUS_DEV, LPC_PCI_CONTROL, byte); + pci_write_config8(dev, LPC_PCI_CONTROL, byte); /* Disable the timeout mechanism on LPC */ - byte = pci_read_config8(SOC_SMBUS_DEV, LPC_IO_OR_MEM_DECODE_ENABLE); + byte = pci_read_config8(dev, LPC_IO_OR_MEM_DECODE_ENABLE); byte &= ~LPC_SYNC_TIMEOUT_COUNT_ENABLE; - pci_write_config8(SOC_SMBUS_DEV, LPC_IO_OR_MEM_DECODE_ENABLE, byte); + pci_write_config8(dev, LPC_IO_OR_MEM_DECODE_ENABLE, byte); /* Disable LPC MSI Capability */ - byte = pci_read_config8(SOC_SMBUS_DEV, LPC_MISC_CONTROL_BITS); + byte = pci_read_config8(dev, LPC_MISC_CONTROL_BITS); /* BIT 1 is not defined in public datasheet. */ byte &= ~(1 << 1); @@ -70,15 +60,15 @@ static void lpc_init(struct device *dev) * interrupt and visit LPC. */ byte &= ~LPC_NOHOG; - pci_write_config8(SOC_SMBUS_DEV, LPC_MISC_CONTROL_BITS, byte); + pci_write_config8(dev, LPC_MISC_CONTROL_BITS, byte); /* * Enable hand-instance of the pulse generator and SPI * controller prefetch of flash. */ - byte = pci_read_config8(SOC_SMBUS_DEV, LPC_HOST_CONTROL); + byte = pci_read_config8(dev, LPC_HOST_CONTROL); byte |= PREFETCH_EN_SPI_FROM_HOST | T_START_ENH; - pci_write_config8(SOC_SMBUS_DEV, LPC_HOST_CONTROL, byte); + pci_write_config8(dev, LPC_HOST_CONTROL, byte); cmos_check_update_date(); @@ -162,9 +152,8 @@ static void lpc_set_resources(struct device *dev) pci_dev_set_resources(dev); } -static void set_child_resource(struct device *child, - u32 *reg, - u32 *reg_x) +static void set_child_resource(struct device *dev, struct device *child, + u32 *reg, u32 *reg_x) { struct resource *res; u32 base, end; @@ -273,7 +262,7 @@ static void set_child_resource(struct device *child, wideio_index = sb_set_wideio_range(base, res->size); if (wideio_index != WIDEIO_RANGE_ERROR) { /* preserve wide IO related bits. */ - *reg_x = pci_read_config32(SOC_LPC_DEV, + *reg_x = pci_read_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE); printk(BIOS_DEBUG, @@ -309,11 +298,8 @@ static void lpc_enable_childrens_resources(struct device *dev) for (child = link->children; child; child = child->sibling) { if (child->enabled - && (child->path.type == DEVICE_PATH_PNP)) { - set_child_resource(child, - ®, - ®_x); - } + && (child->path.type == DEVICE_PATH_PNP)) + set_child_resource(dev, child, ®, ®_x); } } pci_write_config32(dev, LPC_IO_PORT_DECODE_ENABLE, reg); @@ -326,18 +312,6 @@ static void lpc_enable_resources(struct device *dev) lpc_enable_childrens_resources(dev); } -unsigned long acpi_fill_mcfg(unsigned long current) -{ - - current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, - CONFIG_MMCONF_BASE_ADDRESS, - 0, - 0, - CONFIG_MMCONF_BUS_NUMBER); - - return current; -} - static struct pci_operations lops_pci = { .set_subsystem = pci_dev_set_subsystem, }; diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index 42963c0941..5985832c81 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -176,6 +176,18 @@ static void northbridge_init(struct device *dev) setup_ioapic((u8 *)IO_APIC2_ADDR, CONFIG_MAX_CPUS+1); } +unsigned long acpi_fill_mcfg(unsigned long current) +{ + + current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, + CONFIG_MMCONF_BASE_ADDRESS, + 0, + 0, + CONFIG_MMCONF_BUS_NUMBER); + + return current; +} + static unsigned long acpi_fill_hest(acpi_hest_t *hest) { void *addr, *current; diff --git a/src/soc/amd/stoneyridge/sb_util.c b/src/soc/amd/stoneyridge/sb_util.c index b60f186ac8..524efc45ad 100644 --- a/src/soc/amd/stoneyridge/sb_util.c +++ b/src/soc/amd/stoneyridge/sb_util.c @@ -18,118 +18,119 @@ #include #include -void pm_write8(u8 reg, u8 value) +/* PM registers are accessed a byte at a time via CD6/CD7 */ +uint8_t pm_io_read8(uint8_t reg) { - write8((void *)(PM_MMIO_BASE + reg), value); + outb(reg, PM_INDEX); + return inb(PM_DATA); } -u8 pm_read8(u8 reg) +uint16_t pm_io_read16(uint8_t reg) { - return read8((void *)(PM_MMIO_BASE + reg)); + return (pm_io_read8(reg + sizeof(uint8_t)) << 8) | pm_io_read8(reg); } -void pm_write16(u8 reg, u16 value) +uint32_t pm_io_read32(uint8_t reg) { - write16((void *)(PM_MMIO_BASE + reg), value); + return (pm_io_read16(reg + sizeof(uint16_t)) << 16) | pm_io_read16(reg); } -u16 pm_read16(u8 reg) +void pm_io_write8(uint8_t reg, uint8_t value) { - return read16((void *)(PM_MMIO_BASE + reg)); + outb(reg, PM_INDEX); + outb(value, PM_DATA); } -void misc_write32(u8 reg, u32 value) +void pm_io_write16(uint8_t reg, uint16_t value) { - write32((void *)(MISC_MMIO_BASE + reg), value); + pm_io_write8(reg, value & 0xff); + value >>= 8; + pm_io_write8(reg + sizeof(uint8_t), value & 0xff); } -u32 misc_read32(u8 reg) +void pm_io_write32(uint8_t reg, uint32_t value) { - return read32((void *)(MISC_MMIO_BASE + reg)); + pm_io_write16(reg, value & 0xffff); + value >>= 16; + pm_io_write16(reg + sizeof(uint16_t), value & 0xffff); } -void pm_write32(u8 reg, u32 value) -{ - write32((void *)(PM_MMIO_BASE + reg), value); -} +/* smbus pci read/write - access registers at 0xfed80000 - currently unused */ -u32 pm_read32(u8 reg) -{ - return read32((void *)(PM_MMIO_BASE + reg)); -} +/* smi read/write - access registers at 0xfed80200 */ -u8 acpi_read8(u8 reg) +uint8_t smi_read8(uint8_t offset) { - return read8((void *)(ACPI_REG_MMIO_BASE + reg)); -} - -u16 acpi_read16(u8 reg) -{ - return read16((void *)(ACPI_REG_MMIO_BASE + reg)); -} - -u32 acpi_read32(u8 reg) -{ - return read32((void *)(ACPI_REG_MMIO_BASE + reg)); -} - -void acpi_write8(u8 reg, u8 value) -{ - write8((void *)(ACPI_REG_MMIO_BASE + reg), value); -} - -void acpi_write16(u8 reg, u16 value) -{ - write16((void *)(ACPI_REG_MMIO_BASE + reg), value); -} - -void acpi_write32(u8 reg, u32 value) -{ - write32((void *)(ACPI_REG_MMIO_BASE + reg), value); -} - -void smi_write32(uint8_t offset, uint32_t value) -{ - write32((void *)(APU_SMI_BASE + offset), value); -} - -uint32_t smi_read32(uint8_t offset) -{ - return read32((void *)(APU_SMI_BASE + offset)); + return read8((void *)(ACPIMMIO_SMI_BASE + offset)); } uint16_t smi_read16(uint8_t offset) { - return read16((void *)(APU_SMI_BASE + offset)); + return read16((void *)(ACPIMMIO_SMI_BASE + offset)); } -void smi_write16(uint8_t offset, uint16_t value) +uint32_t smi_read32(uint8_t offset) { - write16((void *)(APU_SMI_BASE + offset), value); -} - -uint8_t smi_read8(uint8_t offset) -{ - return read8((void *)(APU_SMI_BASE + offset)); + return read32((void *)(ACPIMMIO_SMI_BASE + offset)); } void smi_write8(uint8_t offset, uint8_t value) { - write8((void *)(APU_SMI_BASE + offset), value); + write8((void *)(ACPIMMIO_SMI_BASE + offset), value); } +void smi_write16(uint8_t offset, uint16_t value) +{ + write16((void *)(ACPIMMIO_SMI_BASE + offset), value); +} + +void smi_write32(uint8_t offset, uint32_t value) +{ + write32((void *)(ACPIMMIO_SMI_BASE + offset), value); +} + +/* pm read/write - access registers at 0xfed80300 */ + +u8 pm_read8(u8 reg) +{ + return read8((void *)(ACPIMMIO_PMIO_BASE + reg)); +} + +u16 pm_read16(u8 reg) +{ + return read16((void *)(ACPIMMIO_PMIO_BASE + reg)); +} + +u32 pm_read32(u8 reg) +{ + return read32((void *)(ACPIMMIO_PMIO_BASE + reg)); +} + +void pm_write8(u8 reg, u8 value) +{ + write8((void *)(ACPIMMIO_PMIO_BASE + reg), value); +} + +void pm_write16(u8 reg, u16 value) +{ + write16((void *)(ACPIMMIO_PMIO_BASE + reg), value); +} + +void pm_write32(u8 reg, u32 value) +{ + write32((void *)(ACPIMMIO_PMIO_BASE + reg), value); +} + +/* pm2 read/write - access registers at 0xfed80400 - currently unused */ + +/* biosram read/write - access registers at 0xfed80500 */ + uint8_t biosram_read8(uint8_t offset) { - return read8((void *)(BIOSRAM_MMIO_BASE + offset)); + return read8((void *)(ACPIMMIO_BIOSRAM_BASE + offset)); } -void biosram_write8(uint8_t offset, uint8_t value) -{ - write8((void *)(BIOSRAM_MMIO_BASE + offset), value); -} - -/* BiosRam may only be accessed a byte at a time */ -uint16_t biosram_read16(uint8_t offset) +uint16_t biosram_read16(uint8_t offset) /* Must be 1 byte at a time */ { int i; uint16_t value = 0; @@ -144,6 +145,11 @@ uint32_t biosram_read32(uint8_t offset) return value | biosram_read16(offset); } +void biosram_write8(uint8_t offset, uint8_t value) +{ + write8((void *)(ACPIMMIO_BIOSRAM_BASE + offset), value); +} + void biosram_write16(uint8_t offset, uint16_t value) { int i; @@ -162,6 +168,206 @@ void biosram_write32(uint8_t offset, uint32_t value) } } +/* cmosram read/write - access registers at 0xfed80600 - currently unused */ + +/* cmos read/write - access registers at 0xfed80700 - currently unused */ + +/* acpi read/write - access registers at 0xfed80800 */ + +u8 acpi_read8(u8 reg) +{ + return read8((void *)(ACPIMMIO_ACPI_BASE + reg)); +} + +u16 acpi_read16(u8 reg) +{ + return read16((void *)(ACPIMMIO_ACPI_BASE + reg)); +} + +u32 acpi_read32(u8 reg) +{ + return read32((void *)(ACPIMMIO_ACPI_BASE + reg)); +} + +void acpi_write8(u8 reg, u8 value) +{ + write8((void *)(ACPIMMIO_ACPI_BASE + reg), value); +} + +void acpi_write16(u8 reg, u16 value) +{ + write16((void *)(ACPIMMIO_ACPI_BASE + reg), value); +} + +void acpi_write32(u8 reg, u32 value) +{ + write32((void *)(ACPIMMIO_ACPI_BASE + reg), value); +} + +/* asf read/write - access registers at 0xfed80900 - not currently used */ + +u8 asf_read8(u8 reg) +{ + return read8((void *)(ACPIMMIO_ASF_BASE + reg)); +} + +u16 asf_read16(u8 reg) +{ + return read16((void *)(ACPIMMIO_ASF_BASE + reg)); +} + +void asf_write8(u8 reg, u8 value) +{ + write8((void *)(ACPIMMIO_ASF_BASE + reg), value); +} + +void asf_write16(u8 reg, u16 value) +{ + write16((void *)(ACPIMMIO_ASF_BASE + reg), value); +} + +/* smbus read/write - access registers at 0xfed80a00 and ASF at 0xfed80900 */ + +u8 smbus_read8(u8 reg) +{ + return read8((void *)(ACPIMMIO_SMBUS_BASE + reg)); +} + +u16 smbus_read16(u8 reg) +{ + return read16((void *)(ACPIMMIO_SMBUS_BASE + reg)); +} + +void smbus_write8(u8 reg, u8 value) +{ + write8((void *)(ACPIMMIO_SMBUS_BASE + reg), value); +} + +void smbus_write16(u8 reg, u16 value) +{ + write16((void *)(ACPIMMIO_SMBUS_BASE + reg), value); +} + +/* wdt read/write - access registers at 0xfed80b00 - not currently used */ + +/* hpet read/write - access registers at 0xfed80c00 - not currently used */ + +/* iomux read/write - access registers at 0xfed80d00 */ + +u8 iomux_read8(u8 reg) +{ + return read8((void *)(ACPIMMIO_IOMUX_BASE + reg)); +} + +u16 iomux_read16(u8 reg) +{ + return read16((void *)(ACPIMMIO_IOMUX_BASE + reg)); +} + +u32 iomux_read32(u8 reg) +{ + return read32((void *)(ACPIMMIO_IOMUX_BASE + reg)); +} + +void iomux_write8(u8 reg, u8 value) +{ + write8((void *)(ACPIMMIO_IOMUX_BASE + reg), value); +} + +void iomux_write16(u8 reg, u16 value) +{ + write16((void *)(ACPIMMIO_IOMUX_BASE + reg), value); +} + +void iomux_write32(u8 reg, u32 value) +{ + write32((void *)(ACPIMMIO_IOMUX_BASE + reg), value); +} + +/* misc read/write - access registers at 0xfed80e00 */ + +u8 misc_read8(u8 reg) +{ + return read8((void *)(ACPIMMIO_MISC_BASE + reg)); +} + +u16 misc_read16(u8 reg) +{ + return read16((void *)(ACPIMMIO_MISC_BASE + reg)); +} + +u32 misc_read32(u8 reg) +{ + return read32((void *)(ACPIMMIO_MISC_BASE + reg)); +} + +void misc_write8(u8 reg, u8 value) +{ + write8((void *)(ACPIMMIO_MISC_BASE + reg), value); +} + +void misc_write16(u8 reg, u16 value) +{ + write16((void *)(ACPIMMIO_MISC_BASE + reg), value); +} + +void misc_write32(u8 reg, u32 value) +{ + write32((void *)(ACPIMMIO_MISC_BASE + reg), value); +} + +/* dpvga read/write - access registers at 0xfed81400 - not currently used */ + +/* gpio bk 0 read/write - access registers at 0xfed81500 - not currently used */ +/* gpio bk 1 read/write - access registers at 0xfed81600 - not currently used */ +/* gpio bk 2 read/write - access registers at 0xfed81700 - not currently used */ + +/* xhci_pm read/write - access registers at 0xfed81c00 */ + +uint8_t xhci_pm_read8(uint8_t reg) +{ + return read8((void *)(ACPIMMIO_XHCIPM_BASE + reg)); +} + +uint16_t xhci_pm_read16(uint8_t reg) +{ + return read16((void *)(ACPIMMIO_XHCIPM_BASE + reg)); +} + +uint32_t xhci_pm_read32(uint8_t reg) +{ + return read32((void *)(ACPIMMIO_XHCIPM_BASE + reg)); +} + +void xhci_pm_write8(uint8_t reg, uint8_t value) +{ + write8((void *)(ACPIMMIO_XHCIPM_BASE + reg), value); +} + +void xhci_pm_write16(uint8_t reg, uint16_t value) +{ + write16((void *)(ACPIMMIO_XHCIPM_BASE + reg), value); +} + +void xhci_pm_write32(uint8_t reg, uint32_t value) +{ + write32((void *)(ACPIMMIO_XHCIPM_BASE + reg), value); +} + +/* acdc_tmr read/write - access registers at 0xfed81d00 */ + +/* aoac read/write - access registers at 0xfed81e00 - not currently used */ + +u8 aoac_read8(u8 reg) +{ + return read8((void *)(ACPIMMIO_AOAC_BASE + reg)); +} + +void aoac_write8(u8 reg, u8 value) +{ + write8((void *)(ACPIMMIO_AOAC_BASE + reg), value); +} + uint16_t pm_acpi_pm_cnt_blk(void) { return pm_read16(PM1_CNT_BLK); @@ -172,46 +378,6 @@ uint16_t pm_acpi_pm_evt_blk(void) return pm_read16(PM_EVT_BLK); } -void xhci_pm_write8(uint8_t reg, uint8_t value) -{ - write8((void *)(XHCI_ACPI_PM_MMIO_BASE + reg), value); -} - -uint8_t xhci_pm_read8(uint8_t reg) -{ - return read8((void *)(XHCI_ACPI_PM_MMIO_BASE + reg)); -} - -void xhci_pm_write16(uint8_t reg, uint16_t value) -{ - write16((void *)(XHCI_ACPI_PM_MMIO_BASE + reg), value); -} - -uint16_t xhci_pm_read16(uint8_t reg) -{ - return read16((void *)(XHCI_ACPI_PM_MMIO_BASE + reg)); -} - -void xhci_pm_write32(uint8_t reg, uint32_t value) -{ - write32((void *)(XHCI_ACPI_PM_MMIO_BASE + reg), value); -} - -uint32_t xhci_pm_read32(uint8_t reg) -{ - return read32((void *)(XHCI_ACPI_PM_MMIO_BASE + reg)); -} - -void smbus_write8(uint32_t mmio, uint8_t reg, uint8_t value) -{ - write8((void *)(mmio + reg), value); -} - -uint8_t smbus_read8(uint32_t mmio, uint8_t reg) -{ - return read8((void *)(mmio + reg)); -} - int acpi_get_sleep_type(void) { return acpi_sleep_from_pm1(inw(pm_acpi_pm_cnt_blk())); diff --git a/src/soc/amd/stoneyridge/sm.c b/src/soc/amd/stoneyridge/sm.c index 9344b2f180..803e628320 100644 --- a/src/soc/amd/stoneyridge/sm.c +++ b/src/soc/amd/stoneyridge/sm.c @@ -42,9 +42,9 @@ static u32 get_sm_mmio(struct device *dev) pbus = get_pbus_smbus(dev); res = find_resource(pbus->dev, 0x90); if (res->base == SMB_BASE_ADDR) - return SMBUS_MMIO_BASE; + return ACPIMMIO_SMBUS_BASE; - return ASF_MMIO_BASE; + return ACPIMMIO_ASF_BASE; } static int lsmbus_recv_byte(struct device *dev) diff --git a/src/soc/amd/stoneyridge/smbus.c b/src/soc/amd/stoneyridge/smbus.c index c4a022a9a9..6285d793b7 100644 --- a/src/soc/amd/stoneyridge/smbus.c +++ b/src/soc/amd/stoneyridge/smbus.c @@ -15,21 +15,51 @@ #include #include +#include #include #include +static u8 controller_read8(u32 base, u8 reg) +{ + switch (base) { + case ACPIMMIO_SMBUS_BASE: + return smbus_read8(reg); + case ACPIMMIO_ASF_BASE: + return asf_read8(reg); + default: + printk(BIOS_ERR, "Error attempting to read SMBus at address 0x%x\n", + base); + } + return 0xff; +} + +static void controller_write8(u32 base, u8 reg, u8 val) +{ + switch (base) { + case ACPIMMIO_SMBUS_BASE: + smbus_write8(reg, val); + break; + case ACPIMMIO_ASF_BASE: + asf_write8(reg, val); + break; + default: + printk(BIOS_ERR, "Error attempting to write SMBus at address 0x%x\n", + base); + } +} + static int smbus_wait_until_ready(u32 mmio) { u32 loops; loops = SMBUS_TIMEOUT; do { u8 val; - val = smbus_read8(mmio, SMBHSTSTAT); + val = controller_read8(mmio, SMBHSTSTAT); val &= SMBHST_STAT_VAL_BITS; if (val == 0) { /* ready now */ return 0; } - smbus_write8(mmio, SMBHSTSTAT, val); + controller_write8(mmio, SMBHSTSTAT, val); } while (--loops); return -2; /* time out */ } @@ -41,12 +71,12 @@ static int smbus_wait_until_done(u32 mmio) do { u8 val; - val = smbus_read8(mmio, SMBHSTSTAT); + val = controller_read8(mmio, SMBHSTSTAT); val &= SMBHST_STAT_VAL_BITS; /* mask off reserved bits */ if (val & SMBHST_STAT_ERROR_BITS) return -5; /* error */ if (val == SMBHST_STAT_NOERROR) { - smbus_write8(mmio, SMBHSTSTAT, val); /* clear sts */ + controller_write8(mmio, SMBHSTSTAT, val); /* clr sts */ return 0; } } while (--loops); @@ -61,19 +91,19 @@ int do_smbus_recv_byte(u32 mmio, u8 device) return -2; /* not ready */ /* set the device I'm talking to */ - smbus_write8(mmio, SMBHSTADDR, ((device & 0x7f) << 1) | 1); + controller_write8(mmio, SMBHSTADDR, ((device & 0x7f) << 1) | 1); - byte = smbus_read8(mmio, SMBHSTCTRL); + byte = controller_read8(mmio, SMBHSTCTRL); byte &= ~SMBHST_CTRL_MODE_BITS; /* Clear [4:2] */ byte |= SMBHST_CTRL_STRT | SMBHST_CTRL_BTE_RW; /* set mode, start */ - smbus_write8(mmio, SMBHSTCTRL, byte); + controller_write8(mmio, SMBHSTCTRL, byte); /* poll for transaction completion */ if (smbus_wait_until_done(mmio) < 0) return -3; /* timeout or error */ /* read results of transaction */ - byte = smbus_read8(mmio, SMBHSTDAT0); + byte = controller_read8(mmio, SMBHSTDAT0); return byte; } @@ -86,15 +116,15 @@ int do_smbus_send_byte(u32 mmio, u8 device, u8 val) return -2; /* not ready */ /* set the command... */ - smbus_write8(mmio, SMBHSTDAT0, val); + controller_write8(mmio, SMBHSTDAT0, val); /* set the device I'm talking to */ - smbus_write8(mmio, SMBHSTADDR, ((device & 0x7f) << 1) | 0); + controller_write8(mmio, SMBHSTADDR, ((device & 0x7f) << 1) | 0); - byte = smbus_read8(mmio, SMBHSTCTRL); + byte = controller_read8(mmio, SMBHSTCTRL); byte &= ~SMBHST_CTRL_MODE_BITS; /* Clear [4:2] */ byte |= SMBHST_CTRL_STRT | SMBHST_CTRL_BTE_RW; /* set mode, start */ - smbus_write8(mmio, SMBHSTCTRL, byte); + controller_write8(mmio, SMBHSTCTRL, byte); /* poll for transaction completion */ if (smbus_wait_until_done(mmio) < 0) @@ -111,22 +141,22 @@ int do_smbus_read_byte(u32 mmio, u8 device, u8 address) return -2; /* not ready */ /* set the command/address... */ - smbus_write8(mmio, SMBHSTCMD, address & 0xff); + controller_write8(mmio, SMBHSTCMD, address & 0xff); /* set the device I'm talking to */ - smbus_write8(mmio, SMBHSTADDR, ((device & 0x7f) << 1) | 1); + controller_write8(mmio, SMBHSTADDR, ((device & 0x7f) << 1) | 1); - byte = smbus_read8(mmio, SMBHSTCTRL); + byte = controller_read8(mmio, SMBHSTCTRL); byte &= ~SMBHST_CTRL_MODE_BITS; /* Clear [4:2] */ byte |= SMBHST_CTRL_STRT | SMBHST_CTRL_BDT_RW; /* set mode, start */ - smbus_write8(mmio, SMBHSTCTRL, byte); + controller_write8(mmio, SMBHSTCTRL, byte); /* poll for transaction completion */ if (smbus_wait_until_done(mmio) < 0) return -3; /* timeout or error */ /* read results of transaction */ - byte = smbus_read8(mmio, SMBHSTDAT0); + byte = controller_read8(mmio, SMBHSTDAT0); return byte; } @@ -139,18 +169,18 @@ int do_smbus_write_byte(u32 mmio, u8 device, u8 address, u8 val) return -2; /* not ready */ /* set the command/address... */ - smbus_write8(mmio, SMBHSTCMD, address & 0xff); + controller_write8(mmio, SMBHSTCMD, address & 0xff); /* set the device I'm talking to */ - smbus_write8(mmio, SMBHSTADDR, ((device & 0x7f) << 1) | 0); + controller_write8(mmio, SMBHSTADDR, ((device & 0x7f) << 1) | 0); /* output value */ - smbus_write8(mmio, SMBHSTDAT0, val); + controller_write8(mmio, SMBHSTDAT0, val); - byte = smbus_read8(mmio, SMBHSTCTRL); + byte = controller_read8(mmio, SMBHSTCTRL); byte &= ~SMBHST_CTRL_MODE_BITS; /* Clear [4:2] */ byte |= SMBHST_CTRL_STRT | SMBHST_CTRL_BDT_RW; /* set mode, start */ - smbus_write8(mmio, SMBHSTCTRL, byte); + controller_write8(mmio, SMBHSTCTRL, byte); /* poll for transaction completion */ if (smbus_wait_until_done(mmio) < 0) diff --git a/src/soc/amd/stoneyridge/smbus_spd.c b/src/soc/amd/stoneyridge/smbus_spd.c index ed73a6e51b..e57ecde578 100644 --- a/src/soc/amd/stoneyridge/smbus_spd.c +++ b/src/soc/amd/stoneyridge/smbus_spd.c @@ -46,7 +46,7 @@ static int readspd(uint8_t SmbusSlaveAddress, char *buffer, size_t count) dev_addr = (SmbusSlaveAddress >> 1); /* Read the first SPD byte */ - error = do_smbus_read_byte(SMBUS_MMIO_BASE, dev_addr, 0); + error = do_smbus_read_byte(ACPIMMIO_SMBUS_BASE, dev_addr, 0); if (error < 0) { printk(BIOS_ERR, "-------------SPD READ ERROR-----------\n"); return error; @@ -56,7 +56,7 @@ static int readspd(uint8_t SmbusSlaveAddress, char *buffer, size_t count) /* Read the remaining SPD bytes using do_smbus_recv_byte for speed */ for (index = 1 ; index < count ; index++) { - error = do_smbus_recv_byte(SMBUS_MMIO_BASE, dev_addr); + error = do_smbus_recv_byte(ACPIMMIO_SMBUS_BASE, dev_addr); if (error < 0) { printk(BIOS_ERR, "-------------SPD READ ERROR-----------\n"); return error; diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 9c546947e3..8dfef8b369 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -279,20 +279,18 @@ int sb_set_wideio_range(uint16_t start, uint16_t size) static void power_on_aoac_device(int aoac_device_control_register) { uint8_t byte; - uint8_t *register_pointer = (uint8_t *)(uintptr_t)AOAC_MMIO_BASE - + aoac_device_control_register; /* Power on the UART and AMBA devices */ - byte = read8(register_pointer); + byte = aoac_read8(aoac_device_control_register); byte |= FCH_AOAC_PWR_ON_DEV; - write8(register_pointer, byte); + aoac_write8(aoac_device_control_register, byte); } static bool is_aoac_device_enabled(int aoac_device_status_register) { uint8_t byte; - byte = read8((uint8_t *)(uintptr_t)AOAC_MMIO_BASE - + aoac_device_status_register); + + byte = aoac_read8(aoac_device_status_register); byte &= (FCH_AOAC_PWR_RST_STATE | FCH_AOAC_RST_CLK_OK_STATE); if (byte == (FCH_AOAC_PWR_RST_STATE | FCH_AOAC_RST_CLK_OK_STATE)) return true; @@ -331,11 +329,9 @@ void sb_lpc_port80(void) u8 byte; /* Enable LPC controller */ - outb(PM_LPC_GATING, PM_INDEX); - byte = inb(PM_DATA); + byte = pm_io_read8(PM_LPC_GATING); byte |= PM_LPC_ENABLE; - outb(PM_LPC_GATING, PM_INDEX); - outb(byte, PM_DATA); + pm_io_write8(PM_LPC_GATING, byte); /* Enable port 80 LPC decode in pci function 3 configuration space. */ byte = pci_read_config8(SOC_LPC_DEV, LPC_IO_OR_MEM_DEC_EN_HIGH); @@ -369,11 +365,9 @@ void sb_acpi_mmio_decode(void) uint8_t byte; /* Enable ACPI MMIO range 0xfed80000 - 0xfed81fff */ - outb(PM_ISA_CONTROL, PM_INDEX); - byte = inb(PM_DATA); + byte = pm_io_read8(PM_ISA_CONTROL); byte |= MMIO_EN; - outb(PM_ISA_CONTROL, PM_INDEX); - outb(byte, PM_DATA); + pm_io_write8(PM_ISA_CONTROL, byte); } static void sb_enable_cf9_io(void) @@ -393,14 +387,12 @@ static void sb_enable_legacy_io(void) void sb_clk_output_48Mhz(u32 osc) { u32 ctrl; - u32 *misc_clk_cntl_1_ptr = (u32 *)(uintptr_t)(MISC_MMIO_BASE - + MISC_CLK_CNTL1); /* * Clear the disable for OSCOUT1 (signal typically named XnnM_25M_48M) * or OSCOUT2 (USBCLK/25M_48M_OSC). The frequency defaults to 48MHz. */ - ctrl = read32(misc_clk_cntl_1_ptr); + ctrl = misc_read32(MISC_CLK_CNTL1); switch (osc) { case 1: @@ -412,7 +404,7 @@ void sb_clk_output_48Mhz(u32 osc) default: return; /* do nothing if invalid */ } - write32(misc_clk_cntl_1_ptr, ctrl); + misc_write32(MISC_CLK_CNTL1, ctrl); } static uintptr_t sb_spibase(void) @@ -632,12 +624,12 @@ static void setup_misc(int *reboot) static void fch_smbus_init(void) { pm_write8(SMB_ASF_IO_BASE, SMB_BASE_ADDR >> 8); - smbus_write8(SMBUS_MMIO_BASE, SMBTIMING, SMB_SPEED_400KHZ); + smbus_write8(SMBTIMING, SMB_SPEED_400KHZ); /* Clear all SMBUS status bits */ - smbus_write8(SMBUS_MMIO_BASE, SMBHSTSTAT, SMBHST_STAT_CLEAR); - smbus_write8(SMBUS_MMIO_BASE, SMBSLVSTAT, SMBSLV_STAT_CLEAR); - smbus_write8(ASF_MMIO_BASE, SMBHSTSTAT, SMBHST_STAT_CLEAR); - smbus_write8(ASF_MMIO_BASE, SMBSLVSTAT, SMBSLV_STAT_CLEAR); + smbus_write8(SMBHSTSTAT, SMBHST_STAT_CLEAR); + smbus_write8(SMBSLVSTAT, SMBSLV_STAT_CLEAR); + asf_write8(SMBHSTSTAT, SMBHST_STAT_CLEAR); + asf_write8(SMBSLVSTAT, SMBSLV_STAT_CLEAR); } /* Before console init */ diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c index c791378f13..ac6903a9d2 100644 --- a/src/soc/intel/apollolake/bootblock/bootblock.c +++ b/src/soc/intel/apollolake/bootblock/bootblock.c @@ -122,12 +122,3 @@ void bootblock_soc_early_init(void) paging_enable_for_car("pdpt", "pt"); } } - -void bootblock_soc_init(void) -{ - /* - * Clear the GPI interrupt enable & status registers to avoid any - * interrupt storm during the kernel bootup. - */ - gpi_clear_int_cfg(); -} diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index c3de4ee802..f6880a7f3f 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -50,6 +50,7 @@ #include #include #include +#include #include "chip.h" @@ -394,6 +395,12 @@ static void soc_init(void *data) * default policy that doesn't honor boards' requirements. */ itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); + /* + * Clear the GPI interrupt status and enable registers. These + * registers do not get reset to default state when booting from S5. + */ + gpi_clear_int_cfg(); + fsp_silicon_init(romstage_handoff_is_resume()); /* Restore GPIO IRQ polarities back to previous settings. */ @@ -762,6 +769,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd) /* Set VTD feature according to devicetree */ silconfig->VtdEnable = cfg->enable_vtd; + + mainboard_silicon_init_params(silconfig); } struct chip_operations soc_intel_apollolake_ops = { @@ -879,4 +888,10 @@ static void spi_flash_init_cb(void *unused) fast_spi_init(); } +__weak +void mainboard_silicon_init_params(FSP_S_CONFIG *silconfig) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); +} + BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, spi_flash_init_cb, NULL); diff --git a/src/soc/intel/apollolake/include/soc/ramstage.h b/src/soc/intel/apollolake/include/soc/ramstage.h new file mode 100644 index 0000000000..287f2ff945 --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/ramstage.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Andrey Petrov for Intel Corp.) + * Copyright (C) 2019 9elements Agency GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_APOLLOLAKE_RAMSTAGE_H_ +#define _SOC_APOLLOLAKE_RAMSTAGE_H_ + +#include + +void mainboard_silicon_init_params(FSP_S_CONFIG *silconfig); + +#endif /* _SOC_APOLLOLAKE_RAMSTAGE_H_ */ diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index a0c07084b8..ed5c9728a3 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -135,4 +135,18 @@ config DISABLE_HPET Enable this to disable the HPET support Solves the Linux MP-BIOS bug timer not connected. +config USE_GOOGLE_FSP + bool + help + Select this to use Google's custom Braswell FSP header/binary + instead of the public release on Github. Only google/cyan + variants require this; all other boards should use the public release. + +config FSP_HEADER_PATH + string + default "$(src)/vendorcode/intel/fsp/fsp1_1/braswell" if USE_GOOGLE_FSP + default "3rdparty/fsp/BraswellFspBinPkg/Include/" + help + Location of FSP header file FspUpdVpd.h + endif diff --git a/src/soc/intel/braswell/Makefile.inc b/src/soc/intel/braswell/Makefile.inc index a538f7daff..4e90edf15c 100644 --- a/src/soc/intel/braswell/Makefile.inc +++ b/src/soc/intel/braswell/Makefile.inc @@ -14,6 +14,7 @@ romstage-y += iosf.c romstage-y += lpc_init.c romstage-y += memmap.c romstage-y += pmutil.c +romstage-y += smbus.c romstage-y += tsc_freq.c postcar-y += tsc_freq.c @@ -52,11 +53,9 @@ smm-y += smihandler.c smm-y += spi.c smm-y += tsc_freq.c -# cpu_microcode_bins += ??? - CPPFLAGS_common += -I$(src)/soc/intel/braswell/ CPPFLAGS_common += -I$(src)/soc/intel/braswell/include -CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp1_1/braswell +CPPFLAGS_common += -I$(call strip_quotes,$(CONFIG_FSP_HEADER_PATH)) CPPFLAGS_common += -I3rdparty/blobs/mainboard/$(MAINBOARDDIR) diff --git a/src/soc/intel/braswell/chip.c b/src/soc/intel/braswell/chip.c index 4be13cdea3..900b2f33fd 100644 --- a/src/soc/intel/braswell/chip.c +++ b/src/soc/intel/braswell/chip.c @@ -129,36 +129,26 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params) params->Usb2Port0PerPortTxiSet = config->Usb2Port0PerPortTxiSet; params->Usb2Port0IUsbTxEmphasisEn = config->Usb2Port0IUsbTxEmphasisEn; params->Usb2Port0PerPortTxPeHalf = config->Usb2Port0PerPortTxPeHalf; - if (config->D0Usb2Port0PerPortRXISet != 0) - params->D0Usb2Port0PerPortRXISet = config->D0Usb2Port0PerPortRXISet; params->Usb2Port1PerPortPeTxiSet = config->Usb2Port1PerPortPeTxiSet; params->Usb2Port1PerPortTxiSet = config->Usb2Port1PerPortTxiSet; params->Usb2Port1IUsbTxEmphasisEn = config->Usb2Port1IUsbTxEmphasisEn; params->Usb2Port1PerPortTxPeHalf = config->Usb2Port1PerPortTxPeHalf; - if (config->D0Usb2Port1PerPortRXISet != 0) - params->D0Usb2Port1PerPortRXISet = config->D0Usb2Port1PerPortRXISet; params->Usb2Port2PerPortPeTxiSet = config->Usb2Port2PerPortPeTxiSet; params->Usb2Port2PerPortTxiSet = config->Usb2Port2PerPortTxiSet; params->Usb2Port2IUsbTxEmphasisEn = config->Usb2Port2IUsbTxEmphasisEn; params->Usb2Port2PerPortTxPeHalf = config->Usb2Port2PerPortTxPeHalf; - if (config->D0Usb2Port2PerPortRXISet != 0) - params->D0Usb2Port2PerPortRXISet = config->D0Usb2Port2PerPortRXISet; params->Usb2Port3PerPortPeTxiSet = config->Usb2Port3PerPortPeTxiSet; params->Usb2Port3PerPortTxiSet = config->Usb2Port3PerPortTxiSet; params->Usb2Port3IUsbTxEmphasisEn = config->Usb2Port3IUsbTxEmphasisEn; params->Usb2Port3PerPortTxPeHalf = config->Usb2Port3PerPortTxPeHalf; - if (config->D0Usb2Port3PerPortRXISet != 0) - params->D0Usb2Port3PerPortRXISet = config->D0Usb2Port3PerPortRXISet; params->Usb2Port4PerPortPeTxiSet = config->Usb2Port4PerPortPeTxiSet; params->Usb2Port4PerPortTxiSet = config->Usb2Port4PerPortTxiSet; params->Usb2Port4IUsbTxEmphasisEn = config->Usb2Port4IUsbTxEmphasisEn; params->Usb2Port4PerPortTxPeHalf = config->Usb2Port4PerPortTxPeHalf; - if (config->D0Usb2Port4PerPortRXISet != 0) - params->D0Usb2Port4PerPortRXISet = config->D0Usb2Port4PerPortRXISet; params->Usb3Lane0Ow2tapgen2deemph3p5 = config->Usb3Lane0Ow2tapgen2deemph3p5; @@ -266,9 +256,6 @@ void soc_display_silicon_init_params(const SILICON_INIT_UPD *old, fsp_display_upd_value("Usb2Port0PerPortTxPeHalf", 1, old->Usb2Port0PerPortTxPeHalf, new->Usb2Port0PerPortTxPeHalf); - fsp_display_upd_value("D0Usb2Port0PerPortRXISet", 1, - old->D0Usb2Port0PerPortRXISet, - new->D0Usb2Port0PerPortRXISet); fsp_display_upd_value("Usb2Port1PerPortPeTxiSet", 1, old->Usb2Port1PerPortPeTxiSet, new->Usb2Port1PerPortPeTxiSet); @@ -281,9 +268,6 @@ void soc_display_silicon_init_params(const SILICON_INIT_UPD *old, fsp_display_upd_value("Usb2Port1PerPortTxPeHalf", 1, old->Usb2Port1PerPortTxPeHalf, new->Usb2Port1PerPortTxPeHalf); - fsp_display_upd_value("D0Usb2Port1PerPortRXISet", 1, - old->D0Usb2Port1PerPortRXISet, - new->D0Usb2Port1PerPortRXISet); fsp_display_upd_value("Usb2Port2PerPortPeTxiSet", 1, old->Usb2Port2PerPortPeTxiSet, new->Usb2Port2PerPortPeTxiSet); @@ -296,9 +280,6 @@ void soc_display_silicon_init_params(const SILICON_INIT_UPD *old, fsp_display_upd_value("Usb2Port2PerPortTxPeHalf", 1, old->Usb2Port2PerPortTxPeHalf, new->Usb2Port2PerPortTxPeHalf); - fsp_display_upd_value("D0Usb2Port2PerPortRXISet", 1, - old->D0Usb2Port2PerPortRXISet, - new->D0Usb2Port2PerPortRXISet); fsp_display_upd_value("Usb2Port3PerPortPeTxiSet", 1, old->Usb2Port3PerPortPeTxiSet, new->Usb2Port3PerPortPeTxiSet); @@ -311,9 +292,6 @@ void soc_display_silicon_init_params(const SILICON_INIT_UPD *old, fsp_display_upd_value("Usb2Port3PerPortTxPeHalf", 1, old->Usb2Port3PerPortTxPeHalf, new->Usb2Port3PerPortTxPeHalf); - fsp_display_upd_value("D0Usb2Port3PerPortRXISet", 1, - old->D0Usb2Port3PerPortRXISet, - new->D0Usb2Port3PerPortRXISet); fsp_display_upd_value("Usb2Port4PerPortPeTxiSet", 1, old->Usb2Port4PerPortPeTxiSet, new->Usb2Port4PerPortPeTxiSet); @@ -326,9 +304,6 @@ void soc_display_silicon_init_params(const SILICON_INIT_UPD *old, fsp_display_upd_value("Usb2Port4PerPortTxPeHalf", 1, old->Usb2Port4PerPortTxPeHalf, new->Usb2Port4PerPortTxPeHalf); - fsp_display_upd_value("D0Usb2Port4PerPortRXISet", 1, - old->D0Usb2Port4PerPortRXISet, - new->D0Usb2Port4PerPortRXISet); fsp_display_upd_value("Usb3Lane0Ow2tapgen2deemph3p5", 1, old->Usb3Lane0Ow2tapgen2deemph3p5, new->Usb3Lane0Ow2tapgen2deemph3p5); diff --git a/src/soc/intel/braswell/chip.h b/src/soc/intel/braswell/chip.h index 4afaf44417..5a00328f4d 100644 --- a/src/soc/intel/braswell/chip.h +++ b/src/soc/intel/braswell/chip.h @@ -32,9 +32,6 @@ #define SVID_CONFIG3 3 #define SVID_PMIC_CONFIG 8 -#define MEM_DDR3 0 -#define MEM_LPDDR3 1 - enum lpe_clk_src { LPE_CLK_SRC_XTAL, LPE_CLK_SRC_PLL, @@ -172,11 +169,6 @@ struct soc_intel_braswell_config { UINT8 I2C4Frequency; UINT8 I2C5Frequency; UINT8 I2C6Frequency; - UINT8 D0Usb2Port0PerPortRXISet; /*setting for D0 stepping SOC*/ - UINT8 D0Usb2Port1PerPortRXISet; /*setting for D0 stepping SOC*/ - UINT8 D0Usb2Port2PerPortRXISet; /*setting for D0 stepping SOC*/ - UINT8 D0Usb2Port3PerPortRXISet; /*setting for D0 stepping SOC*/ - UINT8 D0Usb2Port4PerPortRXISet; /*setting for D0 stepping SOC*/ }; extern struct chip_operations soc_intel_braswell_ops; diff --git a/src/soc/intel/braswell/include/soc/pei_data.h b/src/soc/intel/braswell/include/soc/pei_data.h deleted file mode 100644 index 50aabed66e..0000000000 --- a/src/soc/intel/braswell/include/soc/pei_data.h +++ /dev/null @@ -1,62 +0,0 @@ -/* - * UEFI PEI wrapper - * - * Copyright (C) 2014 Google Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Google Inc. nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL GOOGLE INC BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _PEI_DATA_H_ -#define _PEI_DATA_H_ - -#include - -#define PEI_VERSION 22 - -#define ABI_X86 __attribute__((regparm(0))) - -typedef void ABI_X86(*tx_byte_func)(unsigned char byte); - -struct pei_data { - /* Chip settings */ - void *spd_data_ch0; - void *spd_data_ch1; - uint8_t spd_ch0_config; - uint8_t spd_ch1_config; - - /* System state information */ - int boot_mode; - - /* Fast boot and S3 resume MRC data */ - int saved_data_size; - const void *saved_data; - int disable_saved_data; - - /* New save data from MRC */ - int data_to_save_size; - void *data_to_save; -}; - -typedef struct pei_data PEI_DATA; - -#endif /* _PEI_DATA_H_ */ diff --git a/src/soc/intel/braswell/include/soc/romstage.h b/src/soc/intel/braswell/include/soc/romstage.h index 8fa9c8a713..633233e6c6 100644 --- a/src/soc/intel/braswell/include/soc/romstage.h +++ b/src/soc/intel/braswell/include/soc/romstage.h @@ -20,18 +20,20 @@ #include #include #include -#include #include void gfx_init(void); void tco_disable(void); void punit_init(void); int early_spi_read_wpsr(u8 *sr); -void mainboard_fill_spd_data(struct pei_data *pei_data); void set_max_freq(void); /* romstage_common.c functions */ void program_base_addresses(void); int chipset_prev_sleep_state(struct chipset_power_state *ps); +/* Values for FSP's PcdMemoryTypeEnable */ +#define MEM_DDR3 0 +#define MEM_LPDDR3 1 + #endif /* _SOC_ROMSTAGE_H_ */ diff --git a/src/mainboard/intel/saddlebrook/pei_data.c b/src/soc/intel/braswell/smbus.c similarity index 54% rename from src/mainboard/intel/saddlebrook/pei_data.c rename to src/soc/intel/braswell/smbus.c index ac4ce95723..7e1b0dfbb0 100644 --- a/src/mainboard/intel/saddlebrook/pei_data.c +++ b/src/soc/intel/braswell/smbus.c @@ -1,8 +1,8 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. + * Copyright (C) 2017 Intel Corporation. + * Copyright (C) 2019 3mdeb * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -14,14 +14,16 @@ * GNU General Public License for more details. */ -#include -#include -#include "spd/spd.h" +#include +#include +#include -void mainboard_fill_pei_data(struct pei_data *pei_data) +u8 smbus_read_byte(u32 smbus_dev, u8 addr, u8 offset) { - mainboard_fill_dq_map_data(&pei_data->dq_map); - mainboard_fill_dqs_map_data(&pei_data->dqs_map); - mainboard_fill_rcomp_res_data(&pei_data->RcompResistor); - mainboard_fill_rcomp_strength_data(&pei_data->RcompTarget); + return do_smbus_read_byte(SMBUS_BASE_ADDRESS, addr, offset); +} + +u8 smbus_write_byte(u32 smbus_dev, u8 addr, u8 offset, u8 value) +{ + return do_smbus_write_byte(SMBUS_BASE_ADDRESS, addr, offset, value); } diff --git a/src/soc/intel/braswell/southcluster.c b/src/soc/intel/braswell/southcluster.c index 000790d9a6..bf9f689c2a 100644 --- a/src/soc/intel/braswell/southcluster.c +++ b/src/soc/intel/braswell/southcluster.c @@ -347,7 +347,7 @@ static void sc_init(struct device *dev) * Common code for the south cluster devices. */ -/* Set bit in function disble register to hide this device. */ +/* Set bit in function disable register to hide this device. */ static void sc_disable_devfn(struct device *dev) { void *func_dis = (void *)(PMC_BASE_ADDRESS + FUNC_DIS); diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c index 8438ab45db..7679724ece 100644 --- a/src/soc/intel/broadwell/lpc.c +++ b/src/soc/intel/broadwell/lpc.c @@ -502,7 +502,7 @@ static void pch_lpc_add_mmio_resources(struct device *dev) #define LPC_DEFAULT_IO_RANGE_LOWER 0 #define LPC_DEFAULT_IO_RANGE_UPPER 0x1000 -static inline int pch_io_range_in_default(u16 base, u16 size) +static inline int pch_io_range_in_default(int base, int size) { /* Does it start above the range? */ if (base >= LPC_DEFAULT_IO_RANGE_UPPER) diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 6759b7ff99..e524275b8f 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -90,6 +90,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CPU select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT + select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 select SOC_INTEL_COMMON_BLOCK_HDA select SOC_INTEL_COMMON_BLOCK_SA @@ -182,6 +183,11 @@ config MAX_ROOT_PORTS default 24 if SOC_INTEL_CANNONLAKE_PCH_H default 16 +config MAX_PCIE_CLOCKS + int + default 16 if SOC_INTEL_CANNONLAKE_PCH_H + default 6 + config SMM_TSEG_SIZE hex default 0x800000 diff --git a/src/soc/intel/cannonlake/acpi/lpit.asl b/src/soc/intel/cannonlake/acpi/lpit.asl index 85158069b6..93bce2644e 100644 --- a/src/soc/intel/cannonlake/acpi/lpit.asl +++ b/src/soc/intel/cannonlake/acpi/lpit.asl @@ -14,6 +14,8 @@ * GNU General Public License for more details. */ +External(\_SB.MS0X, MethodObj) + scope(\_SB) { Device(LPID) { @@ -62,12 +64,20 @@ scope(\_SB) */ If(Arg2 == 5) { \_SB.PCI0.LPCB.EC0.S0IX(1) + /* provide board level s0ix hook */ + If (CondRefOf (\_SB.MS0X)) { + \_SB.MS0X(1) + } } /* * Function 6. */ If(Arg2 == 6) { \_SB.PCI0.LPCB.EC0.S0IX(0) + /* provide board level s0ix hook */ + If (CondRefOf (\_SB.MS0X)) { + \_SB.MS0X(0) + } } } Return(Buffer(One) {0x00}) diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 709c7acce9..cdf5edfe4a 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -21,6 +21,7 @@ #include #include #include +#include #include #include #include @@ -167,10 +168,10 @@ struct soc_intel_cannonlake_config { /* PCIe output clocks type to Pcie devices. * 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use, * 0xFF: not used */ - uint8_t PcieClkSrcUsage[CONFIG_MAX_ROOT_PORTS]; + uint8_t PcieClkSrcUsage[CONFIG_MAX_PCIE_CLOCKS]; /* PCIe ClkReq-to-ClkSrc mapping, number of clkreq signal assigned to * clksrc. */ - uint8_t PcieClkSrcClkReq[CONFIG_MAX_ROOT_PORTS]; + uint8_t PcieClkSrcClkReq[CONFIG_MAX_PCIE_CLOCKS]; /* PCIe LTR(Latency Tolerance Reporting) mechanism */ uint8_t PcieRpLtrEnable[CONFIG_MAX_ROOT_PORTS]; /* Enable/Disable HotPlug support for Root Port */ diff --git a/src/soc/intel/common/Kconfig b/src/soc/intel/common/Kconfig index 318cc25c87..ac2268661f 100644 --- a/src/soc/intel/common/Kconfig +++ b/src/soc/intel/common/Kconfig @@ -51,13 +51,6 @@ config SOC_INTEL_COMMON_ACPI bool default n -config SOC_INTEL_COMMON_ACPI_EC_PTS_WAK - bool - default n - help - Set this option to have the platform level _PTS/_WAK methods call - methods provided by the Embedded Controller. - config SOC_INTEL_COMMON_NHLT bool default n diff --git a/src/soc/intel/common/acpi/platform.asl b/src/soc/intel/common/acpi/platform.asl index 8b85d44057..9aa2edc6df 100644 --- a/src/soc/intel/common/acpi/platform.asl +++ b/src/soc/intel/common/acpi/platform.asl @@ -37,10 +37,6 @@ Method (_PTS, 1) { Store (POST_OS_ENTER_PTS, DBG0) -#if CONFIG(SOC_INTEL_COMMON_ACPI_EC_PTS_WAK) - /* Call EC _PTS handler */ - \_SB.PCI0.LPCB.EC0.PTS (Arg0) -#endif If (CondRefOf (\_SB.MPTS)) { \_SB.MPTS (Arg0) @@ -58,10 +54,5 @@ Method (_WAK, 1) \_SB.MWAK (Arg0) } -#if CONFIG(SOC_INTEL_COMMON_ACPI_EC_PTS_WAK) - /* Call EC _WAK handler */ - \_SB.PCI0.LPCB.EC0.WAK (Arg0) -#endif - Return (Package(){0,0}) } diff --git a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h index 91d8f00a89..e1ddd4babb 100644 --- a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h +++ b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h @@ -391,6 +391,13 @@ PAD_IOSSTATE(TxDRxE)) #if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT) +/* GPI, GPIO Driver, SCI interrupt */ +#define PAD_CFG_GPI_GPIO_DRIVER_SCI(pad, pull, rst, trig, inv) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ + PAD_IRQ_CFG(SCI, trig, inv), \ + PAD_PULL(pull) | PAD_CFG1_GPIO_DRIVER | PAD_IOSSTATE(TxDRxE)) + #define PAD_CFG_GPI_DUAL_ROUTE(pad, pull, rst, trig, inv, route1, route2) \ _PAD_CFG_STRUCT(pad, \ PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c index d5f76f3a7b..43b3522431 100644 --- a/src/soc/intel/common/block/lpc/lpc.c +++ b/src/soc/intel/common/block/lpc/lpc.c @@ -127,6 +127,11 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_SPT_H_C236, PCI_DEVICE_ID_INTEL_SPT_H_PREMIUM, PCI_DEVICE_ID_INTEL_SPT_H_H110, + PCI_DEVICE_ID_INTEL_SPT_H_H170, + PCI_DEVICE_ID_INTEL_SPT_H_Z170, + PCI_DEVICE_ID_INTEL_SPT_H_Q170, + PCI_DEVICE_ID_INTEL_SPT_H_Q150, + PCI_DEVICE_ID_INTEL_SPT_H_B150, PCI_DEVICE_ID_INTEL_SPT_H_QM170, PCI_DEVICE_ID_INTEL_SPT_H_HM175, PCI_DEVICE_ID_INTEL_SPT_H_QM175, diff --git a/src/soc/intel/common/block/systemagent/systemagent_early.c b/src/soc/intel/common/block/systemagent/systemagent_early.c index 61f14a935c..c12c64ab53 100644 --- a/src/soc/intel/common/block/systemagent/systemagent_early.c +++ b/src/soc/intel/common/block/systemagent/systemagent_early.c @@ -24,7 +24,7 @@ #include "systemagent_def.h" -#if !ENV_RAMSTAGE +#if ENV_BOOTBLOCK void bootblock_systemagent_early_init(void) { uint32_t reg; diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index ee2c928464..e9f555f13c 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -35,7 +35,6 @@ romstage-y += gspi.c romstage-y += i2c.c romstage-y += memmap.c romstage-y += me.c -romstage-y += pei_data.c romstage-y += pmc.c romstage-y += pmutil.c romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c @@ -58,7 +57,6 @@ ramstage-y += lpc.c ramstage-y += me.c ramstage-y += memmap.c ramstage-y += p2sb.c -ramstage-y += pei_data.c ramstage-y += pmc.c ramstage-y += pmutil.c ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c diff --git a/src/soc/intel/skylake/bootblock/report_platform.c b/src/soc/intel/skylake/bootblock/report_platform.c index f79343508b..de845c7854 100644 --- a/src/soc/intel/skylake/bootblock/report_platform.c +++ b/src/soc/intel/skylake/bootblock/report_platform.c @@ -71,6 +71,11 @@ static struct { { PCI_DEVICE_ID_INTEL_SPT_LP_Y_PREMIUM, "Skylake-Y Premium" }, { PCI_DEVICE_ID_INTEL_SPT_H_PREMIUM, "Skylake PCH-H Premium" }, { PCI_DEVICE_ID_INTEL_SPT_H_H110, "Skylake PCH-H H110" }, + { PCI_DEVICE_ID_INTEL_SPT_H_H170, "Skylake PCH-H H170" }, + { PCI_DEVICE_ID_INTEL_SPT_H_Z170, "Skylake PCH-H Z170" }, + { PCI_DEVICE_ID_INTEL_SPT_H_Q170, "Skylake PCH-H Q170" }, + { PCI_DEVICE_ID_INTEL_SPT_H_Q150, "Skylake PCH-H Q150" }, + { PCI_DEVICE_ID_INTEL_SPT_H_B150, "Skylake PCH-H B150" }, { PCI_DEVICE_ID_INTEL_SPT_H_C236, "Skylake PCH-H C236" }, { PCI_DEVICE_ID_INTEL_SPT_H_QM170, "Skylake PCH-H QM170" }, { PCI_DEVICE_ID_INTEL_SPT_H_HM175, "Skylake PCH-H HM175" }, diff --git a/src/soc/intel/skylake/include/fsp11/soc/romstage.h b/src/soc/intel/skylake/include/fsp11/soc/romstage.h index 36825f7aea..386931043d 100644 --- a/src/soc/intel/skylake/include/fsp11/soc/romstage.h +++ b/src/soc/intel/skylake/include/fsp11/soc/romstage.h @@ -24,6 +24,4 @@ void intel_early_me_status(void); void enable_smbus(void); int smbus_read_byte(unsigned int device, unsigned int address); -void mainboard_fill_spd_data(struct pei_data *pei_data); - #endif /* _SOC_ROMSTAGE_H_ */ diff --git a/src/soc/intel/skylake/include/soc/pei_data.h b/src/soc/intel/skylake/include/soc/pei_data.h deleted file mode 100644 index 02e04c6c02..0000000000 --- a/src/soc/intel/skylake/include/soc/pei_data.h +++ /dev/null @@ -1,99 +0,0 @@ -/* - * UEFI PEI wrapper - * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Google Inc. nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL GOOGLE INC BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _PEI_DATA_H_ -#define _PEI_DATA_H_ - -#include - -#define PEI_VERSION 22 - -#define ABI_X86 __attribute__((regparm(0))) - -typedef void ABI_X86(*tx_byte_func)(unsigned char byte); - -struct pei_data { - uint32_t pei_version; - - int boot_mode; - int ec_present; - - /* Console output function */ - tx_byte_func tx_byte; - - /* - * DIMM SPD data for memory down configurations - * [CHANNEL][SLOT][SPD] - */ - uint8_t spd_data[2][2][512]; - - /* - * LPDDR3 DQ byte map - * [CHANNEL][ITERATION][2] - * - * Maps which PI clocks are used by what LPDDR DQ Bytes (from CPU side) - * DQByteMap[0] - ClkDQByteMap: - * - If clock is per rank, program to [0xFF, 0xFF] - * - If clock is shared by 2 ranks, program to [0xFF, 0] or [0, 0xFF] - * - If clock is shared by 2 ranks but does not go to all bytes, - * Entry[i] defines which DQ bytes Group i services - * DQByteMap[1] - CmdNDQByteMap: [0] is CmdN/CAA and [1] is CmdN/CAB - * DQByteMap[2] - CmdSDQByteMap: [0] is CmdS/CAA and [1] is CmdS/CAB - * DQByteMap[3] - CkeDQByteMap : [0] is CKE /CAA and [1] is CKE /CAB - * For DDR, DQByteMap[3:1] = [0xFF, 0] - * DQByteMap[4] - CtlDQByteMap : Always program to [0xFF, 0] - * since we have 1 CTL / rank - * DQByteMap[5] - CmdVDQByteMap: Always program to [0xFF, 0] - * since we have 1 CA Vref - */ - uint8_t dq_map[2][12]; - - /* - * LPDDR3 Map from CPU DQS pins to SDRAM DQS pins - * [CHANNEL][MAX_BYTES] - */ - uint8_t dqs_map[2][8]; - uint16_t RcompResistor[3]; - uint16_t RcompTarget[5]; - /* Data read from flash and passed into MRC */ - const void *saved_data; - int saved_data_size; - - /* Disable use of saved data (can be set by mainboard) */ - int disable_saved_data; - - /* Data from MRC that should be saved to flash */ - void *data_to_save; - int data_to_save_size; - int mem_cfg_id; -} __packed; - -typedef struct pei_data PEI_DATA; - -#endif /* _PEI_DATA_H_ */ diff --git a/src/soc/intel/skylake/memmap.c b/src/soc/intel/skylake/memmap.c index fde916a922..ff7edbc95a 100644 --- a/src/soc/intel/skylake/memmap.c +++ b/src/soc/intel/skylake/memmap.c @@ -170,13 +170,13 @@ static size_t get_prmrr_size(uintptr_t dram_base, } /* Calculate Intel Traditional Memory size based on GSM, DSM, TSEG and DPR. */ -static size_t calculate_traditional_mem_size(uintptr_t dram_base, - const struct device *dev) +static size_t calculate_traditional_mem_size(uintptr_t dram_base) { + const struct device *igd_dev = pcidev_path_on_root(SA_DEVFN_IGD); uintptr_t traditional_mem_base = dram_base; size_t traditional_mem_size; - if (dev->enabled) { + if (igd_dev && igd_dev->enabled) { /* Read BDSM from Host Bridge */ traditional_mem_base -= sa_get_dsm_size(); @@ -200,9 +200,9 @@ static size_t calculate_traditional_mem_size(uintptr_t dram_base, * Calculate Intel Reserved Memory size based on * PRMRR size, Trace Hub config and PTT selection. */ -static size_t calculate_reserved_mem_size(uintptr_t dram_base, - const struct device *dev) +static size_t calculate_reserved_mem_size(uintptr_t dram_base) { + const struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT); uintptr_t reserve_mem_base = dram_base; size_t reserve_mem_size; const struct soc_intel_skylake_config *config; @@ -259,20 +259,15 @@ static size_t calculate_reserved_mem_size(uintptr_t dram_base, static uintptr_t calculate_dram_base(size_t *reserved_mem_size) { uintptr_t dram_base; - const struct device *dev; - - dev = dev_find_slot(0, PCI_DEVFN(SA_DEV_SLOT_IGD, 0)); - if (!dev) - die("ERROR - IGD device not found!"); /* Read TOLUD from Host Bridge offset */ dram_base = sa_get_tolud_base(); /* Get Intel Traditional Memory Range Size */ - dram_base -= calculate_traditional_mem_size(dram_base, dev); + dram_base -= calculate_traditional_mem_size(dram_base); /* Get Intel Reserved Memory Range Size */ - *reserved_mem_size = calculate_reserved_mem_size(dram_base, dev); + *reserved_mem_size = calculate_reserved_mem_size(dram_base); dram_base -= *reserved_mem_size; diff --git a/src/soc/intel/skylake/pei_data.c b/src/soc/intel/skylake/pei_data.c deleted file mode 100644 index 203a1d8e36..0000000000 --- a/src/soc/intel/skylake/pei_data.c +++ /dev/null @@ -1,48 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "chip.h" - -static void ABI_X86 send_to_console(unsigned char b) -{ - console_tx_byte(b); -} - -void soc_fill_pei_data(struct pei_data *pei_data) -{ - const struct device *dev; - const struct soc_intel_skylake_config *config; - - /* Set the parameters for MemoryInit */ - dev = dev_find_slot(0, PCH_DEVFN_LPC); - config = dev->chip_info; - - pei_data->pei_version = PEI_VERSION; - pei_data->tx_byte = &send_to_console; - - /* Force a full memory train if RMT is enabled */ - pei_data->disable_saved_data = config->Rmt; -} diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index 0501b04493..12239ae13e 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -26,7 +26,6 @@ #include #include #include -#include #include #include #include @@ -44,8 +43,11 @@ void soc_pre_ram_init(struct romstage_params *params) /* Program MCHBAR and DMIBAR */ systemagent_early_init(); - /* Prepare to initialize memory */ - soc_fill_pei_data(params->pei_data); + const struct device *const dev = pcidev_path_on_root(PCH_DEVFN_LPC); + const struct soc_intel_skylake_config *const config = + dev ? dev->chip_info : NULL; + /* Force a full memory train if RMT is enabled */ + params->disable_saved_data = config && config->Rmt; } /* UPD parameters to be initialized before MemoryInit */ diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index c166e3a7c1..2f75479339 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -304,10 +304,6 @@ static void soc_primary_gfx_config_params(FSP_M_CONFIG *m_cfg, */ m_cfg->InternalGfx = 0; m_cfg->IgdDvmt50PreAlloc = 0; - if (config->PrimaryDisplay == Display_iGFX) - m_cfg->PrimaryDisplay = Display_Auto; - else - m_cfg->PrimaryDisplay = config->PrimaryDisplay; } else { m_cfg->InternalGfx = 1; /* @@ -319,8 +315,8 @@ static void soc_primary_gfx_config_params(FSP_M_CONFIG *m_cfg, * a high resolution panel */ m_cfg->IgdDvmt50PreAlloc = 2; - m_cfg->PrimaryDisplay = config->PrimaryDisplay; } + m_cfg->PrimaryDisplay = config->PrimaryDisplay; } void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) diff --git a/src/soc/mediatek/mt8183/mt6358.c b/src/soc/mediatek/mt8183/mt6358.c index 8162e3aaf1..705424337f 100644 --- a/src/soc/mediatek/mt8183/mt6358.c +++ b/src/soc/mediatek/mt8183/mt6358.c @@ -16,6 +16,7 @@ #include #include #include +#include static struct pmic_setting init_setting[] = { /* [15:0]: TMA_KEY */ @@ -775,13 +776,18 @@ static void mt6358_lp_setting(void) void mt6358_init(void) { + struct stopwatch voltage_settled; + if (pwrap_init()) die("ERROR - Failed to initialize pmic wrap!"); pmic_set_power_hold(true); pmic_wdt_set(); mt6358_init_setting(); + stopwatch_init_usecs_expire(&voltage_settled, 200); wk_sleep_voltage_by_ddr(); wk_power_down_seq(); mt6358_lp_setting(); + while (!stopwatch_expired(&voltage_settled)) + /* wait for voltages to settle */; } diff --git a/src/soc/qualcomm/common/Kconfig b/src/soc/qualcomm/common/Kconfig new file mode 100644 index 0000000000..f3d12629fb --- /dev/null +++ b/src/soc/qualcomm/common/Kconfig @@ -0,0 +1,5 @@ + +config QC_SDI_ENABLE + bool + default n + prompt "Debug Build: enable SDI" diff --git a/src/soc/qualcomm/common/include/soc/mmu_common.h b/src/soc/qualcomm/common/include/soc/mmu_common.h new file mode 100644 index 0000000000..ee781224bd --- /dev/null +++ b/src/soc/qualcomm/common/include/soc/mmu_common.h @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_QUALCOMM_MMU_COMMON_H_ +#define _SOC_QUALCOMM_MMU_COMMON_H_ + +#include +#include + +#define CACHED_RAM (MA_MEM | MA_S | MA_RW) +#define UNCACHED_RAM (MA_MEM | MA_S | MA_RW | MA_MEM_NC) +#define DEV_MEM (MA_DEV | MA_S | MA_RW) + +static struct region * const ddr_region = (struct region *)_ddr_information; + +void soc_mmu_dram_config_post_dram_init(void); +void qc_mmu_dram_config_post_dram_init(void *ddr_base, size_t ddr_size); + +#endif /* _SOC_QUALCOMM_MMU_COMMON_H_ */ diff --git a/src/soc/qualcomm/common/include/soc/qclib_common.h b/src/soc/qualcomm/common/include/soc/qclib_common.h new file mode 100644 index 0000000000..19ec083bfd --- /dev/null +++ b/src/soc/qualcomm/common/include/soc/qclib_common.h @@ -0,0 +1,76 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_QUALCOMM_QCLIB_COMMON_H__ +#define _SOC_QUALCOMM_QCLIB_COMMON_H__ + +/* coreboot & QCLib I/F definitions */ + +/* string field lengths */ +#define QCLIB_MAGIC_NUMBER_LENGTH 8 +#define QCLIB_FMAP_NAME_LENGTH 24 +#define QCLIB_TE_NAME_LENGTH 24 + +/* FMAP_REGION names */ +#define QCLIB_FR_DDR_TRAINING_DATA "RO_DDR_TRAINING" +#define QCLIB_FR_LIMITS_CFG_DATA "RO_LIMITS_CFG" + +/* TE_NAME (table entry name) */ +#define QCLIB_TE_DDR_INFORMATION "ddr_information" +#define QCLIB_TE_QCLIB_LOG_BUFFER "qclib_log_buffer" +#define QCLIB_TE_DCB_SETTINGS "dcb_settings" +#define QCLIB_TE_CDT_SETTINGS "cdt_settings" +#define QCLIB_TE_PMIC_SETTINGS "pmic_settings" +#define QCLIB_TE_DDR_TRAINING_DATA "ddr_training_data" +#define QCLIB_TE_LIMITS_CFG_DATA "limits_cfg_data" +#define QCLIB_TE_QCSDI "qcsdi" + +/* BA_BMASK_VALUES (blob_attributes bit mask values) */ +#define QCLIB_BA_SAVE_TO_STORAGE 0x00000001 + +struct qclib_cb_if_table_entry { + char name[QCLIB_TE_NAME_LENGTH]; /* 0x00 TE_NAME */ + uint64_t blob_address; /* 0x18 blob addr in SRAM */ + uint32_t size; /* 0x20 blob size in SRAM */ + uint32_t blob_attributes; /* 0x24 BA_BMASK_VALUES */ +}; + +/* GA_BMASK_VALUES (global_attributes bit mask values) */ +#define QCLIB_GA_ENABLE_UART_LOGGING 0x00000001 + +#define QCLIB_INTERFACE_VERSION 0x00000001 +#define QCLIB_MAX_NUMBER_OF_ENTRIES 16 + +#define QCLIB_MAGIC_NUMBER "QCLIB_CB" + +struct qclib_cb_if_table { + char magic[8]; /* 0x00 */ + uint32_t version; /* 0x08 */ + uint32_t num_entries; /* 0x0C */ + uint32_t max_entries; /* 0x10 */ + uint32_t global_attributes; /* 0x14 */ + uint64_t reserved; /* 0x18 */ + struct qclib_cb_if_table_entry + te[QCLIB_MAX_NUMBER_OF_ENTRIES]; /* 0x20 */ +}; + +extern struct qclib_cb_if_table qclib_cb_if_table; + +void qclib_add_if_table_entry(const char *name, void *base, + uint32_t size, uint32_t attrs); +void qclib_load_and_run(void); +int qclib_soc_blob_load(void); + +#endif // _SOC_QUALCOMM_QCLIB_COMMON_H_ diff --git a/src/soc/qualcomm/common/include/soc/symbols_common.h b/src/soc/qualcomm/common/include/soc/symbols_common.h new file mode 100644 index 0000000000..ffa535c493 --- /dev/null +++ b/src/soc/qualcomm/common/include/soc/symbols_common.h @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_QUALCOMM_SYMBOLS_COMMON_H_ +#define _SOC_QUALCOMM_SYMBOLS_COMMON_H_ + +#include + +DECLARE_REGION(ddr_training); +DECLARE_REGION(qclib_serial_log); +DECLARE_REGION(ddr_information); + +#endif // _SOC_QUALCOMM_SYMBOLS_COMMON_H_ diff --git a/src/soc/qualcomm/common/mmu.c b/src/soc/qualcomm/common/mmu.c new file mode 100644 index 0000000000..79d2eb7271 --- /dev/null +++ b/src/soc/qualcomm/common/mmu.c @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +__weak void soc_mmu_dram_config_post_dram_init(void) { /* no-op */ } + +void qc_mmu_dram_config_post_dram_init(void *ddr_base, size_t ddr_size) +{ + mmu_config_range((void *)ddr_base, ddr_size, CACHED_RAM); + soc_mmu_dram_config_post_dram_init(); +} diff --git a/src/soc/qualcomm/common/qclib.c b/src/soc/qualcomm/common/qclib.c new file mode 100644 index 0000000000..1fd79b57b5 --- /dev/null +++ b/src/soc/qualcomm/common/qclib.c @@ -0,0 +1,227 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct qclib_cb_if_table qclib_cb_if_table = { + .magic = QCLIB_MAGIC_NUMBER, + .version = QCLIB_INTERFACE_VERSION, + .num_entries = 0, + .max_entries = QCLIB_MAX_NUMBER_OF_ENTRIES, + .global_attributes = 0, + .reserved = 0, +}; + +void qclib_add_if_table_entry(const char *name, void *base, + uint32_t size, uint32_t attrs) +{ + struct qclib_cb_if_table_entry *te = + &qclib_cb_if_table.te[qclib_cb_if_table.num_entries++]; + assert(qclib_cb_if_table.num_entries <= qclib_cb_if_table.max_entries); + strncpy(te->name, name, sizeof(te->name)); + te->blob_address = (uintptr_t)base; + te->size = size; + te->blob_attributes = attrs; +} + +static void write_ddr_information(struct qclib_cb_if_table_entry *te) +{ + uint64_t ddr_size; + + /* Save DDR info in SRAM region to share with ramstage */ + ddr_region->offset = te->blob_address; + ddr_size = te->size; + ddr_region->size = ddr_size * MiB; + + /* Use DDR info to configure MMU */ + qc_mmu_dram_config_post_dram_init((void *)ddr_region->offset, + (size_t)ddr_region->size); +} + +static void write_qclib_log_to_cbmemc(struct qclib_cb_if_table_entry *te) +{ + int i; + char *ptr = (char *)te->blob_address; + + for (i = 0; i < te->size; i++) + __cbmemc_tx_byte(*ptr++); +} + +static void write_table_entry(struct qclib_cb_if_table_entry *te) +{ + + if (!strncmp(QCLIB_TE_DDR_INFORMATION, te->name, + sizeof(te->name))) { + + write_ddr_information(te); + + } else if (!strncmp(QCLIB_TE_DDR_TRAINING_DATA, te->name, + sizeof(te->name))) { + + assert(fmap_overwrite_area(QCLIB_FR_DDR_TRAINING_DATA, + (const void *)te->blob_address, te->size)); + + } else if (!strncmp(QCLIB_TE_LIMITS_CFG_DATA, te->name, + sizeof(te->name))) { + + assert(fmap_overwrite_area(QCLIB_FR_LIMITS_CFG_DATA, + (const void *)te->blob_address, te->size)); + + } else if (!strncmp(QCLIB_TE_QCLIB_LOG_BUFFER, te->name, + sizeof(te->name))) { + + write_qclib_log_to_cbmemc(te); + + } else { + + printk(BIOS_WARNING, "%s write not implemented\n", te->name); + printk(BIOS_WARNING, " blob_address[%llx]..size[%x]\n", + te->blob_address, te->size); + + } +} + +static void dump_te_table(void) +{ + struct qclib_cb_if_table_entry *te; + int i; + + for (i = 0; i < qclib_cb_if_table.num_entries; i++) { + te = &qclib_cb_if_table.te[i]; + printk(BIOS_DEBUG, "[%s][%llx][%x][%x]\n", + te->name, te->blob_address, + te->size, te->blob_attributes); + } +} + +__weak int qclib_soc_blob_load(void) { return 0; } + +void qclib_load_and_run(void) +{ + int i; + ssize_t ssize; + struct mmu_context pre_qclib_mmu_context; + + /* zero ddr_information SRAM region, needs new data each boot */ + memset(ddr_region, 0, sizeof(struct region)); + + /* output area, QCLib copies console log buffer out */ + if (IS_ENABLED(CONFIG_CONSOLE_CBMEM)) + qclib_add_if_table_entry(QCLIB_TE_QCLIB_LOG_BUFFER, + _qclib_serial_log, + REGION_SIZE(qclib_serial_log), 0); + + /* output area, QCLib fills in DDR details */ + qclib_add_if_table_entry(QCLIB_TE_DDR_INFORMATION, NULL, 0, 0); + + /* Attempt to load DDR Training Blob */ + ssize = fmap_read_area(QCLIB_FR_DDR_TRAINING_DATA, _ddr_training, + REGION_SIZE(ddr_training)); + if (ssize < 0) + goto fail; + qclib_add_if_table_entry(QCLIB_TE_DDR_TRAINING_DATA, + _ddr_training, ssize, 0); + + /* hook for SoC specific binary blob loads */ + if (qclib_soc_blob_load()) { + printk(BIOS_ERR, "qclib_soc_blob_load failed\n"); + goto fail; + } + + /* Enable QCLib serial output, based on Kconfig */ + if (IS_ENABLED(CONFIG_CONSOLE_SERIAL)) + qclib_cb_if_table.global_attributes = + QCLIB_GA_ENABLE_UART_LOGGING; + + if (IS_ENABLED(CONFIG_QC_SDI_ENABLE)) { + struct prog qcsdi = + PROG_INIT(PROG_REFCODE, CONFIG_CBFS_PREFIX "/qcsdi"); + + /* Attempt to load QCSDI elf */ + if (prog_locate(&qcsdi)) + goto fail; + + if (cbfs_prog_stage_load(&qcsdi)) + goto fail; + + qclib_add_if_table_entry(QCLIB_TE_QCSDI, prog_entry(&qcsdi), + prog_size(&qcsdi), 0); + printk(BIOS_INFO, "qcsdi.entry[%p]\n", qcsdi.entry); + } + + dump_te_table(); + + /* Attempt to load QCLib elf */ + struct prog qclib = + PROG_INIT(PROG_REFCODE, CONFIG_CBFS_PREFIX "/qclib"); + + if (prog_locate(&qclib)) + goto fail; + + if (cbfs_prog_stage_load(&qclib)) + goto fail; + + prog_set_entry(&qclib, prog_entry(&qclib), &qclib_cb_if_table); + + printk(BIOS_DEBUG, "\n\n\nQCLib is about to Initialize DDR\n"); + printk(BIOS_DEBUG, "Global Attributes[%x]..Table Entries Count[%d]\n", + qclib_cb_if_table.global_attributes, + qclib_cb_if_table.num_entries); + printk(BIOS_DEBUG, "Jumping to QCLib code at %p(%p)\n", + prog_entry(&qclib), prog_entry_arg(&qclib)); + + /* back-up mmu context before disabling mmu and executing qclib */ + mmu_save_context(&pre_qclib_mmu_context); + /* disable mmu before jumping to qclib. mmu_disable also + flushes and invalidates caches before disabling mmu. */ + mmu_disable(); + + prog_run(&qclib); + + /* Before returning, QCLib flushes cache and disables mmu. + Explicitly disable mmu (flush, invalidate and disable mmu) + before re-enabling mmu with backed-up mmu context */ + mmu_disable(); + mmu_restore_context(&pre_qclib_mmu_context); + mmu_enable(); + + /* step through I/F table, handling return values */ + for (i = 0; i < qclib_cb_if_table.num_entries; i++) + if (qclib_cb_if_table.te[i].blob_attributes & + QCLIB_BA_SAVE_TO_STORAGE) + write_table_entry(&qclib_cb_if_table.te[i]); + + /* confirm that we received valid ddr information from QCLib */ + assert((uintptr_t)_dram == region_offset(ddr_region) && + region_sz(ddr_region) >= (u8 *)cbmem_top() - _dram); + + printk(BIOS_DEBUG, "QCLib completed\n\n\n"); + + return; + +fail: + die("Couldn't run QCLib.\n"); +} diff --git a/src/soc/qualcomm/ipq40xx/Kconfig b/src/soc/qualcomm/ipq40xx/Kconfig index 72e05faf22..90744d5285 100644 --- a/src/soc/qualcomm/ipq40xx/Kconfig +++ b/src/soc/qualcomm/ipq40xx/Kconfig @@ -47,7 +47,7 @@ config SBL_ELF config SBL_UTIL_PATH depends on USE_BLOBS string "Path for utils to combine SBL_ELF and bootblock" - default "util/ipqheader" + default "util/qualcomm" help Path for utils to combine SBL_ELF and bootblock diff --git a/src/soc/qualcomm/ipq40xx/mbn_header.h b/src/soc/qualcomm/ipq40xx/mbn_header.h index cedcf12584..a48de1c883 100644 --- a/src/soc/qualcomm/ipq40xx/mbn_header.h +++ b/src/soc/qualcomm/ipq40xx/mbn_header.h @@ -18,7 +18,7 @@ #include -/* QCA firmware blob header gleaned from util/ipqheader/ipqheader.py */ +/* QCA firmware blob header gleaned from util/qualcomm/ipqheader.py */ struct mbn_header { u32 mbn_type; diff --git a/src/soc/qualcomm/ipq40xx/qup.c b/src/soc/qualcomm/ipq40xx/qup.c index 9d1f92d48a..438bd14757 100644 --- a/src/soc/qualcomm/ipq40xx/qup.c +++ b/src/soc/qualcomm/ipq40xx/qup.c @@ -478,8 +478,7 @@ qup_return_t qup_set_state(blsp_qup_id_t id, uint32_t state) qup_return_t ret = QUP_ERR_UNDEFINED; unsigned curr_state = read32(QUP_ADDR(id, QUP_STATE)); - if ((state >= QUP_STATE_RESET && state <= QUP_STATE_PAUSE) - && (curr_state & QUP_STATE_VALID_MASK)) { + if (state <= QUP_STATE_PAUSE && (curr_state & QUP_STATE_VALID_MASK)) { /* * For PAUSE_STATE to RESET_STATE transition, * two writes of 10[binary]) are required for the diff --git a/src/soc/qualcomm/ipq40xx/spi.c b/src/soc/qualcomm/ipq40xx/spi.c index 109eda9fc0..b68e1cb864 100644 --- a/src/soc/qualcomm/ipq40xx/spi.c +++ b/src/soc/qualcomm/ipq40xx/spi.c @@ -648,8 +648,8 @@ static int spi_ctrlr_setup(const struct spi_slave *slave) { struct ipq_spi_slave *ds = NULL; int i; - unsigned int bus = slave->bus; - unsigned int cs = slave->cs; + int bus = slave->bus; + int cs = slave->cs; if ((bus < BLSP0_SPI) || (bus > BLSP1_SPI) || ((bus == BLSP0_SPI) && (cs > 2)) diff --git a/src/soc/qualcomm/ipq806x/Makefile.inc b/src/soc/qualcomm/ipq806x/Makefile.inc index 8a428b2f0d..1fd134a7b3 100644 --- a/src/soc/qualcomm/ipq806x/Makefile.inc +++ b/src/soc/qualcomm/ipq806x/Makefile.inc @@ -62,14 +62,14 @@ ifeq ($(CONFIG_USE_BLOBS),y) # Add MBN header to allow SBL3 to start coreboot bootblock $(objcbfs)/bootblock.mbn: $(objcbfs)/bootblock.raw.bin @printf " ADD MBN $(subst $(obj)/,,$(@))\n" - ./util/ipqheader/ipqheader.py $(call loadaddr,bootblock) $< $@.tmp + ./util/qualcomm/ipqheader.py $(call loadaddr,bootblock) $< $@.tmp @mv $@.tmp $@ # Create a complete bootblock which will start up the system $(objcbfs)/bootblock.bin: $(call strip_quotes,$(CONFIG_SBL_BLOB)) \ $(objcbfs)/bootblock.mbn @printf " MBNCAT $(subst $(obj)/,,$(@))\n" - @util/ipqheader/mbncat.py -o $@.tmp $^ + @util/qualcomm/mbncat.py -o $@.tmp $^ @mv $@.tmp $@ endif diff --git a/src/soc/qualcomm/ipq806x/mbn_header.h b/src/soc/qualcomm/ipq806x/mbn_header.h index 1e6a32f732..c7b38d3a81 100644 --- a/src/soc/qualcomm/ipq806x/mbn_header.h +++ b/src/soc/qualcomm/ipq806x/mbn_header.h @@ -18,7 +18,7 @@ #include -/* Qualcomm firmware blob header gleaned from util/ipqheader/ipqheader.py */ +/* Qualcomm firmware blob header gleaned from util/qualcomm/ipqheader.py */ struct mbn_header { u32 mbn_type; diff --git a/src/soc/qualcomm/ipq806x/qup.c b/src/soc/qualcomm/ipq806x/qup.c index 872b264cfa..3ceb84d881 100644 --- a/src/soc/qualcomm/ipq806x/qup.c +++ b/src/soc/qualcomm/ipq806x/qup.c @@ -379,8 +379,7 @@ qup_return_t qup_set_state(gsbi_id_t gsbi_id, uint32_t state) qup_return_t ret = QUP_ERR_UNDEFINED; unsigned curr_state = read32(QUP_ADDR(gsbi_id, QUP_STATE)); - if ((state >= QUP_STATE_RESET && state <= QUP_STATE_PAUSE) - && (curr_state & QUP_STATE_VALID_MASK)) { + if (state <= QUP_STATE_PAUSE && (curr_state & QUP_STATE_VALID_MASK)) { /* * For PAUSE_STATE to RESET_STATE transition, * two writes of 10[binary]) are required for the diff --git a/src/soc/qualcomm/ipq806x/spi.c b/src/soc/qualcomm/ipq806x/spi.c index 657734524c..2657b9c574 100644 --- a/src/soc/qualcomm/ipq806x/spi.c +++ b/src/soc/qualcomm/ipq806x/spi.c @@ -760,8 +760,8 @@ static int spi_ctrlr_setup(const struct spi_slave *slave) { struct ipq_spi_slave *ds = NULL; int i; - unsigned int bus = slave->bus; - unsigned int cs = slave->cs; + int bus = slave->bus; + int cs = slave->cs; /* * IPQ GSBI (Generic Serial Bus Interface) supports SPI Flash diff --git a/src/soc/qualcomm/sdm845/Kconfig b/src/soc/qualcomm/sdm845/Kconfig index ba064889f0..ffb95cb4cd 100644 --- a/src/soc/qualcomm/sdm845/Kconfig +++ b/src/soc/qualcomm/sdm845/Kconfig @@ -18,6 +18,7 @@ config VBOOT select VBOOT_RETURN_FROM_VERSTAGE select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_STARTS_IN_BOOTBLOCK + select VBOOT_MIGRATE_WORKING_DATA config SDM845_QSPI bool diff --git a/src/soc/qualcomm/sdm845/Makefile.inc b/src/soc/qualcomm/sdm845/Makefile.inc index 896ae58e5f..78b3568a8b 100644 --- a/src/soc/qualcomm/sdm845/Makefile.inc +++ b/src/soc/qualcomm/sdm845/Makefile.inc @@ -24,6 +24,11 @@ romstage-y += timer.c romstage-y += gpio.c romstage-y += clock.c romstage-$(CONFIG_SDM845_QSPI) += qspi.c +romstage-y += usb.c +romstage-y += ../common/qclib.c +romstage-y += qclib.c +romstage-y += ../common/mmu.c +romstage-y += mmu.c ################################################################################ ramstage-y += soc.c @@ -33,10 +38,12 @@ ramstage-y += timer.c ramstage-y += gpio.c ramstage-y += clock.c ramstage-$(CONFIG_SDM845_QSPI) += qspi.c +ramstage-y += usb.c ################################################################################ CPPFLAGS_common += -Isrc/soc/qualcomm/sdm845/include +CPPFLAGS_common += -Isrc/soc/qualcomm/common/include $(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin @printf "Generating: $(subst $(obj)/,,$(@))\n" diff --git a/src/soc/qualcomm/sdm845/include/soc/addressmap.h b/src/soc/qualcomm/sdm845/include/soc/addressmap.h index 5a94e23e96..bf4b30b32b 100644 --- a/src/soc/qualcomm/sdm845/include/soc/addressmap.h +++ b/src/soc/qualcomm/sdm845/include/soc/addressmap.h @@ -25,4 +25,23 @@ #define GCC_BASE 0x00100000 #define AOSS_CC_BASE 0x0C2F0000 +/* + * USB BASE ADDRESSES + */ +#define QFPROM_BASE 0x00780000 +#define QUSB_PRIM_PHY_BASE 0x088e2000 +#define QUSB_PRIM_PHY_DIG_BASE 0x088e2200 +#define QUSB_SEC_PHY_BASE 0x088e3000 +#define QUSB_SEC_PHY_DIG_BASE 0x088e3200 +#define QMP_PHY_QSERDES_COM_REG_BASE 0x088e9000 +#define QMP_PHY_QSERDES_TX_REG_BASE 0x088e9200 +#define QMP_PHY_QSERDES_RX_REG_BASE 0x088e9400 +#define QMP_PHY_PCS_REG_BASE 0x088e9c00 +#define QMP_UNIPHY_QSERDES_COM_REG_BASE 0x088eb000 +#define QMP_UNIPHY_QSERDES_TX_REG_BASE 0x088eb200 +#define QMP_UNIPHY_QSERDES_RX_REG_BASE 0x088eb400 +#define QMP_UNIPHY_PCS_REG_BASE 0x088eb800 +#define USB_HOST0_DWC3_BASE 0x0a60c100 +#define USB_HOST1_DWC3_BASE 0x0a80c100 + #endif /* __SOC_QUALCOMM_SDM845_ADDRESS_MAP_H__ */ diff --git a/src/soc/qualcomm/sdm845/include/soc/clock.h b/src/soc/qualcomm/sdm845/include/soc/clock.h index 9f0533f33f..6aee9c14f3 100644 --- a/src/soc/qualcomm/sdm845/include/soc/clock.h +++ b/src/soc/qualcomm/sdm845/include/soc/clock.h @@ -74,7 +74,14 @@ struct sdm845_gpll { struct sdm845_gcc { struct sdm845_gpll gpll0; - u8 _res0[0x17000 - 0x1000]; + u8 _res0[0xf000 - 0x1000]; + u32 usb30_prim_bcr; + u8 _res1[0x10000 - 0xf004]; + u32 usb30_sec_bcr; + u8 _res2[0x12000 - 0x10004]; + u32 qusb2phy_prim_bcr; + u32 qusb2phy_sec_bcr; + u8 _res3[0x17000 - 0x12008]; u32 qup_wrap0_bcr; u32 qup_wrap0_m_ahb_cbcr; u32 qup_wrap0_s_ahb_cbcr; @@ -82,9 +89,9 @@ struct sdm845_gcc { u32 qup_wrap0_core_cdivr; u32 qup_wrap0_core_2x_cbcr; struct sdm845_rcg qup_wrap0_core_2x; - u8 _res1[0x17030 - 0x17020]; + u8 _res4[0x17030 - 0x17020]; struct sdm845_qupv3_clock qup_wrap0_s[8]; - u8 _res2[0x18000 - 0x179b0]; + u8 _res5[0x18000 - 0x179b0]; u32 qup_wrap1_bcr; u32 qup_wrap1_core_2x_cbcr; u32 qup_wrap1_core_cbcr; @@ -92,14 +99,28 @@ struct sdm845_gcc { u32 qup_wrap1_s_ahb_cbcr; struct sdm845_qupv3_clock qup_wrap1_s[8]; u32 qup_wrap1_core_cdivr; - u8 _res4[0x4B000 - 0x18998]; + u8 _res6[0x4B000 - 0x18998]; u32 qspi_cnoc_ahb_cbcr; u32 qspi_core_cbcr; struct sdm845_rcg qspi_core; - u8 _res5[0x5200c-0x4b010]; + u8 _res7[0x50000-0x4b010]; + u32 usb3_phy_prim_bcr; + u32 usb3phy_phy_prim_bcr; + u32 usb3_dp_phy_prim_bcr; + u32 usb3_phy_sec_bcr; + u32 usb3phy_phy_sec_bcr; + u8 _res8[0x5200c-0x50014]; u32 apcs_clk_br_en1; - u8 _res6[0x1000000-0x52010]; + u8 _res9[0x1000000-0x52010]; }; +check_member(sdm845_gcc, usb30_prim_bcr, 0xf000); +check_member(sdm845_gcc, usb30_sec_bcr, 0x10000); +check_member(sdm845_gcc, qusb2phy_prim_bcr, 0x12000); +check_member(sdm845_gcc, qusb2phy_sec_bcr, 0x12004); +check_member(sdm845_gcc, usb3phy_phy_prim_bcr, 0x50004); +check_member(sdm845_gcc, usb3_phy_prim_bcr, 0x50000); +check_member(sdm845_gcc, usb3_phy_sec_bcr, 0x5000c); +check_member(sdm845_gcc, usb3phy_phy_sec_bcr, 0x50010); check_member(sdm845_gcc, apcs_clk_br_en1, 0x5200c); struct sdm845_aoss { diff --git a/src/soc/qualcomm/sdm845/include/soc/efuse.h b/src/soc/qualcomm/sdm845/include/soc/efuse.h new file mode 100644 index 0000000000..309193cf43 --- /dev/null +++ b/src/soc/qualcomm/sdm845/include/soc/efuse.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2018 Qualcomm Technologies + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_QUALCOMM_SDM845_EFUSE_ADDRESS_MAP_H__ +#define __SOC_QUALCOMM_SDM845_EFUSE_ADDRESS_MAP_H__ + +/** + * USB EFUSE registers + */ +struct qfprom_corr { + u8 rsvd[0x41E8 - 0x0]; + u32 qusb_hstx_trim_lsb; + u32 qusb_hstx_trim_msb; +}; + +check_member(qfprom_corr, qusb_hstx_trim_lsb, 0x41E8); +check_member(qfprom_corr, qusb_hstx_trim_msb, 0x41EC); +#endif /* __SOC_QUALCOMM_SDM845_EFUSE_ADDRESS_MAP_H__ */ diff --git a/src/soc/qualcomm/sdm845/include/soc/memlayout.ld b/src/soc/qualcomm/sdm845/include/soc/memlayout.ld index 7063c6910e..b1b633317f 100644 --- a/src/soc/qualcomm/sdm845/include/soc/memlayout.ld +++ b/src/soc/qualcomm/sdm845/include/soc/memlayout.ld @@ -28,11 +28,12 @@ SECTIONS { SSRAM_START(0x14680000) OVERLAP_VERSTAGE_ROMSTAGE(0x14680000, 100K) - DMA_COHERENT(0x14699000, 0x2000) + DMA_COHERENT(0x14699000, 8K) + REGION(qcsdi, 0x146AC000, 44K, 4K) SSRAM_END(0x146C0000) BSRAM_START(0x14800000) - REGION(fw_reserved2, 0x14800000, 0x16000, 4096) + REGION(fw_reserved2, 0x14800000, 0x16000, 0x1000) BOOTBLOCK(0x14816000, 40K) TTB(0x14820000, 56K) VBOOT2_WORK(0x1482E000, 12K) @@ -40,15 +41,19 @@ SECTIONS TIMESTAMP(0x14836000, 1K) PRERAM_CBMEM_CONSOLE(0x14836400, 32K) PRERAM_CBFS_CACHE(0x1483E400, 70K) - REGION(bsram_unused, 0x1484FC00, 0xA2400, 0x100) - REGION(qclib, 0x148F2000, 0x80000, 4096) - REGION(dcb, 0x14972000, 0x4000, 4096) - REGION(pmic, 0x14976000, 0xA000, 4096) + REGION(bsram_unused, 0x1484FC00, 0x9E300, 0x100) + REGION(ddr_information, 0x148EDF00, 256, 256) + REGION(limits_cfg, 0x148EE000, 4K, 4K) + REGION(qclib_serial_log, 0x148EF000, 4K, 4K) + REGION(ddr_training, 0x148F0000, 8K, 4K) + REGION(qclib, 0x148F2000, 512K, 4K) + REGION(dcb, 0x14972000, 16K, 4K) + REGION(pmic, 0x14976000, 40K, 4K) BSRAM_END(0x14980000) DRAM_START(0x80000000) /* Various hardware/software subsystems make use of this area */ - REGION(dram_reserved, 0x85000000, 0x1A800000, 4096) + REGION(dram_reserved, 0x85000000, 0x1A800000, 0x1000) POSTRAM_CBFS_CACHE(0x9F800000, 384K) - RAMSTAGE(0x9F860000, 128K) + RAMSTAGE(0x9F860000, 2M) } diff --git a/src/soc/qualcomm/sdm845/include/soc/mmu.h b/src/soc/qualcomm/sdm845/include/soc/mmu.h index 299700a63f..c9883bc0bf 100644 --- a/src/soc/qualcomm/sdm845/include/soc/mmu.h +++ b/src/soc/qualcomm/sdm845/include/soc/mmu.h @@ -16,8 +16,6 @@ #ifndef _SOC_QUALCOMM_SDM845_MMU_H__ #define _SOC_QUALCOMM_SDM845_MMU_H__ -#define DRAMSIZE4GB 0x100000000 - void sdm845_mmu_init(void); #endif // _SOC_QUALCOMM_SDM845_MMU_H_ diff --git a/src/soc/qualcomm/sdm845/include/soc/symbols.h b/src/soc/qualcomm/sdm845/include/soc/symbols.h index 1c14c03d01..e7bf1b2aea 100644 --- a/src/soc/qualcomm/sdm845/include/soc/symbols.h +++ b/src/soc/qualcomm/sdm845/include/soc/symbols.h @@ -17,10 +17,12 @@ #define _SOC_QUALCOMM_SDM845_SYMBOLS_H_ #include -#include DECLARE_REGION(ssram) DECLARE_REGION(bsram) DECLARE_REGION(dram_reserved) +DECLARE_REGION(dcb); +DECLARE_REGION(pmic); +DECLARE_REGION(limits_cfg); #endif // _SOC_QUALCOMM_SDM845_SYMBOLS_H_ diff --git a/src/soc/qualcomm/sdm845/include/soc/usb.h b/src/soc/qualcomm/sdm845/include/soc/usb.h new file mode 100644 index 0000000000..b657676763 --- /dev/null +++ b/src/soc/qualcomm/sdm845/include/soc/usb.h @@ -0,0 +1,96 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2018 Qualcomm Technologies + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include + +#ifndef _SDM845_USB_H_ +#define _SDM845_USB_H_ + +/* QSCRATCH_GENERAL_CFG register bit offset */ +#define PIPE_UTMI_CLK_SEL BIT(0) +#define PIPE3_PHYSTATUS_SW BIT(3) +#define PIPE_UTMI_CLK_DIS BIT(8) + +/* Global USB3 Control Registers */ +#define DWC3_GUSB3PIPECTL_DELAYP1TRANS BIT(18) +#define DWC3_GUSB3PIPECTL_UX_EXIT_IN_PX BIT(27) +#define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12) +#define DWC3_GCTL_PRTCAP_OTG 3 +#define DWC3_GCTL_PRTCAP_HOST 1 + +/* Global USB2 PHY Configuration Register */ +#define DWC3_GUSB2PHYCFG_USBTRDTIM(n) ((n) << 10) +#define DWC3_GUSB2PHYCFG_USB2TRDTIM_MASK DWC3_GUSB2PHYCFG_USBTRDTIM(0xf) +#define DWC3_GUSB2PHYCFG_PHYIF(n) ((n) << 3) +#define DWC3_GUSB2PHYCFG_PHYIF_MASK DWC3_GUSB2PHYCFG_PHYIF(1) +#define USBTRDTIM_UTMI_8_BIT 9 +#define UTMI_PHYIF_8_BIT 0 + +#define DWC3_GCTL_SCALEDOWN(n) ((n) << 4) +#define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3) +#define DWC3_GCTL_DISSCRAMBLE (1 << 3) +#define DWC3_GCTL_U2EXIT_LFPS (1 << 2) +#define DWC3_GCTL_DSBLCLKGTNG (1 << 0) + +#define PORT_TUNE1_MASK 0xf0 + +/* QUSB2PHY_PWR_CTRL1 register related bits */ +#define POWER_DOWN BIT(0) + +/* DEBUG_CTRL2 register value to program VSTATUS MUX for PHY status */ +#define DEBUG_CTRL2_MUX_PLL_LOCK_STATUS 0x4 + +/* STAT5 register bits */ +#define VSTATUS_PLL_LOCK_STATUS_MASK BIT(0) + +/* QUSB PHY register values */ +#define QUSB2PHY_PLL_ANALOG_CONTROLS_TWO 0x03 +#define QUSB2PHY_PLL_CLOCK_INVERTERS 0x7c +#define QUSB2PHY_PLL_CMODE 0x80 +#define QUSB2PHY_PLL_LOCK_DELAY 0x0a +#define QUSB2PHY_PLL_DIGITAL_TIMERS_TWO 0x19 +#define QUSB2PHY_PLL_BIAS_CONTROL_1 0x40 +#define QUSB2PHY_PLL_BIAS_CONTROL_2 0x20 +#define QUSB2PHY_PWR_CTRL2 0x21 +#define QUSB2PHY_IMP_CTRL1 0x0 +#define QUSB2PHY_IMP_CTRL2 0x58 +#define QUSB2PHY_PORT_TUNE1 0x30 +#define QUSB2PHY_PORT_TUNE2 0x29 +#define QUSB2PHY_PORT_TUNE3 0xca +#define QUSB2PHY_PORT_TUNE4 0x04 +#define QUSB2PHY_PORT_TUNE5 0x03 +#define QUSB2PHY_CHG_CTRL2 0x0 + +/* USB3PHY_PCIE_USB3_PCS_PCS_STATUS bit */ +#define USB3_PCS_PHYSTATUS BIT(6) + +struct usb_board_data { + /* Register values going to override from the boardfile */ + u32 pll_bias_control_2; + u32 imp_ctrl1; + u32 port_tune1; +}; + +struct qmp_phy_init_tbl { + u32 *address; + u32 val; +}; + +void setup_usb_host0(struct usb_board_data *data); +void setup_usb_host1(struct usb_board_data *data); +/* Call reset_ before setup_ */ +void reset_usb0(void); +void reset_usb1(void); + +#endif /* _SDM845_USB_H_ */ diff --git a/src/soc/qualcomm/sdm845/mmu.c b/src/soc/qualcomm/sdm845/mmu.c index ef6c058ab3..ec5fa55de2 100644 --- a/src/soc/qualcomm/sdm845/mmu.c +++ b/src/soc/qualcomm/sdm845/mmu.c @@ -17,12 +17,9 @@ #include #include #include +#include #include -#define CACHED_RAM (MA_MEM | MA_S | MA_RW) -#define UNCACHED_RAM (MA_MEM | MA_S | MA_RW | MA_MEM_NC) -#define DEV_MEM (MA_DEV | MA_S | MA_RW) - void sdm845_mmu_init(void) { mmu_init(); diff --git a/src/soc/qualcomm/sdm845/qclib.c b/src/soc/qualcomm/sdm845/qclib.c new file mode 100644 index 0000000000..9c05452c9e --- /dev/null +++ b/src/soc/qualcomm/sdm845/qclib.c @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include + +int qclib_soc_blob_load(void) +{ + size_t size; + ssize_t ssize; + + /* Attempt to load PMICCFG Blob */ + size = cbfs_boot_load_file(CONFIG_CBFS_PREFIX "/pmiccfg", + _pmic, REGION_SIZE(pmic), CBFS_TYPE_RAW); + if (!size) + return -1; + qclib_add_if_table_entry(QCLIB_TE_PMIC_SETTINGS, _pmic, size, 0); + + /* Attempt to load DCB Blob */ + size = cbfs_boot_load_file(CONFIG_CBFS_PREFIX "/dcb", + _dcb, REGION_SIZE(dcb), CBFS_TYPE_RAW); + if (!size) + return -1; + qclib_add_if_table_entry(QCLIB_TE_DCB_SETTINGS, _dcb, size, 0); + + /* Attempt to load Limits Config Blob */ + ssize = fmap_read_area(QCLIB_FR_LIMITS_CFG_DATA, _limits_cfg, + REGION_SIZE(limits_cfg)); + if (ssize < 0) + return -1; + qclib_add_if_table_entry(QCLIB_TE_LIMITS_CFG_DATA, + _limits_cfg, ssize, 0); + + return 0; +} diff --git a/src/soc/qualcomm/sdm845/soc.c b/src/soc/qualcomm/sdm845/soc.c index bc7235f3ed..ef283c0eae 100644 --- a/src/soc/qualcomm/sdm845/soc.c +++ b/src/soc/qualcomm/sdm845/soc.c @@ -16,11 +16,13 @@ #include #include #include +#include #include static void soc_read_resources(struct device *dev) { - ram_resource(dev, 0, (uintptr_t)_dram / KiB, DRAMSIZE4GB / KiB); + ram_resource(dev, 0, (uintptr_t)ddr_region->offset / KiB, + ddr_region->size / KiB); reserved_ram_resource(dev, 1, (uintptr_t)_dram_reserved / KiB, REGION_SIZE(dram_reserved) / KiB); } diff --git a/src/soc/qualcomm/sdm845/usb.c b/src/soc/qualcomm/sdm845/usb.c new file mode 100644 index 0000000000..c7d65e6b42 --- /dev/null +++ b/src/soc/qualcomm/sdm845/usb.c @@ -0,0 +1,915 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2018 Qualcomm Technologies + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct usb_qusb_phy_dig { + u8 rsvd1[16]; + u32 pwr_ctrl1; + u32 pwr_ctrl2; + u8 rsvd2[8]; + u32 imp_ctrl1; + u32 imp_ctrl2; + u8 rsvd3[20]; + u32 chg_ctrl2; + u32 tune1; + u32 tune2; + u32 tune3; + u32 tune4; + u32 tune5; + u8 rsvd4[44]; + u32 debug_ctrl2; + u8 rsvd5[28]; + u32 debug_stat5; +}; +check_member(usb_qusb_phy_dig, tune5, 0x50); +check_member(usb_qusb_phy_dig, debug_ctrl2, 0x80); +check_member(usb_qusb_phy_dig, debug_stat5, 0xA0); + +struct usb_qusb_phy_pll { + u8 rsvd0[4]; + u32 analog_controls_two; + u8 rsvd1[36]; + u32 cmode; + u8 rsvd2[132]; + u32 dig_tim; + u8 rsvd3[204]; + u32 lock_delay; + u8 rsvd4[4]; + u32 clock_inverters; + u8 rsvd5[4]; + u32 bias_ctrl_1; + u32 bias_ctrl_2; +}; +check_member(usb_qusb_phy_pll, cmode, 0x2C); +check_member(usb_qusb_phy_pll, bias_ctrl_2, 0x198); +check_member(usb_qusb_phy_pll, dig_tim, 0xB4); + +/* Only for QMP V3 PHY - QSERDES COM registers */ +struct usb3_phy_qserdes_com_reg_layout { + u8 _reserved1[16]; + u32 com_ssc_en_center; + u32 com_ssc_adj_per1; + u32 com_ssc_adj_per2; + u32 com_ssc_per1; + u32 com_ssc_per2; + u32 com_ssc_step_size1; + u32 com_ssc_step_size2; + u8 _reserved2[8]; + u32 com_bias_en_clkbuflr_en; + u32 com_sys_clk_enable1; + u32 com_sys_clk_ctrl; + u32 com_sysclk_buf_enable; + u32 com_pll_en; + u32 com_pll_ivco; + u8 _reserved3[20]; + u32 com_cp_ctrl_mode0; + u8 _reserved4[4]; + u32 com_pll_rctrl_mode0; + u8 _reserved5[4]; + u32 com_pll_cctrl_mode0; + u8 _reserved6[12]; + u32 com_sysclk_en_sel; + u8 _reserved7[8]; + u32 com_resetsm_ctrl2; + u32 com_lock_cmp_en; + u32 com_lock_cmp_cfg; + u32 com_lock_cmp1_mode0; + u32 com_lock_cmp2_mode0; + u32 com_lock_cmp3_mode0; + u8 _reserved8[12]; + u32 com_dec_start_mode0; + u8 _reserved9[4]; + u32 com_div_frac_start1_mode0; + u32 com_div_frac_start2_mode0; + u32 com_div_frac_start3_mode0; + u8 _reserved10[20]; + u32 com_integloop_gain0_mode0; + u32 com_integloop_gain1_mode0; + u8 _reserved11[16]; + u32 com_vco_tune_map; + u32 com_vco_tune1_mode0; + u32 com_vco_tune2_mode0; + u8 _reserved12[60]; + u32 com_clk_select; + u32 com_hsclk_sel; + u8 _reserved13[8]; + u32 com_coreclk_div_mode0; + u8 _reserved14[8]; + u32 com_core_clk_en; + u32 com_c_ready_status; + u32 com_cmn_config; + u32 com_cmn_rate_override; + u32 com_svs_mode_clk_sel; +}; +check_member(usb3_phy_qserdes_com_reg_layout, com_ssc_en_center, 0x010); +check_member(usb3_phy_qserdes_com_reg_layout, com_ssc_adj_per1, 0x014); +check_member(usb3_phy_qserdes_com_reg_layout, com_ssc_adj_per2, 0x018); +check_member(usb3_phy_qserdes_com_reg_layout, com_ssc_per1, 0x01c); +check_member(usb3_phy_qserdes_com_reg_layout, com_ssc_per2, 0x020); +check_member(usb3_phy_qserdes_com_reg_layout, com_bias_en_clkbuflr_en, 0x034); +check_member(usb3_phy_qserdes_com_reg_layout, com_pll_ivco, 0x048); +check_member(usb3_phy_qserdes_com_reg_layout, com_cp_ctrl_mode0, 0x060); +check_member(usb3_phy_qserdes_com_reg_layout, com_sysclk_en_sel, 0x080); +check_member(usb3_phy_qserdes_com_reg_layout, com_resetsm_ctrl2, 0x08c); +check_member(usb3_phy_qserdes_com_reg_layout, com_dec_start_mode0, 0x0b0); +check_member(usb3_phy_qserdes_com_reg_layout, com_div_frac_start1_mode0, 0x0b8); +check_member(usb3_phy_qserdes_com_reg_layout, com_integloop_gain0_mode0, 0x0d8); +check_member(usb3_phy_qserdes_com_reg_layout, com_vco_tune_map, 0x0f0); +check_member(usb3_phy_qserdes_com_reg_layout, com_clk_select, 0x138); +check_member(usb3_phy_qserdes_com_reg_layout, com_coreclk_div_mode0, 0x148); +check_member(usb3_phy_qserdes_com_reg_layout, com_core_clk_en, 0x154); +check_member(usb3_phy_qserdes_com_reg_layout, com_svs_mode_clk_sel, 0x164); + +/* Only for QMP V3 PHY - TX registers */ +struct usb3_phy_qserdes_tx_reg_layout { + u8 _reserved1[68]; + u32 tx_res_code_lane_offset_tx; + u32 tx_res_code_lane_offset_rx; + u8 _reserved2[20]; + u32 tx_highz_drvr_en; + u8 _reserved3[40]; + u32 tx_lane_mode_1; + u8 _reserved4[20]; + u32 tx_rcv_detect_lvl_2; +}; +check_member(usb3_phy_qserdes_tx_reg_layout, tx_res_code_lane_offset_tx, 0x044); +check_member(usb3_phy_qserdes_tx_reg_layout, tx_res_code_lane_offset_rx, 0x048); +check_member(usb3_phy_qserdes_tx_reg_layout, tx_highz_drvr_en, 0x060); +check_member(usb3_phy_qserdes_tx_reg_layout, tx_lane_mode_1, 0x08c); +check_member(usb3_phy_qserdes_tx_reg_layout, tx_rcv_detect_lvl_2, 0x0a4); + +/* Only for QMP V3 PHY - RX registers */ +struct usb3_phy_qserdes_rx_reg_layout { + u8 _reserved1[8]; + u32 rx_ucdr_fo_gain; + u32 rx_ucdr_so_gain_half; + u8 _reserved2[32]; + u32 rx_ucdr_fastlock_fo_gain; + u32 rx_ucdr_so_saturtn_and_en; + u8 _reserved3[12]; + u32 rx_ucdr_pi_cntrls; + u8 _reserved4[120]; + u32 rx_vga_cal_ctrl2; + u8 _reserved5[16]; + u32 rx_rx_equ_adap_ctrl2; + u32 rx_rx_equ_adap_ctrl3; + u32 rx_rx_equ_adap_ctrl4; + u8 _reserved6[24]; + u32 rx_rx_eq_offset_adap_ctrl1; + u32 rx_rx_offset_adap_ctrl2; + u32 rx_sigdet_enables; + u32 rx_sigdet_ctrl; + u8 _reserved7[4]; + u32 rx_sigdet_deglitch_ctrl; + u32 rx_rx_band; + u8 _reserved8[80]; + u32 rx_rx_mode_00; +}; +check_member(usb3_phy_qserdes_rx_reg_layout, rx_ucdr_fo_gain, 0x008); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_ucdr_so_gain_half, 0x00c); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_ucdr_fastlock_fo_gain, 0x030); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_ucdr_so_saturtn_and_en, 0x034); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_ucdr_pi_cntrls, 0x044); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_vga_cal_ctrl2, 0x0c0); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_rx_equ_adap_ctrl2, 0x0d4); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_rx_equ_adap_ctrl3, 0x0d8); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_rx_equ_adap_ctrl4, 0x0dc); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_rx_eq_offset_adap_ctrl1, 0x0f8); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_rx_offset_adap_ctrl2, 0x0fc); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_sigdet_enables, 0x100); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_sigdet_ctrl, 0x104); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_sigdet_deglitch_ctrl, 0x10c); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_rx_band, 0x110); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_rx_mode_00, 0x164); + +/* Only for QMP V3 PHY - PCS registers */ +struct usb3_phy_pcs_reg_layout { + u32 pcs_sw_reset; + u32 pcs_power_down_control; + u32 pcs_start_control; + u32 pcs_txmgn_v0; + u32 pcs_txmgn_v1; + u32 pcs_txmgn_v2; + u32 pcs_txmgn_v3; + u32 pcs_txmgn_v4; + u32 pcs_txmgn_ls; + u32 pcs_txdeemph_m6db_v0; + u32 pcs_txdeemph_m3p5db_v0; + u32 pcs_txdeemph_m6db_v1; + u32 pcs_txdeemph_m3p5db_v1; + u32 pcs_txdeemph_m6db_v2; + u32 pcs_txdeemph_m3p5db_v2; + u32 pcs_txdeemph_m6db_v3; + u32 pcs_txdeemph_m3p5db_v3; + u32 pcs_txdeemph_m6db_v4; + u32 pcs_txdeemph_m3p5db_v4; + u32 pcs_txdeemph_m6db_ls; + u32 pcs_txdeemph_m3p5db_ls; + u8 _reserved1[8]; + u32 pcs_rate_slew_cntrl; + u8 _reserved2[4]; + u32 pcs_power_state_config2; + u8 _reserved3[8]; + u32 pcs_rcvr_dtct_dly_p1u2_l; + u32 pcs_rcvr_dtct_dly_p1u2_h; + u32 pcs_rcvr_dtct_dly_u3_l; + u32 pcs_rcvr_dtct_dly_u3_h; + u32 pcs_lock_detect_config1; + u32 pcs_lock_detect_config2; + u32 pcs_lock_detect_config3; + u32 pcs_tsync_rsync_time; + u8 _reserved4[16]; + u32 pcs_pwrup_reset_dly_time_auxclk; + u8 _reserved5[12]; + u32 pcs_lfps_ecstart_eqtlock; + u8 _reserved6[4]; + u32 pcs_rxeqtraining_wait_time; + u32 pcs_rxeqtraining_run_time; + u8 _reserved7[4]; + u32 pcs_fll_ctrl1; + u32 pcs_fll_ctrl2; + u32 pcs_fll_cnt_val_l; + u32 pcs_fll_cnt_val_h_tol; + u32 pcs_fll_man_code; + u32 pcs_autonomous_mode_ctrl; + u8 _reserved8[152]; + u32 pcs_ready_status; + u8 _reserved9[96]; + u32 pcs_rx_sigdet_lvl; + u8 _reserved10[48]; + u32 pcs_refgen_req_config1; + u32 pcs_refgen_req_config2; +}; +check_member(usb3_phy_pcs_reg_layout, pcs_sw_reset, 0x000); +check_member(usb3_phy_pcs_reg_layout, pcs_txmgn_v0, 0x00c); +check_member(usb3_phy_pcs_reg_layout, pcs_txmgn_v1, 0x010); +check_member(usb3_phy_pcs_reg_layout, pcs_txmgn_v2, 0x014); +check_member(usb3_phy_pcs_reg_layout, pcs_txmgn_v3, 0x018); +check_member(usb3_phy_pcs_reg_layout, pcs_txmgn_v4, 0x01c); +check_member(usb3_phy_pcs_reg_layout, pcs_txmgn_ls, 0x020); +check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m6db_v0, 0x024); +check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m3p5db_v0, 0x028); +check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m6db_v1, 0x02c); +check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m3p5db_v1, 0x030); +check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m6db_v2, 0x034); +check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m3p5db_v2, 0x038); +check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m6db_v3, 0x03c); +check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m3p5db_v3, 0x040); +check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m6db_v4, 0x044); +check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m3p5db_v4, 0x048); +check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m6db_ls, 0x04c); +check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m3p5db_ls, 0x050); +check_member(usb3_phy_pcs_reg_layout, pcs_rate_slew_cntrl, 0x05c); +check_member(usb3_phy_pcs_reg_layout, pcs_power_state_config2, 0x064); +check_member(usb3_phy_pcs_reg_layout, pcs_rcvr_dtct_dly_p1u2_l, 0x070); +check_member(usb3_phy_pcs_reg_layout, pcs_rcvr_dtct_dly_p1u2_h, 0x074); +check_member(usb3_phy_pcs_reg_layout, pcs_rcvr_dtct_dly_u3_l, 0x078); +check_member(usb3_phy_pcs_reg_layout, pcs_rcvr_dtct_dly_u3_h, 0x07c); +check_member(usb3_phy_pcs_reg_layout, pcs_lock_detect_config1, 0x080); +check_member(usb3_phy_pcs_reg_layout, pcs_lock_detect_config2, 0x084); +check_member(usb3_phy_pcs_reg_layout, pcs_lock_detect_config3, 0x088); +check_member(usb3_phy_pcs_reg_layout, pcs_pwrup_reset_dly_time_auxclk, 0x0a0); +check_member(usb3_phy_pcs_reg_layout, pcs_rxeqtraining_wait_time, 0x0b8); +check_member(usb3_phy_pcs_reg_layout, pcs_fll_cnt_val_h_tol, 0x0d0); +check_member(usb3_phy_pcs_reg_layout, pcs_autonomous_mode_ctrl, 0x0d8); +check_member(usb3_phy_pcs_reg_layout, pcs_ready_status, 0x174); +check_member(usb3_phy_pcs_reg_layout, pcs_refgen_req_config2, 0x210); + +static struct usb3_phy_qserdes_com_reg_layout *const qserdes_com_reg_layout = + (void *)QMP_PHY_QSERDES_COM_REG_BASE; +static struct usb3_phy_qserdes_tx_reg_layout *const qserdes_tx_reg_layout = + (void *)QMP_PHY_QSERDES_TX_REG_BASE; +static struct usb3_phy_qserdes_rx_reg_layout *const qserdes_rx_reg_layout = + (void *)QMP_PHY_QSERDES_RX_REG_BASE; +static struct usb3_phy_pcs_reg_layout *const pcs_reg_layout = + (void *)QMP_PHY_PCS_REG_BASE; + +static struct usb3_phy_qserdes_com_reg_layout *const + uniphy_qserdes_com_reg_layout = + (void *)QMP_UNIPHY_QSERDES_COM_REG_BASE; +static struct usb3_phy_qserdes_tx_reg_layout + *const uniphy_qserdes_tx_reg_layout = + (void *)QMP_UNIPHY_QSERDES_TX_REG_BASE; +static struct usb3_phy_qserdes_rx_reg_layout + *const uniphy_qserdes_rx_reg_layout = + (void *)QMP_UNIPHY_QSERDES_RX_REG_BASE; +static struct usb3_phy_pcs_reg_layout *const uniphy_pcs_reg_layout = + (void *)QMP_UNIPHY_PCS_REG_BASE; + +struct usb_dwc3 { + u32 sbuscfg0; + u32 sbuscfg1; + u32 txthrcfg; + u32 rxthrcfg; + u32 ctl; + u32 pmsts; + u32 sts; + u32 uctl1; + u32 snpsid; + u32 gpio; + u32 uid; + u32 uctl; + u64 buserraddr; + u64 prtbimap; + u8 reserved1[32]; + u32 dbgfifospace; + u32 dbgltssm; + u32 dbglnmcc; + u32 dbgbmu; + u32 dbglspmux; + u32 dbglsp; + u32 dbgepinfo0; + u32 dbgepinfo1; + u64 prtbimap_hs; + u64 prtbimap_fs; + u8 reserved2[112]; + u32 usb2phycfg; + u8 reserved3[60]; + u32 usb2i2cctl; + u8 reserved4[60]; + u32 usb2phyacc; + u8 reserved5[60]; + u32 usb3pipectl; + u8 reserved6[60]; +}; +check_member(usb_dwc3, usb3pipectl, 0x1c0); + +static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = { + {&qserdes_com_reg_layout->com_pll_ivco, 0x07}, + {&qserdes_com_reg_layout->com_sysclk_en_sel, 0x14}, + {&qserdes_com_reg_layout->com_bias_en_clkbuflr_en, 0x08}, + {&qserdes_com_reg_layout->com_clk_select, 0x30}, + {&qserdes_com_reg_layout->com_sys_clk_ctrl, 0x02}, + {&qserdes_com_reg_layout->com_resetsm_ctrl2, 0x08}, + {&qserdes_com_reg_layout->com_cmn_config, 0x16}, + {&qserdes_com_reg_layout->com_svs_mode_clk_sel, 0x01}, + {&qserdes_com_reg_layout->com_hsclk_sel, 0x80}, + {&qserdes_com_reg_layout->com_dec_start_mode0, 0x82}, + {&qserdes_com_reg_layout->com_div_frac_start1_mode0, 0xab}, + {&qserdes_com_reg_layout->com_div_frac_start2_mode0, 0xea}, + {&qserdes_com_reg_layout->com_div_frac_start3_mode0, 0x02}, + {&qserdes_com_reg_layout->com_cp_ctrl_mode0, 0x06}, + {&qserdes_com_reg_layout->com_pll_rctrl_mode0, 0x16}, + {&qserdes_com_reg_layout->com_pll_cctrl_mode0, 0x36}, + {&qserdes_com_reg_layout->com_integloop_gain1_mode0, 0x00}, + {&qserdes_com_reg_layout->com_integloop_gain0_mode0, 0x3f}, + {&qserdes_com_reg_layout->com_vco_tune2_mode0, 0x01}, + {&qserdes_com_reg_layout->com_vco_tune1_mode0, 0xc9}, + {&qserdes_com_reg_layout->com_coreclk_div_mode0, 0x0a}, + {&qserdes_com_reg_layout->com_lock_cmp3_mode0, 0x00}, + {&qserdes_com_reg_layout->com_lock_cmp2_mode0, 0x34}, + {&qserdes_com_reg_layout->com_lock_cmp1_mode0, 0x15}, + {&qserdes_com_reg_layout->com_lock_cmp_en, 0x04}, + {&qserdes_com_reg_layout->com_core_clk_en, 0x00}, + {&qserdes_com_reg_layout->com_lock_cmp_cfg, 0x00}, + {&qserdes_com_reg_layout->com_vco_tune_map, 0x00}, + {&qserdes_com_reg_layout->com_sysclk_buf_enable, 0x0a}, + {&qserdes_com_reg_layout->com_ssc_en_center, 0x01}, + {&qserdes_com_reg_layout->com_ssc_per1, 0x31}, + {&qserdes_com_reg_layout->com_ssc_per2, 0x01}, + {&qserdes_com_reg_layout->com_ssc_adj_per1, 0x00}, + {&qserdes_com_reg_layout->com_ssc_adj_per2, 0x00}, + {&qserdes_com_reg_layout->com_ssc_step_size1, 0x85}, + {&qserdes_com_reg_layout->com_ssc_step_size2, 0x07}, +}; + +static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = { + {&qserdes_tx_reg_layout->tx_highz_drvr_en, 0x10}, + {&qserdes_tx_reg_layout->tx_rcv_detect_lvl_2, 0x12}, + {&qserdes_tx_reg_layout->tx_lane_mode_1, 0x16}, + {&qserdes_tx_reg_layout->tx_res_code_lane_offset_rx, 0x09}, + {&qserdes_tx_reg_layout->tx_res_code_lane_offset_tx, 0x06}, +}; + +static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = { + {&qserdes_rx_reg_layout->rx_ucdr_fastlock_fo_gain, 0x0b}, + {&qserdes_rx_reg_layout->rx_rx_equ_adap_ctrl2, 0x0f}, + {&qserdes_rx_reg_layout->rx_rx_equ_adap_ctrl3, 0x4e}, + {&qserdes_rx_reg_layout->rx_rx_equ_adap_ctrl4, 0x18}, + {&qserdes_rx_reg_layout->rx_rx_eq_offset_adap_ctrl1, 0x77}, + {&qserdes_rx_reg_layout->rx_rx_offset_adap_ctrl2, 0x80}, + {&qserdes_rx_reg_layout->rx_sigdet_ctrl, 0x03}, + {&qserdes_rx_reg_layout->rx_sigdet_deglitch_ctrl, 0x16}, + {&qserdes_rx_reg_layout->rx_ucdr_so_saturtn_and_en, 0x75}, + {&qserdes_rx_reg_layout->rx_ucdr_pi_cntrls, 0x80}, + {&qserdes_rx_reg_layout->rx_ucdr_fo_gain, 0x0a}, + {&qserdes_rx_reg_layout->rx_ucdr_so_gain_half, 0x06}, + {&qserdes_rx_reg_layout->rx_sigdet_enables, 0x00}, +}; + +static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = { + /* FLL settings */ + {&pcs_reg_layout->pcs_fll_ctrl2, 0x83}, + {&pcs_reg_layout->pcs_fll_cnt_val_l, 0x09}, + {&pcs_reg_layout->pcs_fll_cnt_val_h_tol, 0xa2}, + {&pcs_reg_layout->pcs_fll_man_code, 0x40}, + {&pcs_reg_layout->pcs_fll_ctrl1, 0x02}, + + /* Lock Det settings */ + {&pcs_reg_layout->pcs_lock_detect_config1, 0xd1}, + {&pcs_reg_layout->pcs_lock_detect_config2, 0x1f}, + {&pcs_reg_layout->pcs_lock_detect_config3, 0x47}, + {&pcs_reg_layout->pcs_power_state_config2, 0x1b}, + + {&pcs_reg_layout->pcs_rx_sigdet_lvl, 0xba}, + {&pcs_reg_layout->pcs_txmgn_v0, 0x9f}, + {&pcs_reg_layout->pcs_txmgn_v1, 0x9f}, + {&pcs_reg_layout->pcs_txmgn_v2, 0xb7}, + {&pcs_reg_layout->pcs_txmgn_v3, 0x4e}, + {&pcs_reg_layout->pcs_txmgn_v4, 0x65}, + {&pcs_reg_layout->pcs_txmgn_ls, 0x6b}, + {&pcs_reg_layout->pcs_txdeemph_m6db_v0, 0x15}, + {&pcs_reg_layout->pcs_txdeemph_m3p5db_v0, 0x0d}, + {&pcs_reg_layout->pcs_txdeemph_m6db_v1, 0x15}, + {&pcs_reg_layout->pcs_txdeemph_m3p5db_v1, 0x0d}, + {&pcs_reg_layout->pcs_txdeemph_m6db_v2, 0x15}, + {&pcs_reg_layout->pcs_txdeemph_m3p5db_v2, 0x0d}, + {&pcs_reg_layout->pcs_txdeemph_m6db_v3, 0x15}, + {&pcs_reg_layout->pcs_txdeemph_m3p5db_v3, 0x1d}, + {&pcs_reg_layout->pcs_txdeemph_m6db_v4, 0x15}, + {&pcs_reg_layout->pcs_txdeemph_m3p5db_v4, 0x0d}, + {&pcs_reg_layout->pcs_txdeemph_m6db_ls, 0x15}, + {&pcs_reg_layout->pcs_txdeemph_m3p5db_ls, 0x0d}, + {&pcs_reg_layout->pcs_rate_slew_cntrl, 0x02}, + {&pcs_reg_layout->pcs_pwrup_reset_dly_time_auxclk, 0x04}, + {&pcs_reg_layout->pcs_tsync_rsync_time, 0x44}, + {&pcs_reg_layout->pcs_rcvr_dtct_dly_p1u2_l, 0xe7}, + {&pcs_reg_layout->pcs_rcvr_dtct_dly_p1u2_h, 0x03}, + {&pcs_reg_layout->pcs_rcvr_dtct_dly_u3_l, 0x40}, + {&pcs_reg_layout->pcs_rcvr_dtct_dly_u3_h, 0x00}, + {&pcs_reg_layout->pcs_rxeqtraining_wait_time, 0x75}, + {&pcs_reg_layout->pcs_lfps_ecstart_eqtlock, 0x86}, + {&pcs_reg_layout->pcs_rxeqtraining_run_time, 0x13}, +}; + +static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_serdes_tbl[] = { + {&uniphy_qserdes_com_reg_layout->com_pll_ivco, 0x07}, + {&uniphy_qserdes_com_reg_layout->com_sysclk_en_sel, 0x14}, + {&uniphy_qserdes_com_reg_layout->com_bias_en_clkbuflr_en, 0x04}, + {&uniphy_qserdes_com_reg_layout->com_clk_select, 0x30}, + {&uniphy_qserdes_com_reg_layout->com_sys_clk_ctrl, 0x02}, + {&uniphy_qserdes_com_reg_layout->com_resetsm_ctrl2, 0x08}, + {&uniphy_qserdes_com_reg_layout->com_cmn_config, 0x06}, + {&uniphy_qserdes_com_reg_layout->com_svs_mode_clk_sel, 0x01}, + {&uniphy_qserdes_com_reg_layout->com_hsclk_sel, 0x80}, + {&uniphy_qserdes_com_reg_layout->com_dec_start_mode0, 0x82}, + {&uniphy_qserdes_com_reg_layout->com_div_frac_start1_mode0, 0xab}, + {&uniphy_qserdes_com_reg_layout->com_div_frac_start2_mode0, 0xea}, + {&uniphy_qserdes_com_reg_layout->com_div_frac_start3_mode0, 0x02}, + {&uniphy_qserdes_com_reg_layout->com_cp_ctrl_mode0, 0x06}, + {&uniphy_qserdes_com_reg_layout->com_pll_rctrl_mode0, 0x16}, + {&uniphy_qserdes_com_reg_layout->com_pll_cctrl_mode0, 0x36}, + {&uniphy_qserdes_com_reg_layout->com_integloop_gain1_mode0, 0x00}, + {&uniphy_qserdes_com_reg_layout->com_integloop_gain0_mode0, 0x3f}, + {&uniphy_qserdes_com_reg_layout->com_vco_tune2_mode0, 0x01}, + {&uniphy_qserdes_com_reg_layout->com_vco_tune1_mode0, 0xc9}, + {&uniphy_qserdes_com_reg_layout->com_coreclk_div_mode0, 0x0a}, + {&uniphy_qserdes_com_reg_layout->com_lock_cmp3_mode0, 0x00}, + {&uniphy_qserdes_com_reg_layout->com_lock_cmp2_mode0, 0x34}, + {&uniphy_qserdes_com_reg_layout->com_lock_cmp1_mode0, 0x15}, + {&uniphy_qserdes_com_reg_layout->com_lock_cmp_en, 0x04}, + {&uniphy_qserdes_com_reg_layout->com_core_clk_en, 0x00}, + {&uniphy_qserdes_com_reg_layout->com_lock_cmp_cfg, 0x00}, + {&uniphy_qserdes_com_reg_layout->com_vco_tune_map, 0x00}, + {&uniphy_qserdes_com_reg_layout->com_sysclk_buf_enable, 0x0a}, + {&uniphy_qserdes_com_reg_layout->com_ssc_en_center, 0x01}, + {&uniphy_qserdes_com_reg_layout->com_ssc_per1, 0x31}, + {&uniphy_qserdes_com_reg_layout->com_ssc_per2, 0x01}, + {&uniphy_qserdes_com_reg_layout->com_ssc_adj_per1, 0x00}, + {&uniphy_qserdes_com_reg_layout->com_ssc_adj_per2, 0x00}, + {&uniphy_qserdes_com_reg_layout->com_ssc_step_size1, 0x85}, + {&uniphy_qserdes_com_reg_layout->com_ssc_step_size2, 0x07}, +}; + +static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_tx_tbl[] = { + {&uniphy_qserdes_tx_reg_layout->tx_highz_drvr_en, 0x10}, + {&uniphy_qserdes_tx_reg_layout->tx_rcv_detect_lvl_2, 0x12}, + {&uniphy_qserdes_tx_reg_layout->tx_lane_mode_1, 0xc6}, + {&uniphy_qserdes_tx_reg_layout->tx_res_code_lane_offset_rx, 0x06}, + {&uniphy_qserdes_tx_reg_layout->tx_res_code_lane_offset_tx, 0x06}, +}; + +static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_rx_tbl[] = { + {&uniphy_qserdes_rx_reg_layout->rx_vga_cal_ctrl2, 0x0c}, + {&uniphy_qserdes_rx_reg_layout->rx_rx_mode_00, 0x50}, + {&uniphy_qserdes_rx_reg_layout->rx_ucdr_fastlock_fo_gain, 0x0b}, + {&uniphy_qserdes_rx_reg_layout->rx_rx_equ_adap_ctrl2, 0x0e}, + {&uniphy_qserdes_rx_reg_layout->rx_rx_equ_adap_ctrl3, 0x4e}, + {&uniphy_qserdes_rx_reg_layout->rx_rx_equ_adap_ctrl4, 0x18}, + {&uniphy_qserdes_rx_reg_layout->rx_rx_eq_offset_adap_ctrl1, 0x77}, + {&uniphy_qserdes_rx_reg_layout->rx_rx_offset_adap_ctrl2, 0x80}, + {&uniphy_qserdes_rx_reg_layout->rx_sigdet_ctrl, 0x03}, + {&uniphy_qserdes_rx_reg_layout->rx_sigdet_deglitch_ctrl, 0x1c}, + {&uniphy_qserdes_rx_reg_layout->rx_ucdr_so_saturtn_and_en, 0x75}, + {&uniphy_qserdes_rx_reg_layout->rx_ucdr_pi_cntrls, 0x80}, + {&uniphy_qserdes_rx_reg_layout->rx_ucdr_fo_gain, 0x0a}, + {&uniphy_qserdes_rx_reg_layout->rx_ucdr_so_gain_half, 0x06}, + {&uniphy_qserdes_rx_reg_layout->rx_sigdet_enables, 0x00}, +}; + +static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_pcs_tbl[] = { + /* FLL settings */ + {&uniphy_pcs_reg_layout->pcs_fll_ctrl2, 0x83}, + {&uniphy_pcs_reg_layout->pcs_fll_cnt_val_l, 0x09}, + {&uniphy_pcs_reg_layout->pcs_fll_cnt_val_h_tol, 0xa2}, + {&uniphy_pcs_reg_layout->pcs_fll_man_code, 0x40}, + {&uniphy_pcs_reg_layout->pcs_fll_ctrl1, 0x02}, + + /* Lock Det settings */ + {&uniphy_pcs_reg_layout->pcs_lock_detect_config1, 0xd1}, + {&uniphy_pcs_reg_layout->pcs_lock_detect_config2, 0x1f}, + {&uniphy_pcs_reg_layout->pcs_lock_detect_config3, 0x47}, + {&uniphy_pcs_reg_layout->pcs_power_state_config2, 0x1b}, + + {&uniphy_pcs_reg_layout->pcs_rx_sigdet_lvl, 0xba}, + {&uniphy_pcs_reg_layout->pcs_txmgn_v0, 0x9f}, + {&uniphy_pcs_reg_layout->pcs_txmgn_v1, 0x9f}, + {&uniphy_pcs_reg_layout->pcs_txmgn_v2, 0xb5}, + {&uniphy_pcs_reg_layout->pcs_txmgn_v3, 0x4c}, + {&uniphy_pcs_reg_layout->pcs_txmgn_v4, 0x64}, + {&uniphy_pcs_reg_layout->pcs_txmgn_ls, 0x6a}, + {&uniphy_pcs_reg_layout->pcs_txdeemph_m6db_v0, 0x15}, + {&uniphy_pcs_reg_layout->pcs_txdeemph_m3p5db_v0, 0x0d}, + {&uniphy_pcs_reg_layout->pcs_txdeemph_m6db_v1, 0x15}, + {&uniphy_pcs_reg_layout->pcs_txdeemph_m3p5db_v1, 0x0d}, + {&uniphy_pcs_reg_layout->pcs_txdeemph_m6db_v2, 0x15}, + {&uniphy_pcs_reg_layout->pcs_txdeemph_m3p5db_v2, 0x0d}, + {&uniphy_pcs_reg_layout->pcs_txdeemph_m6db_v3, 0x15}, + {&uniphy_pcs_reg_layout->pcs_txdeemph_m3p5db_v3, 0x1d}, + {&uniphy_pcs_reg_layout->pcs_txdeemph_m6db_v4, 0x15}, + {&uniphy_pcs_reg_layout->pcs_txdeemph_m3p5db_v4, 0x0d}, + {&uniphy_pcs_reg_layout->pcs_txdeemph_m6db_ls, 0x15}, + {&uniphy_pcs_reg_layout->pcs_txdeemph_m3p5db_ls, 0x0d}, + {&uniphy_pcs_reg_layout->pcs_rate_slew_cntrl, 0x02}, + {&uniphy_pcs_reg_layout->pcs_pwrup_reset_dly_time_auxclk, 0x04}, + {&uniphy_pcs_reg_layout->pcs_tsync_rsync_time, 0x44}, + {&uniphy_pcs_reg_layout->pcs_rcvr_dtct_dly_p1u2_l, 0xe7}, + {&uniphy_pcs_reg_layout->pcs_rcvr_dtct_dly_p1u2_h, 0x03}, + {&uniphy_pcs_reg_layout->pcs_rcvr_dtct_dly_u3_l, 0x40}, + {&uniphy_pcs_reg_layout->pcs_rcvr_dtct_dly_u3_h, 0x00}, + {&uniphy_pcs_reg_layout->pcs_rxeqtraining_wait_time, 0x75}, + {&uniphy_pcs_reg_layout->pcs_lfps_ecstart_eqtlock, 0x86}, + {&uniphy_pcs_reg_layout->pcs_rxeqtraining_run_time, 0x13}, + {&uniphy_pcs_reg_layout->pcs_refgen_req_config1, 0x21}, + {&uniphy_pcs_reg_layout->pcs_refgen_req_config2, 0x60}, +}; + +struct usb_dwc3_cfg { + struct usb_dwc3 *usb_host_dwc3; + struct usb_qusb_phy_pll *qusb_phy_pll; + struct usb_qusb_phy_dig *qusb_phy_dig; + /* Init sequence for QMP PHY blocks - serdes, tx, rx, pcs */ + const struct qmp_phy_init_tbl *serdes_tbl; + int serdes_tbl_num; + const struct qmp_phy_init_tbl *tx_tbl; + int tx_tbl_num; + const struct qmp_phy_init_tbl *rx_tbl; + int rx_tbl_num; + const struct qmp_phy_init_tbl *pcs_tbl; + int pcs_tbl_num; + struct usb3_phy_pcs_reg_layout *qmp_pcs_reg; + + u32 *usb3_bcr; + u32 *qusb2phy_bcr; + u32 *gcc_usb3phy_bcr_reg; + u32 *gcc_qmpphy_bcr_reg; + struct usb_board_data *board_data; + u32 efuse_offset; +}; + +static struct usb_dwc3_cfg usb_port0 = { + .usb_host_dwc3 = (void *)USB_HOST0_DWC3_BASE, + .qusb_phy_pll = (void *)QUSB_PRIM_PHY_BASE, + .qusb_phy_dig = (void *)QUSB_PRIM_PHY_DIG_BASE, + .serdes_tbl = qmp_v3_usb3_serdes_tbl, + .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl), + .tx_tbl = qmp_v3_usb3_tx_tbl, + .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl), + .rx_tbl = qmp_v3_usb3_rx_tbl, + .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl), + .pcs_tbl = qmp_v3_usb3_pcs_tbl, + .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl), + .qmp_pcs_reg = (void *)QMP_PHY_PCS_REG_BASE, + .usb3_bcr = &gcc->usb30_prim_bcr, + .qusb2phy_bcr = &gcc->qusb2phy_prim_bcr, + .gcc_usb3phy_bcr_reg = &gcc->usb3_dp_phy_prim_bcr, + .gcc_qmpphy_bcr_reg = &gcc->usb3_phy_prim_bcr, + .efuse_offset = 25, +}; +static struct usb_dwc3_cfg usb_port1 = { + .usb_host_dwc3 = (void *)USB_HOST1_DWC3_BASE, + .qusb_phy_pll = (void *)QUSB_SEC_PHY_BASE, + .qusb_phy_dig = (void *)QUSB_SEC_PHY_DIG_BASE, + .serdes_tbl = qmp_v3_usb3_uniphy_serdes_tbl, + .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_serdes_tbl), + .tx_tbl = qmp_v3_usb3_uniphy_tx_tbl, + .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_tx_tbl), + .rx_tbl = qmp_v3_usb3_uniphy_rx_tbl, + .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_rx_tbl), + .pcs_tbl = qmp_v3_usb3_uniphy_pcs_tbl, + .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_pcs_tbl), + .qmp_pcs_reg = (void *)QMP_UNIPHY_PCS_REG_BASE, + .usb3_bcr = &gcc->usb30_sec_bcr, + .qusb2phy_bcr = &gcc->qusb2phy_sec_bcr, + .gcc_usb3phy_bcr_reg = &gcc->usb3phy_phy_sec_bcr, + .gcc_qmpphy_bcr_reg = &gcc->usb3_phy_sec_bcr, + .efuse_offset = 30, +}; + +static struct qfprom_corr * const qfprom_corr_efuse = (void *)QFPROM_BASE; + +static void reset_usb(struct usb_dwc3_cfg *dwc3) +{ + /* Assert Core reset */ + clock_reset_bcr(dwc3->usb3_bcr, 1); + + /* Assert QUSB PHY reset */ + clock_reset_bcr(dwc3->qusb2phy_bcr, 1); + + /* Assert QMP PHY reset */ + clock_reset_bcr(dwc3->gcc_usb3phy_bcr_reg, 1); + clock_reset_bcr(dwc3->gcc_qmpphy_bcr_reg, 1); +} + +void reset_usb0(void) +{ + /* Before Resetting PHY, put Core in Reset */ + printk(BIOS_INFO, "Starting DWC3 and PHY resets for USB(0)\n"); + + reset_usb(&usb_port0); +} + +void reset_usb1(void) +{ + /* Before Resetting PHY, put Core in Reset */ + printk(BIOS_INFO, "Starting DWC3 and PHY resets for USB(1)\n"); + + reset_usb(&usb_port1); +} +/* + * Update board specific PHY tuning override values that specified from + * board file. + */ +static void qusb2_phy_override_phy_params(struct usb_dwc3_cfg *dwc3) +{ + /* Override preemphasis value */ + write32(&dwc3->qusb_phy_dig->tune1, + dwc3->board_data->port_tune1); + + /* Override BIAS_CTRL_2 to reduce the TX swing overshooting. */ + write32(&dwc3->qusb_phy_pll->bias_ctrl_2, + dwc3->board_data->pll_bias_control_2); + + /* Override IMP_RES_OFFSET value */ + write32(&dwc3->qusb_phy_dig->imp_ctrl1, + dwc3->board_data->imp_ctrl1); +} + +/* + * Fetches HS Tx tuning value from efuse register and sets the + * QUSB2PHY_PORT_TUNE1/2 register. + * For error case, skip setting the value and use the default value. + */ +static void qusb2_phy_set_tune_param(struct usb_dwc3_cfg *dwc3) +{ + /* + * Efuse registers 4 bit value specifies tuning for HSTX + * output current in TUNE1 Register. Hence Extract 4 bits from + * EFUSE at correct position. + */ + + const int efuse_bits = 4; + int bit_pos = dwc3->efuse_offset; + + u32 bit_mask = (1 << efuse_bits) - 1; + u32 tune_val = + (read32(&qfprom_corr_efuse->qusb_hstx_trim_lsb) >> bit_pos) + & bit_mask; + + if (bit_pos + efuse_bits > 32) { + /* + * Value split between two EFUSE registers, + * get the second part. + */ + int done_bits = 32 - bit_pos; + + bit_mask = (1 << (efuse_bits - done_bits)) - 1; + tune_val |= + (read32(&qfprom_corr_efuse->qusb_hstx_trim_msb) & + bit_mask) << done_bits; + } + + /* + * if efuse reg is updated (i.e non-zero) then use it to program + * tune parameters. + */ + if (tune_val) + clrsetbits_le32(&dwc3->qusb_phy_dig->tune1, + PORT_TUNE1_MASK, tune_val << 4); +} + +static void tune_phy(struct usb_dwc3_cfg *dwc3, struct usb_qusb_phy_dig *phy) +{ + write32(&phy->pwr_ctrl2, QUSB2PHY_PWR_CTRL2); + /* IMP_CTRL1: Control the impedance reduction */ + write32(&phy->imp_ctrl1, QUSB2PHY_IMP_CTRL1); + /* IMP_CTRL2: Impedance offset/mapping slope */ + write32(&phy->imp_ctrl2, QUSB2PHY_IMP_CTRL1); + write32(&phy->chg_ctrl2, QUSB2PHY_IMP_CTRL2); + /* + * TUNE1: Sets HS Impedance to approx 45 ohms + * then override with efuse value. + */ + write32(&phy->tune1, QUSB2PHY_PORT_TUNE1); + /* TUNE2: Tuning for HS Disconnect Level */ + write32(&phy->tune2, QUSB2PHY_PORT_TUNE2); + /* TUNE3: Tune squelch range */ + write32(&phy->tune3, QUSB2PHY_PORT_TUNE3); + /* TUNE4: Sets EOP_DLY(Squelch rising edge to linestate falling edge) */ + write32(&phy->tune4, QUSB2PHY_PORT_TUNE4); + write32(&phy->tune5, QUSB2PHY_PORT_TUNE5); + + if (dwc3->board_data) { + /* Override board specific PHY tuning values */ + qusb2_phy_override_phy_params(dwc3); + + /* Set efuse value for tuning the PHY */ + qusb2_phy_set_tune_param(dwc3); + } +} + +static void hs_qusb_phy_init(struct usb_dwc3_cfg *dwc3) +{ + /* PWR_CTRL: set the power down bit to disable the PHY */ + setbits_le32(&dwc3->qusb_phy_dig->pwr_ctrl1, POWER_DOWN); + + write32(&dwc3->qusb_phy_pll->analog_controls_two, + QUSB2PHY_PLL_ANALOG_CONTROLS_TWO); + write32(&dwc3->qusb_phy_pll->clock_inverters, + QUSB2PHY_PLL_CLOCK_INVERTERS); + write32(&dwc3->qusb_phy_pll->cmode, + QUSB2PHY_PLL_CMODE); + write32(&dwc3->qusb_phy_pll->lock_delay, + QUSB2PHY_PLL_LOCK_DELAY); + write32(&dwc3->qusb_phy_pll->dig_tim, + QUSB2PHY_PLL_DIGITAL_TIMERS_TWO); + write32(&dwc3->qusb_phy_pll->bias_ctrl_1, + QUSB2PHY_PLL_BIAS_CONTROL_1); + write32(&dwc3->qusb_phy_pll->bias_ctrl_2, + QUSB2PHY_PLL_BIAS_CONTROL_2); + + tune_phy(dwc3, dwc3->qusb_phy_dig); + + /* PWR_CTRL1: Clear the power down bit to enable the PHY */ + clrbits_le32(&dwc3->qusb_phy_dig->pwr_ctrl1, POWER_DOWN); + + write32(&dwc3->qusb_phy_dig->debug_ctrl2, + DEBUG_CTRL2_MUX_PLL_LOCK_STATUS); + + /* + * DEBUG_STAT5: wait for 160uS for PLL lock; + * vstatus[0] changes from 0 to 1. + */ + long lock_us = wait_us(160, read32(&dwc3->qusb_phy_dig->debug_stat5) & + VSTATUS_PLL_LOCK_STATUS_MASK); + if (!lock_us) + printk(BIOS_ERR, "ERROR: QUSB PHY PLL LOCK fails\n"); + else + printk(BIOS_DEBUG, "QUSB PHY initialized and locked in %ldus\n", + lock_us); +} + +static void qcom_qmp_phy_configure(const struct qmp_phy_init_tbl tbl[], + int num) +{ + int i; + const struct qmp_phy_init_tbl *t = tbl; + + if (!t) + return; + + for (i = 0; i < num; i++, t++) + write32(t->address, t->val); +} + +static void ss_qmp_phy_init(struct usb_dwc3_cfg *dwc3) +{ + /* power up USB3 PHY */ + write32(&dwc3->qmp_pcs_reg->pcs_power_down_control, 0x01); + + /* Serdes configuration */ + qcom_qmp_phy_configure(dwc3->serdes_tbl, dwc3->serdes_tbl_num); + /* Tx, Rx, and PCS configurations */ + qcom_qmp_phy_configure(dwc3->tx_tbl, dwc3->tx_tbl_num); + qcom_qmp_phy_configure(dwc3->rx_tbl, dwc3->rx_tbl_num); + qcom_qmp_phy_configure(dwc3->pcs_tbl, dwc3->pcs_tbl_num); + + /* perform software reset of PCS/Serdes */ + write32(&dwc3->qmp_pcs_reg->pcs_sw_reset, 0x00); + /* start PCS/Serdes to operation mode */ + write32(&dwc3->qmp_pcs_reg->pcs_start_control, 0x03); + + /* + * Wait for PHY initialization to be done + * PCS_STATUS: wait for 1ms for PHY STATUS; + * SW can continuously check for PHYSTATUS = 1.b0. + */ + long lock_us = wait_us(1000, + !(read32(&dwc3->qmp_pcs_reg->pcs_ready_status) & + USB3_PCS_PHYSTATUS)); + if (!lock_us) + printk(BIOS_ERR, "ERROR: QMP PHY PLL LOCK fails:\n"); + else + printk(BIOS_DEBUG, "QMP PHY initialized and locked in %ldus\n", + lock_us); +} + +static void setup_dwc3(struct usb_dwc3 *dwc3) +{ + /* core exits U1/U2/U3 only in PHY power state P1/P2/P3 respectively */ + clrsetbits_le32(&dwc3->usb3pipectl, + DWC3_GUSB3PIPECTL_DELAYP1TRANS, + DWC3_GUSB3PIPECTL_UX_EXIT_IN_PX); + + /* + * Configure USB phy interface of DWC3 core. + * 1. Select UTMI+ PHY with 16-bit interface. + * 2. Set USBTRDTIM to the corresponding value + * according to the UTMI+ PHY interface. + */ + clrsetbits_le32(&dwc3->usb2phycfg, + (DWC3_GUSB2PHYCFG_USB2TRDTIM_MASK | + DWC3_GUSB2PHYCFG_PHYIF_MASK), + (DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) | + DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT))); + + clrsetbits_le32(&dwc3->ctl, (DWC3_GCTL_SCALEDOWN_MASK | + DWC3_GCTL_DISSCRAMBLE), + DWC3_GCTL_U2EXIT_LFPS | DWC3_GCTL_DSBLCLKGTNG); + + /* configure controller in Host mode */ + clrsetbits_le32(&dwc3->ctl, (DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)), + DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_HOST)); + printk(BIOS_SPEW, "Configure USB in Host mode\n"); +} + +/* Initialization of DWC3 Core and PHY */ +static void setup_usb_host(struct usb_dwc3_cfg *dwc3, + struct usb_board_data *board_data) +{ + dwc3->board_data = board_data; + + /* Clear core reset. */ + clock_reset_bcr(dwc3->usb3_bcr, 0); + + /* Clear QUSB PHY reset. */ + clock_reset_bcr(dwc3->qusb2phy_bcr, 0); + + /* Initialize QUSB PHY */ + hs_qusb_phy_init(dwc3); + + /* Clear QMP PHY resets. */ + clock_reset_bcr(dwc3->gcc_usb3phy_bcr_reg, 0); + clock_reset_bcr(dwc3->gcc_qmpphy_bcr_reg, 0); + + /* Initialize QMP PHY */ + ss_qmp_phy_init(dwc3); + + setup_dwc3(dwc3->usb_host_dwc3); + + printk(BIOS_INFO, "DWC3 and PHY setup finished\n"); +} + +void setup_usb_host0(struct usb_board_data *board_data) +{ + printk(BIOS_INFO, "Setting up USB HOST0 controller.\n"); + setup_usb_host(&usb_port0, board_data); +} + +void setup_usb_host1(struct usb_board_data *board_data) +{ + printk(BIOS_INFO, "Setting up USB HOST1 controller.\n"); + setup_usb_host(&usb_port1, board_data); +} diff --git a/src/soc/rockchip/common/spi.c b/src/soc/rockchip/common/spi.c index 98016c0fc9..e929419a14 100644 --- a/src/soc/rockchip/common/spi.c +++ b/src/soc/rockchip/common/spi.c @@ -96,7 +96,7 @@ static void rockchip_spi_set_clk(struct rockchip_spi *regs, unsigned int hz) void rockchip_spi_init(unsigned int bus, unsigned int speed_hz) { - assert(bus >= 0 && bus < ARRAY_SIZE(rockchip_spi_slaves)); + assert(bus < ARRAY_SIZE(rockchip_spi_slaves)); struct rockchip_spi *regs = rockchip_spi_slaves[bus].regs; unsigned int ctrlr0 = 0; @@ -134,13 +134,13 @@ void rockchip_spi_init(unsigned int bus, unsigned int speed_hz) void rockchip_spi_set_sample_delay(unsigned int bus, unsigned int delay_ns) { - assert(bus >= 0 && bus < ARRAY_SIZE(rockchip_spi_slaves)); + assert(bus < ARRAY_SIZE(rockchip_spi_slaves)); struct rockchip_spi *regs = rockchip_spi_slaves[bus].regs; unsigned int rsd; /* Rxd Sample Delay */ rsd = DIV_ROUND_CLOSEST(delay_ns * (SPI_SRCCLK_HZ >> 8), 1*GHz >> 8); - assert(rsd >= 0 && rsd <= 3); + assert(rsd <= 3); clrsetbits_le32(®s->ctrlr0, SPI_RXDSD_MASK << SPI_RXDSD_OFFSET, rsd << SPI_RXDSD_OFFSET); } diff --git a/src/soc/samsung/exynos5420/spi.c b/src/soc/samsung/exynos5420/spi.c index 753a24be19..1903f6b3b9 100644 --- a/src/soc/samsung/exynos5420/spi.c +++ b/src/soc/samsung/exynos5420/spi.c @@ -206,7 +206,7 @@ static void spi_ctrlr_release_bus(const struct spi_slave *slave) static int spi_ctrlr_setup(const struct spi_slave *slave) { - ASSERT(slave->bus >= 0 && slave->bus < 3); + ASSERT(slave->bus < 3); struct exynos_spi_slave *eslave; eslave = to_exynos_spi(slave); diff --git a/src/southbridge/amd/rs780/ht.c b/src/southbridge/amd/rs780/ht.c index 94df2337c1..8943fc1300 100644 --- a/src/southbridge/amd/rs780/ht.c +++ b/src/southbridge/amd/rs780/ht.c @@ -24,24 +24,24 @@ void avoid_lpc_dma_deadlock(struct device *nb_dev, struct device *sb_dev) { struct device *cpu_f0; - u8 reg; + u32 reg32; cpu_f0 = pcidev_on_root(0x18, 0); set_nbcfg_enable_bits(cpu_f0, 0x68, 3 << 21, 1 << 21); - reg = nbpcie_p_read_index(sb_dev, 0x10); - reg |= 0x100; /* bit9=1 */ - nbpcie_p_write_index(sb_dev, 0x10, reg); + reg32 = nbpcie_p_read_index(sb_dev, 0x10); + reg32 |= 0x100; /* bit9=1 */ + nbpcie_p_write_index(sb_dev, 0x10, reg32); - reg = nbpcie_p_read_index(nb_dev, 0x10); - reg |= 0x100; /* bit9=1 */ - nbpcie_p_write_index(nb_dev, 0x10, reg); + reg32 = nbpcie_p_read_index(nb_dev, 0x10); + reg32 |= 0x100; /* bit9=1 */ + nbpcie_p_write_index(nb_dev, 0x10, reg32); /* Enable NP protocol over PCIE for memory-mapped writes targeting LPC * Set this bit to avoid a deadlock condition. */ - reg = htiu_read_index(nb_dev, 0x6); - reg |= 0x1000000; /* bit26 */ - htiu_write_index(nb_dev, 0x6, reg); + reg32 = htiu_read_index(nb_dev, 0x6); + reg32 |= 0x1000000; /* bit26 */ + htiu_write_index(nb_dev, 0x6, reg32); } static void pcie_init(struct device *dev) diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig index dae3c32c86..fc3e9fcadb 100644 --- a/src/southbridge/intel/bd82x6x/Kconfig +++ b/src/southbridge/intel/bd82x6x/Kconfig @@ -44,6 +44,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy select HAVE_INTEL_CHIPSET_LOCKDOWN select SOUTHBRIDGE_INTEL_COMMON_SMM select SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT + select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG config EHCI_BAR hex diff --git a/src/southbridge/intel/bd82x6x/Makefile.inc b/src/southbridge/intel/bd82x6x/Makefile.inc index a950e5ce5d..023f5d32c2 100644 --- a/src/southbridge/intel/bd82x6x/Makefile.inc +++ b/src/southbridge/intel/bd82x6x/Makefile.inc @@ -31,7 +31,6 @@ ramstage-y += ../common/pciehp.c ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c ramstage-y += me_status.c -ramstage-y += watchdog.c ramstage-$(CONFIG_ELOG) += elog.c diff --git a/src/southbridge/intel/bd82x6x/early_usb.c b/src/southbridge/intel/bd82x6x/early_usb.c index 17919af53a..955737e2a8 100644 --- a/src/southbridge/intel/bd82x6x/early_usb.c +++ b/src/southbridge/intel/bd82x6x/early_usb.c @@ -19,6 +19,9 @@ #include #include #include +#include +#include + #include "pch.h" void early_usb_init(const struct southbridge_usb_port *portmap) @@ -32,46 +35,39 @@ void early_usb_init(const struct southbridge_usb_port *portmap) 0x2000094a, 0x2000035f, 0x20000f53, 0x20000357, 0x20000353 }; int i; - /* Activate PMBAR. */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1); - pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE + 4, 0); - /* Enable ACPI BAR */ - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */, 0x80); /* Unlock registers. */ - outw(inw(DEFAULT_PMBASE | UPRWC) | UPRWC_WR_EN, - DEFAULT_PMBASE | UPRWC); + write_pmbase16(UPRWC, read_pmbase16(UPRWC) | UPRWC_WR_EN); for (i = 0; i < 14; i++) - write32(DEFAULT_RCBABASE + (0x3500 + 4 * i), - currents[portmap[i].current]); + RCBA32(0x3500 + 4 * i) = currents[portmap[i].current]; for (i = 0; i < 10; i++) - write32(DEFAULT_RCBABASE + (0x3538 + 4 * i), 0); + RCBA32(0x3538 + 4 * i) = 0; for (i = 0; i < 8; i++) - write32(DEFAULT_RCBABASE + (0x3560 + 4 * i), rcba_dump[i]); + RCBA32(0x3560 + 4 * i) = rcba_dump[i]; for (i = 0; i < 8; i++) - write32(DEFAULT_RCBABASE + (0x3580 + 4 * i), 0); + RCBA32(0x3580 + 4 * i) = 0; reg32 = 0; for (i = 0; i < 14; i++) if (!portmap[i].enabled) reg32 |= (1 << i); - write32(DEFAULT_RCBABASE + USBPDO, reg32); + RCBA32(USBPDO) = reg32; reg32 = 0; for (i = 0; i < 8; i++) if (portmap[i].enabled && portmap[i].oc_pin >= 0) reg32 |= (1 << (i + 8 * portmap[i].oc_pin)); - write32(DEFAULT_RCBABASE + USBOCM1, reg32); + RCBA32(USBOCM1) = reg32; reg32 = 0; for (i = 8; i < 14; i++) if (portmap[i].enabled && portmap[i].oc_pin >= 4) reg32 |= (1 << (i - 8 + 8 * (portmap[i].oc_pin - 4))); - write32(DEFAULT_RCBABASE + USBOCM2, reg32); + RCBA32(USBOCM2) = reg32; for (i = 0; i < 22; i++) - write32(DEFAULT_RCBABASE + (0x35a8 + 4 * i), 0); + RCBA32(0x35a8 + 4 * i) = 0; - pci_write_config32(PCI_DEV(0, 0x14, 0), 0xe4, 0x00000000); + pci_write_config32(PCH_XHCI_DEV, 0xe4, 0x00000000); /* Relock registers. */ - outw(0, DEFAULT_PMBASE | UPRWC); + write_pmbase16(UPRWC, 0); } diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index e9e49649f2..f7bb7e4303 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -908,6 +908,12 @@ static void lpc_final(struct device *dev) if (CONFIG(INTEL_CHIPSET_LOCKDOWN) || acpi_is_wakeup_s3()) { outb(APM_CNT_FINALIZE, APM_CNT); + if (CONFIG(CONSOLE_SPI_FLASH)) + /* Re-init SPI driver to handle locked BAR. + This prevents flashconsole from hanging. + If other code needs to use SPI during + ramstage, whitelist it here. */ + spi_init(); } } } diff --git a/src/southbridge/intel/bd82x6x/pch.c b/src/southbridge/intel/bd82x6x/pch.c index 746c11a2e3..f8540af451 100644 --- a/src/southbridge/intel/bd82x6x/pch.c +++ b/src/southbridge/intel/bd82x6x/pch.c @@ -144,7 +144,7 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue) } #ifndef __SMM__ -/* Set bit in Function Disble register to hide this device */ +/* Set bit in function disable register to hide this device */ static void pch_hide_devfn(unsigned devfn) { switch (devfn) { diff --git a/src/southbridge/intel/bd82x6x/pci.c b/src/southbridge/intel/bd82x6x/pci.c index c3b82577e1..2186287df2 100644 --- a/src/southbridge/intel/bd82x6x/pci.c +++ b/src/southbridge/intel/bd82x6x/pci.c @@ -47,9 +47,6 @@ static void pci_init(struct device *dev) reg8 |= (0x04 << 3); pci_write_config8(dev, SMLT, reg8); - /* Will this improve throughput of bus masters? */ - pci_write_config8(dev, PCI_MIN_GNT, 0x06); - /* Clear errors in status registers */ reg16 = pci_read_config16(dev, PSTS); //reg16 |= 0xf900; diff --git a/src/southbridge/intel/common/Kconfig b/src/southbridge/intel/common/Kconfig index 0c7eb18338..dfd89755ec 100644 --- a/src/southbridge/intel/common/Kconfig +++ b/src/southbridge/intel/common/Kconfig @@ -66,6 +66,10 @@ config INTEL_CHIPSET_LOCKDOWN and S3 resume (always done by coreboot). Select this to let coreboot to do this on normal boot path. +config SOUTHBRIDGE_INTEL_COMMON_WATCHDOG + bool + depends on SOUTHBRIDGE_INTEL_COMMON + if SOUTHBRIDGE_INTEL_COMMON_FINALIZE choice diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc index 1085f6c66a..4cf6e6f57e 100644 --- a/src/southbridge/intel/common/Makefile.inc +++ b/src/southbridge/intel/common/Makefile.inc @@ -27,6 +27,8 @@ ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS) += smbus.c romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB) += pmclib.c +ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG) += watchdog.c + ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_COMMON),y) verstage-y += pmbase.c diff --git a/src/mainboard/purism/librem_skl/pei_data.h b/src/southbridge/intel/common/tco.h similarity index 58% rename from src/mainboard/purism/librem_skl/pei_data.h rename to src/southbridge/intel/common/tco.h index 320d9803d1..9d6f15326e 100644 --- a/src/mainboard/purism/librem_skl/pei_data.h +++ b/src/southbridge/intel/common/tco.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Purism SPC. + * Copyright (c) 2019 Elyes Haouas * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -13,12 +13,15 @@ * GNU General Public License for more details. */ -#ifndef _MAINBOARD_PEI_DATA_H_ -#define _MAINBOARD_PEI_DATA_H_ +#ifndef SOUTHBRIDGE_INTEL_COMMON_TCO_H +#define SOUTHBRIDGE_INTEL_COMMON_TCO_H -void mainboard_fill_dq_map_data(void *dq_map_ptr); -void mainboard_fill_dqs_map_data(void *dqs_map_ptr); -void mainboard_fill_rcomp_res_data(void *rcomp_ptr); -void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr); +#define PMBASE_TCO_OFFSET 0x60 +#define TCO1_STS 0x04 +#define TCO1_TIMEOUT (1 << 3) +#define TCO2_STS 0x06 +#define SECOND_TO_STS (1 << 1) +#define TCO1_CNT 0x08 +#define TCO_TMR_HLT (1 << 11) -#endif +#endif /* SOUTHBRIDGE_INTEL_COMMON_TCO_H */ diff --git a/src/southbridge/intel/bd82x6x/watchdog.c b/src/southbridge/intel/common/watchdog.c similarity index 67% rename from src/southbridge/intel/bd82x6x/watchdog.c rename to src/southbridge/intel/common/watchdog.c index 6373a39e47..778a7a9f7f 100644 --- a/src/southbridge/intel/bd82x6x/watchdog.c +++ b/src/southbridge/intel/common/watchdog.c @@ -16,17 +16,16 @@ */ #include -#include #include #include #include +#include #include -#include - +#include #include /* - * Disable PCH watchdog timer + * Disable ICH-NM10-PCH watchdog timer */ void watchdog_off(void) { @@ -36,21 +35,25 @@ void watchdog_off(void) /* Get LPC device. */ dev = pcidev_on_root(0x1f, 0); - /* Disable interrupt. */ value = pci_read_config16(dev, PCI_COMMAND); - value |= PCI_COMMAND_INT_DISABLE; + + if (CONFIG(SOUTHBRIDGE_INTEL_FSP_RANGELEY)) { + /* Enable I/O space. */ + value |= PCI_COMMAND_IO; + } else { + /* Disable interrupt. */ + value |= PCI_COMMAND_INT_DISABLE; + } pci_write_config16(dev, PCI_COMMAND, value); /* Disable the watchdog timer. */ - value = read_pmbase16(TCO1_CNT); + value = read_pmbase16(PMBASE_TCO_OFFSET + TCO1_CNT); value |= TCO_TMR_HLT; - write_pmbase16(TCO1_CNT, value); + write_pmbase16(PMBASE_TCO_OFFSET + TCO1_CNT, value); /* Clear TCO timeout status. */ - write_pmbase16(TCO1_STS, TCO1_TIMEOUT); - write_pmbase16(TCO2_STS, SECOND_TO_STS); + write_pmbase16(PMBASE_TCO_OFFSET + TCO1_STS, TCO1_TIMEOUT); + write_pmbase16(PMBASE_TCO_OFFSET + TCO2_STS, SECOND_TO_STS); - /* FIXME: Set RCBA GCS Bit5 "No Reboot" ? */ - - printk(BIOS_DEBUG, "PCH: watchdog disabled\n"); + printk(BIOS_DEBUG, "ICH-NM10-PCH: watchdog disabled\n"); } diff --git a/src/southbridge/intel/fsp_rangeley/Kconfig b/src/southbridge/intel/fsp_rangeley/Kconfig index c15c48d445..4526cb3cf5 100644 --- a/src/southbridge/intel/fsp_rangeley/Kconfig +++ b/src/southbridge/intel/fsp_rangeley/Kconfig @@ -31,6 +31,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy select INTEL_DESCRIPTOR_MODE_CAPABLE select SOUTHBRIDGE_INTEL_COMMON select SOUTHBRIDGE_INTEL_COMMON_SMBUS + select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG config EHCI_BAR hex diff --git a/src/southbridge/intel/fsp_rangeley/Makefile.inc b/src/southbridge/intel/fsp_rangeley/Makefile.inc index ac5888ca38..7fc86012de 100644 --- a/src/southbridge/intel/fsp_rangeley/Makefile.inc +++ b/src/southbridge/intel/fsp_rangeley/Makefile.inc @@ -19,7 +19,6 @@ ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_FSP_RANGELEY),y) ramstage-y += soc.c ramstage-y += lpc.c ramstage-y += sata.c -ramstage-y += watchdog.c ramstage-y += spi.c ramstage-y += smbus.c ramstage-y += acpi.c diff --git a/src/southbridge/intel/fsp_rangeley/watchdog.c b/src/southbridge/intel/fsp_rangeley/watchdog.c deleted file mode 100644 index f18af8927c..0000000000 --- a/src/southbridge/intel/fsp_rangeley/watchdog.c +++ /dev/null @@ -1,53 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2011 Google Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include "soc.h" - -void watchdog_off(void) -{ - struct device *dev; - u32 value, abase; - - /* Turn off the watchdog. */ - dev = pcidev_on_root(0x1f, 0); - - /* Enable I/O space. */ - value = pci_read_config16(dev, 0x04); - value |= 1; - pci_write_config16(dev, 0x04, value); - - /* Get TCO base. */ - abase = (pci_read_config32(dev, ABASE) & ~0xf); - - /* Disable the watchdog timer. */ - value = inw(abase + 0x68); - value |= 1 << 11; - outw(value, abase + 0x68); - - /* Clear TCO timeout status. */ - outw(0x0008, abase + 0x64); - outw(0x0002, abase + 0x66); - - printk(BIOS_DEBUG, "TCO Watchdog disabled\n"); -} diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig index a7d65c52bb..2d6e938eba 100644 --- a/src/southbridge/intel/i82801gx/Kconfig +++ b/src/southbridge/intel/i82801gx/Kconfig @@ -30,6 +30,7 @@ config SOUTHBRIDGE_INTEL_I82801GX select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ select INTEL_HAS_TOP_SWAP select SOUTHBRIDGE_INTEL_COMMON_SMM + select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG if SOUTHBRIDGE_INTEL_I82801GX diff --git a/src/southbridge/intel/i82801gx/Makefile.inc b/src/southbridge/intel/i82801gx/Makefile.inc index b72ca235f5..32a4bf5333 100644 --- a/src/southbridge/intel/i82801gx/Makefile.inc +++ b/src/southbridge/intel/i82801gx/Makefile.inc @@ -30,8 +30,6 @@ ramstage-y += usb_ehci.c ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c -ramstage-y += watchdog.c - smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c romstage-y += early_smbus.c diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index 3db5d49f3f..a91ffc500b 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -89,12 +89,12 @@ int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes, #define RTC_POWER_FAILED (1 << 1) #define SLEEP_AFTER_POWER_FAIL (1 << 0) -#define PMBASE 0x40 #define ACPI_CNTL 0x44 #define ACPI_EN (1 << 7) #define BIOS_CNTL 0xDC #define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */ #define GPIO_CNTL 0x4C /* LPC GPIO Control Register */ +#define GPIO_EN (1 << 4) #define PIRQA_ROUT 0x60 #define PIRQB_ROUT 0x61 diff --git a/src/southbridge/intel/i82801gx/pci.c b/src/southbridge/intel/i82801gx/pci.c index c54769fff3..22c516581f 100644 --- a/src/southbridge/intel/i82801gx/pci.c +++ b/src/southbridge/intel/i82801gx/pci.c @@ -46,9 +46,6 @@ static void pci_init(struct device *dev) reg8 |= (0x04 << 3); pci_write_config8(dev, SMLT, reg8); - /* Will this improve throughput of bus masters? */ - pci_write_config8(dev, PCI_MIN_GNT, 0x06); - /* Clear errors in status registers */ reg16 = pci_read_config16(dev, PSTS); //reg16 |= 0xf900; diff --git a/src/southbridge/intel/i82801gx/watchdog.c b/src/southbridge/intel/i82801gx/watchdog.c deleted file mode 100644 index 12284b46c1..0000000000 --- a/src/southbridge/intel/i82801gx/watchdog.c +++ /dev/null @@ -1,50 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include - -void watchdog_off(void) -{ - struct device *dev; - unsigned long value, base; - - /* Turn off the ICH7 watchdog. */ - dev = pcidev_on_root(0x1f, 0); - - /* Enable I/O space. */ - value = pci_read_config16(dev, 0x04); - value |= (1 << 10); - pci_write_config16(dev, 0x04, value); - - /* Get TCO base. */ - base = (pci_read_config32(dev, 0x40) & 0x0fffe) + 0x60; - - /* Disable the watchdog timer. */ - value = inw(base + 0x08); - value |= 1 << 11; - outw(value, base + 0x08); - - /* Clear TCO timeout status. */ - outw(0x0008, base + 0x04); - outw(0x0002, base + 0x06); - - printk(BIOS_DEBUG, "ICH7 watchdog disabled\n"); -} diff --git a/src/southbridge/intel/i82801ix/Kconfig b/src/southbridge/intel/i82801ix/Kconfig index 44b2cbc0e6..a2697739a8 100644 --- a/src/southbridge/intel/i82801ix/Kconfig +++ b/src/southbridge/intel/i82801ix/Kconfig @@ -29,6 +29,7 @@ config SOUTHBRIDGE_INTEL_I82801IX select SOUTHBRIDGE_INTEL_COMMON_PMCLIB select INTEL_DESCRIPTOR_MODE_CAPABLE select ACPI_INTEL_HARDWARE_SLEEP_VALUES + select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG if SOUTHBRIDGE_INTEL_I82801IX diff --git a/src/southbridge/intel/i82801ix/Makefile.inc b/src/southbridge/intel/i82801ix/Makefile.inc index 3cc7da5ead..caa493211c 100644 --- a/src/southbridge/intel/i82801ix/Makefile.inc +++ b/src/southbridge/intel/i82801ix/Makefile.inc @@ -29,8 +29,6 @@ ramstage-y += ../common/pciehp.c ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c -ramstage-y += ../i82801gx/watchdog.c - ifneq ($(CONFIG_SMM_TSEG),y) ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/smm/smmrelocate.S diff --git a/src/southbridge/intel/i82801jx/Kconfig b/src/southbridge/intel/i82801jx/Kconfig index be2d2897ba..b423ecae40 100644 --- a/src/southbridge/intel/i82801jx/Kconfig +++ b/src/southbridge/intel/i82801jx/Kconfig @@ -33,6 +33,7 @@ config SOUTHBRIDGE_INTEL_I82801JX select ACPI_INTEL_HARDWARE_SLEEP_VALUES select HAVE_POWER_STATE_AFTER_FAILURE select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE + select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG if SOUTHBRIDGE_INTEL_I82801JX diff --git a/src/southbridge/intel/i82801jx/Makefile.inc b/src/southbridge/intel/i82801jx/Makefile.inc index c333566e0f..6626bb5d33 100644 --- a/src/southbridge/intel/i82801jx/Makefile.inc +++ b/src/southbridge/intel/i82801jx/Makefile.inc @@ -29,8 +29,6 @@ ramstage-y += ../common/pciehp.c ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c -ramstage-y += ../i82801gx/watchdog.c - smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c romstage-y += early_smbus.c diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig index bb6e22cb73..4763133b80 100644 --- a/src/southbridge/intel/ibexpeak/Kconfig +++ b/src/southbridge/intel/ibexpeak/Kconfig @@ -40,6 +40,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy select HAVE_INTEL_CHIPSET_LOCKDOWN select HAVE_POWER_STATE_AFTER_FAILURE select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE + select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG config EHCI_BAR hex diff --git a/src/southbridge/intel/ibexpeak/Makefile.inc b/src/southbridge/intel/ibexpeak/Makefile.inc index 5c890300a4..2fb371841a 100644 --- a/src/southbridge/intel/ibexpeak/Makefile.inc +++ b/src/southbridge/intel/ibexpeak/Makefile.inc @@ -31,7 +31,6 @@ ramstage-y += ../common/pciehp.c ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c ramstage-y += ../bd82x6x/me_status.c -ramstage-y += ../bd82x6x/watchdog.c ramstage-$(CONFIG_ELOG) += ../bd82x6x/elog.c ramstage-y += madt.c diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig index 5573ec96ad..67e20be11f 100644 --- a/src/southbridge/intel/lynxpoint/Kconfig +++ b/src/southbridge/intel/lynxpoint/Kconfig @@ -42,6 +42,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy select COMMON_FADT select HAVE_POWER_STATE_AFTER_FAILURE select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE + select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG config INTEL_LYNXPOINT_LP bool diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc index 04e0bc9909..f0bfa5bcc3 100644 --- a/src/southbridge/intel/lynxpoint/Makefile.inc +++ b/src/southbridge/intel/lynxpoint/Makefile.inc @@ -37,7 +37,6 @@ endif ramstage-y += rcba.c ramstage-y += me_status.c -ramstage-y += watchdog.c ramstage-y += acpi.c ramstage-$(CONFIG_ELOG) += elog.c diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index e8cad388d5..951c69c11c 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -623,7 +623,7 @@ static void pch_lpc_add_mmio_resources(struct device *dev) #define LPC_DEFAULT_IO_RANGE_LOWER 0 #define LPC_DEFAULT_IO_RANGE_UPPER 0x1000 -static inline int pch_io_range_in_default(u16 base, u16 size) +static inline int pch_io_range_in_default(int base, int size) { /* Does it start above the range? */ if (base >= LPC_DEFAULT_IO_RANGE_UPPER) diff --git a/src/southbridge/intel/lynxpoint/pch.c b/src/southbridge/intel/lynxpoint/pch.c index 5cf67aa238..a57bae311d 100644 --- a/src/southbridge/intel/lynxpoint/pch.c +++ b/src/southbridge/intel/lynxpoint/pch.c @@ -100,7 +100,7 @@ static void pch_enable_d3hot(struct device *dev) pci_write_config32(dev, PCH_PCS, reg32); } -/* Set bit in Function Disble register to hide this device */ +/* Set bit in function disable register to hide this device */ void pch_disable_devfn(struct device *dev) { switch (dev->path.pci.devfn) { diff --git a/src/southbridge/intel/lynxpoint/watchdog.c b/src/southbridge/intel/lynxpoint/watchdog.c deleted file mode 100644 index 545d3d50d5..0000000000 --- a/src/southbridge/intel/lynxpoint/watchdog.c +++ /dev/null @@ -1,56 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2011 Google Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include - - // - // Disable PCH Watchdog timer at SB_RCBA+0x3410 - // - // Mmio32((MmPci32(0, 0, 0x1F, 0, 0xF0) & ~BIT0), 0x3410) |= 0x20; - // -void watchdog_off(void) -{ - struct device *dev; - unsigned long value, base; - - /* Turn off the ICH7 watchdog. */ - dev = pcidev_on_root(0x1f, 0); - - /* Enable I/O space. */ - value = pci_read_config16(dev, 0x04); - value |= (1 << 10); - pci_write_config16(dev, 0x04, value); - - /* Get TCO base. */ - base = (pci_read_config32(dev, 0x40) & 0x0fffe) + 0x60; - - /* Disable the watchdog timer. */ - value = inw(base + 0x08); - value |= 1 << 11; - outw(value, base + 0x08); - - /* Clear TCO timeout status. */ - outw(0x0008, base + 0x04); - outw(0x0002, base + 0x06); - - printk(BIOS_DEBUG, "PCH watchdog disabled\n"); -} diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbSmuLib.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbSmuLib.c index 37c9ff19bd..3bf8de5d71 100644 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbSmuLib.c +++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/NbSmuLib.c @@ -527,7 +527,6 @@ NbSmuReadEfuseField ( UINT32 Address; UINT16 Shift; ASSERT (Length <= 32); - ASSERT (Chain <= 0xff); Shift = (Offset - (Offset & ~0x7)); Address = 0xFE000000 | (Chain << 12) | (Offset >> 3); Value = NbSmuReadEfuse (Address, StdHeader); diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbSmuLib.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbSmuLib.c index 76401d435c..bf1396de55 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbSmuLib.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/NbSmuLib.c @@ -506,7 +506,6 @@ NbSmuReadEfuseField ( UINT32 Address; UINT16 Shift; ASSERT (Length <= 32); - ASSERT (Chain <= 0xff); Shift = (Offset - (Offset & ~0x7)); Address = 0xFE000000 | (Chain << 12) | (Offset >> 3); Value = NbSmuReadEfuse (Address, StdHeader); diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnDmi.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnDmi.c index 7b7fa0dd91..b0f98cf01c 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnDmi.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/cpuF15TnDmi.c @@ -331,7 +331,7 @@ DmiF15TnGetVoltage ( LibAmdMsrRead ((MSR_PSTATE_0 + NumberBoostStates), &MsrData, StdHeader); MaxVid = (UINT8) (((PSTATE_MSR *)&MsrData)->CpuVid); - if ((MaxVid >= 0xF8) && (MaxVid <= 0xFF)) { + if ((MaxVid >= 0xF8)) { Voltage = 0; } else { Voltage = (UINT8) ((155000L - (625 * MaxVid) + 5000) / 10000); diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Family/0x15/TN/IdsF15TnAllService.c b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Family/0x15/TN/IdsF15TnAllService.c index 5e76e9a88a..a7cb9547dc 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Family/0x15/TN/IdsF15TnAllService.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/IDS/Family/0x15/TN/IdsF15TnAllService.c @@ -62,6 +62,9 @@ CODE_GROUP (G3_DXE) RDATA_GROUP (G3_DXE) +/* Don't warn when checking header-defined ranges that may start at 0. */ +#pragma GCC diagnostic ignored "-Wtype-limits" + #define FILECODE PROC_IDS_FAMILY_0X15_TN_IDSF15TNALLSERVICE_FILECODE /** diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbDmi.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbDmi.c index 45b1b8f418..6e8e6f06ab 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbDmi.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbDmi.c @@ -287,7 +287,7 @@ DmiF16KbGetVoltage ( LibAmdMsrRead ((MSR_PSTATE_0 + NumberBoostStates), &MsrData, StdHeader); MaxVid = (UINT8) (((PSTATE_MSR *)&MsrData)->CpuVid); - if ((MaxVid >= 0xF8) && (MaxVid <= 0xFF)) { + if ((MaxVid >= 0xF8)) { Voltage = 0; } else { Voltage = (UINT8) ((155000L - (625 * MaxVid) + 5000) / 10000); diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/IDS/Family/0x16/KB/IdsF16KbAllService.c b/src/vendorcode/amd/agesa/f16kb/Proc/IDS/Family/0x16/KB/IdsF16KbAllService.c index fddf8eb403..94e32a3743 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/IDS/Family/0x16/KB/IdsF16KbAllService.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/IDS/Family/0x16/KB/IdsF16KbAllService.c @@ -63,6 +63,9 @@ CODE_GROUP (G3_DXE) RDATA_GROUP (G3_DXE) +/* Don't warn when checking header-defined ranges that may start at 0. */ +#pragma GCC diagnostic ignored "-Wtype-limits" + #define FILECODE PROC_IDS_FAMILY_0X16_KB_IDSF16KBALLSERVICE_FILECODE /** diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mpmaxfreq.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mpmaxfreq.c index 1302396909..eba8263e34 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mpmaxfreq.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mpmaxfreq.c @@ -136,7 +136,7 @@ MemPGetMaxFreqSupported ( UINT16 MaxFreqSupported; UINT16 *SpeedArray; UINT8 DDR3Voltage; - UINT8 CurrentVoltage; + INT8 CurrentVoltage; DIMM_TYPE DimmType; CPU_LOGICAL_ID LogicalCpuid; UINT8 PackageType; diff --git a/src/vendorcode/amd/pi/00670F00/binaryPI/AGESA.c b/src/vendorcode/amd/pi/00670F00/binaryPI/AGESA.c index 2efee4eb62..e17cedcb64 100644 --- a/src/vendorcode/amd/pi/00670F00/binaryPI/AGESA.c +++ b/src/vendorcode/amd/pi/00670F00/binaryPI/AGESA.c @@ -72,157 +72,3 @@ AmdReleaseStruct ( if (!Dispatcher) return AGESA_UNSUPPORTED; return Dispatcher(InterfaceParams); } - -/********************************************************************** - * Interface call: AmdInitReset - **********************************************************************/ -AGESA_STATUS -AmdInitReset ( - IN OUT AMD_RESET_PARAMS *ResetParams - ) -{ - MODULE_ENTRY Dispatcher = agesa_get_dispatcher(); - ResetParams->StdHeader.Func = AMD_INIT_RESET; - if (!Dispatcher) return AGESA_UNSUPPORTED; - return Dispatcher(ResetParams); -} - -/********************************************************************** - * Interface call: AmdInitEarly - **********************************************************************/ -AGESA_STATUS -AmdInitEarly ( - IN OUT AMD_EARLY_PARAMS *EarlyParams - ) -{ - MODULE_ENTRY Dispatcher = agesa_get_dispatcher(); - EarlyParams->StdHeader.Func = AMD_INIT_EARLY; - if (!Dispatcher) return AGESA_UNSUPPORTED; - return Dispatcher(EarlyParams); -} - -/********************************************************************** - * Interface call: AmdInitPost - **********************************************************************/ -AGESA_STATUS -AmdInitPost ( - IN OUT AMD_POST_PARAMS *PostParams ///< Amd Cpu init param - ) -{ - MODULE_ENTRY Dispatcher = agesa_get_dispatcher(); - PostParams->StdHeader.Func = AMD_INIT_POST; - if (!Dispatcher) return AGESA_UNSUPPORTED; - return Dispatcher(PostParams); -} - -/********************************************************************** - * Interface call: AmdInitEnv - **********************************************************************/ -AGESA_STATUS -AmdInitEnv ( - IN OUT AMD_ENV_PARAMS *EnvParams - ) -{ - MODULE_ENTRY Dispatcher = agesa_get_dispatcher(); - EnvParams->StdHeader.Func = AMD_INIT_ENV; - if (!Dispatcher) return AGESA_UNSUPPORTED; - return Dispatcher(EnvParams); -} - -/********************************************************************** - * Interface call: AmdInitMid - **********************************************************************/ -AGESA_STATUS -AmdInitMid ( - IN OUT AMD_MID_PARAMS *MidParams - ) -{ - MODULE_ENTRY Dispatcher = agesa_get_dispatcher(); - MidParams->StdHeader.Func = AMD_INIT_MID; - if (!Dispatcher) return AGESA_UNSUPPORTED; - return Dispatcher(MidParams); -} - -/********************************************************************** - * Interface call: AmdInitLate - **********************************************************************/ -AGESA_STATUS -AmdInitLate ( - IN OUT AMD_LATE_PARAMS *LateParams - ) -{ - MODULE_ENTRY Dispatcher = agesa_get_dispatcher(); - LateParams->StdHeader.Func = AMD_INIT_LATE; - if (!Dispatcher) return AGESA_UNSUPPORTED; - return Dispatcher(LateParams); -} - -/********************************************************************** - * Interface call: AmdInitResume - **********************************************************************/ -AGESA_STATUS -AmdInitResume ( - IN AMD_RESUME_PARAMS *ResumeParams - ) -{ - MODULE_ENTRY Dispatcher = agesa_get_dispatcher(); - ResumeParams->StdHeader.Func = AMD_INIT_RESUME; - if (!Dispatcher) return AGESA_UNSUPPORTED; - return Dispatcher(ResumeParams); -} - -/********************************************************************** - * Interface call: AmdS3LateRestore - **********************************************************************/ -AGESA_STATUS -AmdS3LateRestore ( - IN OUT AMD_S3LATE_PARAMS *S3LateParams - ) -{ - MODULE_ENTRY Dispatcher = agesa_get_dispatcher(); - S3LateParams->StdHeader.Func = AMD_S3LATE_RESTORE; - if (!Dispatcher) return AGESA_UNSUPPORTED; - return Dispatcher(S3LateParams); -} - -/********************************************************************** - * Interface call: AmdS3FinalRestore - **********************************************************************/ -AGESA_STATUS -AmdS3FinalRestore ( - IN OUT AMD_S3FINAL_PARAMS *S3FinalParams - ) -{ - MODULE_ENTRY Dispatcher = agesa_get_dispatcher(); - S3FinalParams->StdHeader.Func = AMD_S3FINAL_RESTORE; - if (!Dispatcher) return AGESA_UNSUPPORTED; - return Dispatcher(S3FinalParams); -} - -/********************************************************************** - * Interface call: AmdInitRtb - **********************************************************************/ -AGESA_STATUS -AmdInitRtb ( - IN OUT AMD_RTB_PARAMS *AmdInitRtbParams - ) -{ - MODULE_ENTRY Dispatcher = agesa_get_dispatcher(); - AmdInitRtbParams->StdHeader.Func = AMD_INIT_RTB; - if (!Dispatcher) return AGESA_UNSUPPORTED; - return Dispatcher(AmdInitRtbParams); -} - -/********************************************************************** - * Interface call: AmdLateRunApTask - **********************************************************************/ -AGESA_STATUS -AmdLateRunApTask ( - IN AP_EXE_PARAMS *AmdApExeParams -) -{ - MODULE_ENTRY Dispatcher = agesa_get_dispatcher(); - AmdApExeParams->StdHeader.Func = AMD_LATE_RUN_AP_TASK; - if (!Dispatcher) return AGESA_UNSUPPORTED; - return Dispatcher(AmdApExeParams); -} diff --git a/src/vendorcode/google/chromeos/acpi/amac.asl b/src/vendorcode/google/chromeos/acpi/amac.asl index 51159f5124..c87862f6ff 100644 --- a/src/vendorcode/google/chromeos/acpi/amac.asl +++ b/src/vendorcode/google/chromeos/acpi/amac.asl @@ -42,6 +42,7 @@ Scope (\_SB) /* Get "dock_passthru" value from RW_VPD */ Local0 = \VPD.VPDF ("RW", "dock_passthru") + Local1 = Zero Switch (ToString (Local0)) { Case ("ethernet_mac0") { @@ -55,7 +56,7 @@ Scope (\_SB) Local1 = \VPD.VPDF ("RO", "dock_mac") } } - If (!Local1) { + If (Local1 == Zero) { Return (Zero) } Printf ("MAC address returned from VPD: %o", Local1) diff --git a/src/vendorcode/google/chromeos/acpi/vpd.asl b/src/vendorcode/google/chromeos/acpi/vpd.asl index 3b262f75a8..8f8b0e571d 100644 --- a/src/vendorcode/google/chromeos/acpi/vpd.asl +++ b/src/vendorcode/google/chromeos/acpi/vpd.asl @@ -139,7 +139,7 @@ Device (VPD) Local1 <<= 7 Local1 |= Local2 & 0x7f } - If (!Local1) { + If (Local1 == Zero) { Return (Zero) } @@ -162,7 +162,7 @@ Device (VPD) */ Method (VPDS, 0, Serialized) { - Name (VPKV, Package () { Zero, Zero }) + Name (VPKV, Package () { "", "" }) /* Read the VPD type and ensure it is a string */ If (^VPRB () != ^VPES) { @@ -193,14 +193,14 @@ Device (VPD) /* End address of VPD region */ ^VEND = ^VPTR + DerefOf (Local0[1]) - If (!^VPTR || !^VEND) { + If (^VPTR == Zero || ^VEND == Zero) { Printf ("Unable to find VPD region") Return (Zero) } /* Verify VPD info header and save size */ Local0 = VVPD (^VPTR) - If (!Local0) { + If (Local0 == Zero) { Printf ("VPD region %o did not verify", Arg0) Return (Zero) } @@ -213,7 +213,7 @@ Device (VPD) While (Local1 != ToString (Arg1)) { Local2 = VPDS () Local1 = DerefOf (Local2[0]) - If (!Local1) { + If (Local1 == "") { Printf ("VPD KEY %o not found", Arg1) Return (Zero) } diff --git a/util/cbfstool/Makefile.inc b/util/cbfstool/Makefile.inc index 1787eb14c0..79285207b0 100644 --- a/util/cbfstool/Makefile.inc +++ b/util/cbfstool/Makefile.inc @@ -81,7 +81,6 @@ TOOLCPPFLAGS += -I$(top)/util/cbfstool TOOLCPPFLAGS += -I$(objutil)/cbfstool TOOLCPPFLAGS += -I$(top)/src/commonlib/include TOOLCPPFLAGS += -include $(top)/src/commonlib/include/commonlib/compiler.h -TOOLCPPFLAGS += -DNEED_VB2_SHA_LIBRARY TOOLCPPFLAGS += -I$(VBOOT_SOURCE)/firmware/include TOOLCPPFLAGS += -I$(VBOOT_SOURCE)/firmware/2lib/include # UEFI header file support. It's not pretty, but that's what we currently diff --git a/util/cbfstool/cbfs_image.c b/util/cbfstool/cbfs_image.c index 5ff81309f4..5cbe1f185a 100644 --- a/util/cbfstool/cbfs_image.c +++ b/util/cbfstool/cbfs_image.c @@ -22,6 +22,7 @@ #include #include #include +#include #include "common.h" #include "cbfs_image.h" diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c index ae1d2127fb..52fdc9b81f 100644 --- a/util/cbmem/cbmem.c +++ b/util/cbmem/cbmem.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include #include diff --git a/util/ectool/ectool.c b/util/ectool/ectool.c index bc3d46cd52..2af45c30f2 100644 --- a/util/ectool/ectool.c +++ b/util/ectool/ectool.c @@ -22,7 +22,6 @@ #include #endif #include -#include #if defined __NetBSD__ || defined __OpenBSD__ diff --git a/util/inteltool/gpio.c b/util/inteltool/gpio.c index 41f4df90c8..c946d5c65f 100644 --- a/util/inteltool/gpio.c +++ b/util/inteltool/gpio.c @@ -1028,9 +1028,13 @@ int print_gpios(struct pci_dev *sb, int show_all, int show_diffs) case PCI_DEVICE_ID_INTEL_CM236: case PCI_DEVICE_ID_INTEL_APL_LPC: case PCI_DEVICE_ID_INTEL_DNV_LPC: - case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE: - case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM: - case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_PRE: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_SKL: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_SKL: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_SKL: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_KBL: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_KBL: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_KBL: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_BASE: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_PREM: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_IHDCP_PREM: diff --git a/util/inteltool/gpio_groups.c b/util/inteltool/gpio_groups.c index 8b328a7383..21e2de93d5 100644 --- a/util/inteltool/gpio_groups.c +++ b/util/inteltool/gpio_groups.c @@ -1778,9 +1778,13 @@ void print_gpio_groups(struct pci_dev *const sb) communities = sunrise_communities; pcr_init(sb); break; - case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE: - case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM: - case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_PRE: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_SKL: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_SKL: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_SKL: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_KBL: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_KBL: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_KBL: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_BASE: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_PREM: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_IHDCP_PREM: diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index e89fd3cf22..40e7646450 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -224,18 +224,26 @@ static const struct { { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_LPC, "Bay Trail" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_PRE, "Sunrise Point Desktop Engineering Sample" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE, - "Sunrise Point-LP U Base" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM, - "Sunrise Point-LP U Premium" }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM, - "Sunrise Point-LP Y Premium" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_PRE, + "Sunrise Point-LP Engineering Sample" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_SKL, + "Sunrise Point-LP U Base/Skylake" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_SKL, + "Sunrise Point-LP Y Premium/Skylake" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_SKL, + "Sunrise Point-LP U Premium/Skylake" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_KBL, + "Sunrise Point-LP U Base/Kabylake" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_KBL, + "Sunrise Point-LP Y Premium/Kabylake" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_KBL, + "Sunrise Point-LP U Premium/Kabylake" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_BASE, - "Sunrise Point-LP U iHDCP 2.2 Base" }, + "Sunrise Point-LP U iHDCP 2.2 Base/Kabylake" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_PREM, - "Sunrise Point-LP U iHDCP 2.2 Premium" }, + "Sunrise Point-LP U iHDCP 2.2 Premium/Kabylake" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_IHDCP_PREM, - "Sunrise Point-LP Y iHDCP 2.2 Premium" }, + "Sunrise Point-LP Y iHDCP 2.2 Premium/Kabylake" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H110, "H110" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H170, "H170" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Z170, "Z170" }, diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index 25b3a1504a..6aec3879c2 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -145,9 +145,13 @@ static inline uint32_t inl(unsigned port) #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_P2SB 0xa120 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_PRE 0xa141 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SATA 0x9d03 -#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE 0x9d53 -#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM 0x9d58 -#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM 0x9d56 +#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_PRE 0x9d41 +#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_SKL 0x9d43 +#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_SKL 0x9d46 +#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_SKL 0x9d48 +#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_KBL 0x9d53 +#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_KBL 0x9d56 +#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_KBL 0x9d58 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_BASE 0x9d50 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_PREM 0x9d4e #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_IHDCP_PREM 0x9d4b diff --git a/util/inteltool/pcr.c b/util/inteltool/pcr.c index a296b19be4..c969620fa0 100644 --- a/util/inteltool/pcr.c +++ b/util/inteltool/pcr.c @@ -79,9 +79,13 @@ void pcr_init(struct pci_dev *const sb) switch (sb->device_id) { case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_PRE: - case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE: - case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM: - case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_PRE: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_SKL: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_SKL: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_SKL: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_KBL: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_KBL: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_KBL: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_BASE: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_PREM: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_IHDCP_PREM: diff --git a/util/inteltool/powermgt.c b/util/inteltool/powermgt.c index 359180093d..675e31a1da 100644 --- a/util/inteltool/powermgt.c +++ b/util/inteltool/powermgt.c @@ -745,9 +745,13 @@ int print_pmbase(struct pci_dev *sb, struct pci_access *pacc) case PCI_DEVICE_ID_INTEL_C224: case PCI_DEVICE_ID_INTEL_C226: case PCI_DEVICE_ID_INTEL_H81: - case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE: - case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM: - case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_PRE: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_SKL: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_SKL: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_SKL: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_KBL: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_KBL: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_KBL: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_BASE: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_PREM: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_IHDCP_PREM: diff --git a/util/inteltool/rootcmplx.c b/util/inteltool/rootcmplx.c index ddcd8e3ed3..70d7cbe3ed 100644 --- a/util/inteltool/rootcmplx.c +++ b/util/inteltool/rootcmplx.c @@ -112,9 +112,13 @@ int print_rcba(struct pci_dev *sb) case PCI_DEVICE_ID_INTEL_C224: case PCI_DEVICE_ID_INTEL_C226: case PCI_DEVICE_ID_INTEL_H81: - case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE: - case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM: - case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_PRE: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_SKL: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_SKL: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_SKL: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_KBL: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_KBL: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_KBL: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_BASE: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_PREM: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_IHDCP_PREM: diff --git a/util/inteltool/spi.c b/util/inteltool/spi.c index cb38c55587..da5533deaa 100644 --- a/util/inteltool/spi.c +++ b/util/inteltool/spi.c @@ -175,9 +175,13 @@ int print_bioscntl(struct pci_dev *sb) case PCI_DEVICE_ID_INTEL_C224: case PCI_DEVICE_ID_INTEL_C226: case PCI_DEVICE_ID_INTEL_H81: - case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE: - case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM: - case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_PRE: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_SKL: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_SKL: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_SKL: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_KBL: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_KBL: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_KBL: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_BASE: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_PREM: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_IHDCP_PREM: @@ -309,9 +313,13 @@ int print_spibar(struct pci_dev *sb) { case PCI_DEVICE_ID_INTEL_C224: case PCI_DEVICE_ID_INTEL_C226: case PCI_DEVICE_ID_INTEL_H81: - case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE: - case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM: - case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_PRE: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_SKL: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_SKL: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_SKL: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_KBL: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_KBL: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_KBL: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_BASE: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_PREM: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_IHDCP_PREM: diff --git a/util/ipqheader/createxbl.py b/util/qualcomm/createxbl.py similarity index 96% rename from util/ipqheader/createxbl.py rename to util/qualcomm/createxbl.py index 1efd8bac0c..4a218544c0 100755 --- a/util/ipqheader/createxbl.py +++ b/util/qualcomm/createxbl.py @@ -6,7 +6,7 @@ # GENERAL DESCRIPTION # Concatentates XBL segments into one ELF image # -# Copyright (c) 2016, The Linux Foundation. All rights reserved. +# Copyright (c) 2016, 2018, The Linux Foundation. All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are @@ -44,6 +44,7 @@ # # when who what, where, why # -------- --- ------------------------------------------------------ +# 03/26/18 tv Added -e to enable extended MBNV5 support # 09/04/15 et Added -x and -d to embed xbl_sec ELF # 02/11/15 ck Fixed missing elf type check in ZI OOB feature # 11/04/14 ck Updated calls to mbn_tools functions @@ -205,6 +206,11 @@ def main(): else: zi_oob_enabled = True + if options.elf_inp_xbl_sec: + is_ext_mbn_v5 = True + else: + is_ext_mbn_v5 = False + mbn_type = 'elf' header_format = 'reg' @@ -237,7 +243,8 @@ def main(): is_elf2_64_bit, is_elf_xbl_sec_64_bit, is_out_elf_64_bit, - zi_oob_enabled) + zi_oob_enabled, + is_ext_mbn_v5) # Hash the image if user did not explicitly say not to @@ -262,6 +269,7 @@ def main(): target_hash, target_hash_hd, image_header_secflag, + is_ext_mbn_v5, elf_file_name = source_elf) if rv: raise RuntimeError, "Failed to create image header for hash segment" @@ -296,7 +304,8 @@ def merge_elfs(env, is_elf2_64_bit, is_elf_xbl_sec_64_bit, is_out_elf_64_bit, - zi_oob_enabled): + zi_oob_enabled, + is_ext_mbn_v5): [elf_header1, phdr_table1] = \ mbn_tools.preprocess_elf_file(elf_in_file_name1) @@ -654,7 +663,12 @@ def merge_elfs(env, new_phdr.p_paddr = phys_virt_addr new_phdr.p_filesz = os.path.getsize(elf_in_file_xbl_sec) new_phdr.p_memsz = new_phdr.p_filesz - new_phdr.p_flags = 0x5 + if is_ext_mbn_v5 == True: + new_phdr.p_flags = (0x5 | + (mbn_tools.MI_PBT_XBL_SEC_SEGMENT << + mbn_tools.MI_PBT_FLAG_SEGMENT_TYPE_SHIFT)); + else: + new_phdr.p_flags = 0x5 new_phdr.p_align = 0x1000 else: # Converting from 64 to 32 elf requires data size validation @@ -663,18 +677,23 @@ def merge_elfs(env, new_phdr = mbn_tools.Elf32_Phdr('\0' * ELF32_PHDR_SIZE) new_phdr.p_type = 0x1 # new_phdr.p_offset = segment_offset - new_phdr.p_flags = 0x5 + if is_ext_mbn_v5 == True: + new_phdr.p_flags = (0x5 | + (mbn_tools.MI_PBT_XBL_SEC_SEGMENT << + mbn_tools.MI_PBT_FLAG_SEGMENT_TYPE_SHIFT)); + else: + new_phdr.p_flags = 0x5 new_phdr.p_align = 0x1000 if phys_virt_addr > 0xFFFFFFFF: if zi_oob_enabled == False or curr_phdr.p_filesz != 0: - print "ERROR: File xbl_sec VAddr or PAddr is too large for conversion." + print "ERROR: File xbl_sec VAddr or PAddr is too big for conversion." exit() new_phdr.p_vaddr = phys_virt_addr new_phdr.p_paddr = phys_virt_addr if os.path.getsize(elf_in_file_xbl_sec) > 0xFFFFFFFF: - print "ERROR: File xbl_sec Filesz is too large for conversion." + print "ERROR: File xbl_sec Filesz is too big for conversion." exit() new_phdr.p_filesz = os.path.getsize(elf_in_file_xbl_sec) new_phdr.p_memsz = new_phdr.p_filesz diff --git a/util/ipqheader/ipqheader.py b/util/qualcomm/ipqheader.py similarity index 100% rename from util/ipqheader/ipqheader.py rename to util/qualcomm/ipqheader.py diff --git a/util/ipqheader/mbn_tools.py b/util/qualcomm/mbn_tools.py similarity index 99% rename from util/ipqheader/mbn_tools.py rename to util/qualcomm/mbn_tools.py index c66afda7b5..12dc210cac 100755 --- a/util/ipqheader/mbn_tools.py +++ b/util/qualcomm/mbn_tools.py @@ -6,7 +6,7 @@ # GENERAL DESCRIPTION # Contains all MBN Utilities for image generation # -# Copyright (c) 2016, The Linux Foundation. All rights reserved. +# Copyright (c) 2016, 2018, The Linux Foundation. All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are @@ -41,6 +41,7 @@ # # when who what, where, why # -------- --- --------------------------------------------------------- +# 03/22/18 thiru Added support for extended MBNV5. # 06/06/13 yliong CR 497042: Signed and encrypted image is corrupted. MRC features. # 03/18/13 dhaval Add support for hashing elf segments with SHA256 and # sync up to mpss, adsp mbn-tools @@ -166,6 +167,7 @@ MI_PBT_HASH_SEGMENT = 0x2 MI_PBT_BOOT_SEGMENT = 0x3 MI_PBT_L4BSP_SEGMENT = 0x4 MI_PBT_SWAPPED_SEGMENT = 0x5 +MI_PBT_XBL_SEC_SEGMENT = 0x5 MI_PBT_SWAP_POOL_SEGMENT = 0x6 MI_PBT_PHDR_SEGMENT = 0x7 @@ -902,6 +904,7 @@ def image_header(env, gen_dict, code_file_name, output_file_name, secure_type, + is_ext_mbn_v5, header_format = 'reg', requires_preamble = False, preamble_file_name = None, @@ -989,6 +992,12 @@ def image_header(env, gen_dict, boot_header.cert_chain_ptr = image_dest + code_size + signature_size boot_header.cert_chain_size = cert_chain_size + if is_ext_mbn_v5 == True: + # If platform image integrity check is enabled + boot_header.flash_parti_ver = 5 # version + boot_header.image_src = 0 # sig_size_qc + boot_header.image_dest_ptr = 0 # cert_chain_size_qc + # If preamble is required, output the preamble file and update the boot_header if requires_preamble is True: boot_header = image_preamble(gen_dict, preamble_file_name, boot_header, num_of_pages) @@ -2051,7 +2060,7 @@ def get_hash_address(elf_file_name): curr_phdr = phdr_table[i] if curr_phdr.p_paddr > last_paddr: # Skip the demand paging segment as it would be outside the physical RAM location - if MI_PBT_SEGMENT_TYPE_VALUE(curr_phdr.p_flags) != MI_PBT_SWAPPED_SEGMENT: + if MI_PBT_SEGMENT_TYPE_VALUE(curr_phdr.p_flags) != MI_PBT_XBL_SEC_SEGMENT: last_paddr = curr_phdr.p_paddr; last_paddr_segment = i; diff --git a/util/ipqheader/mbncat.py b/util/qualcomm/mbncat.py similarity index 100% rename from util/ipqheader/mbncat.py rename to util/qualcomm/mbncat.py diff --git a/util/qualcomm/qgpt.py b/util/qualcomm/qgpt.py new file mode 100755 index 0000000000..51018361e1 --- /dev/null +++ b/util/qualcomm/qgpt.py @@ -0,0 +1,234 @@ +#!/usr/bin/python +#============================================================================ +# +#/** @file qgpt.py +# +# GENERAL DESCRIPTION +# Generates QCom GPT header for wrapping Bootblock +# +# Copyright (c) 2018, The Linux Foundation. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above +# copyright notice, this list of conditions and the following +# disclaimer in the documentation and/or other materials provided +# with the distribution. +# * Neither the name of The Linux Foundation nor the names of its +# contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED +# WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS +# BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +# BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE +# OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN +# IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +#**/ +# + +import os +import math +import random +import re +import struct +import sys +import tempfile + +from binascii import crc32 +from optparse import OptionParser +from types import * + + +def UpdateMBR(options, GPTBlobBuffer): + i = 0x1BE + GPTBlobBuffer[i + 0] = 0x00 # not bootable + GPTBlobBuffer[i + 1] = 0x00 # head + GPTBlobBuffer[i + 2] = 0x01 # sector + GPTBlobBuffer[i + 3] = 0x00 # cylinder + GPTBlobBuffer[i + 4] = 0xEE # type + GPTBlobBuffer[i + 5] = 0xFF # head + GPTBlobBuffer[i + 6] = 0xFF # sector + GPTBlobBuffer[i + 7] = 0xFF # cylinder + GPTBlobBuffer[i + 8:i + 8 + 4] = [0x01, 0x00, 0x00, 0x00] + + GPTBlobBuffer[i + 12:i + 16] = [0x00, 0x0f, 0x00, 0x00] + + # magic byte for MBR partitioning - always at this location regardless of + # options.sector + GPTBlobBuffer[510:512] = [0x55, 0xAA] + return i + + +def UpdatePartitionEntry(options, GPTBlobBuffer): + + i = 2 * options.sector_size + # GUID of Boot Block + GPTBlobBuffer[i:i + 16] = [0x2c, 0xba, 0xa0, 0xde, 0xdd, 0xcb, 0x05, 0x48, + 0xb4, 0xf9, 0xf4, 0x28, 0x25, 0x1c, 0x3e, 0x98] + i += 16 + + #This is to set Unique Partition GUID. Below Hex Value is : 00ChezaBootblock00 + GPTBlobBuffer[i:i + 16] = [0x00, 0x43, 0x68, 0x65, 0x7a, 0x61, 0x42, 0x6f, + 0x6f, 0x74, 0x62, 0x6c, 0x6f, 0x63, 0x6b, 0x00] + i += 16 + + # LBA of BootBlock Start Content + GPTBlobBuffer[i:i + 8] = [0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00] + i += 8 + + # End LBA of BootBlock Content + GPTBlobBuffer[i] = options.end_lba & 0xFF + GPTBlobBuffer[i+1] = (options.end_lba>>8) & 0xFF + GPTBlobBuffer[i+2] = (options.end_lba>>16) & 0xFF + GPTBlobBuffer[i+3] = (options.end_lba>>24) & 0xFF + GPTBlobBuffer[i+4] = (options.end_lba>>32) & 0xFF + GPTBlobBuffer[i+5] = (options.end_lba>>40) & 0xFF + GPTBlobBuffer[i+6] = (options.end_lba>>48) & 0xFF + GPTBlobBuffer[i+7] = (options.end_lba>>56) & 0xFF + i += 8 + + # Attributes + GPTBlobBuffer[i:i + 8] = [0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00] + i += 8 + + # Label + GPTBlobBuffer[i:i + 17] = [0x62, 0x00, 0x6f, 0x00, 0x6f, 0x00, 0x74, 0x00, + 0x62, 0x00, 0x6c, 0x00, 0x6f, 0x00, 0x63, 0x00, 0x6b] + + return i + +def UpdateGPTHeader(options, GPTBlobBuffer): + + i = options.sector_size + # Signature and Revision and HeaderSize i.e. "EFI PART" and 00 00 01 00 + # and 5C 00 00 00 + GPTBlobBuffer[i:i + 16] = [0x45, 0x46, 0x49, 0x20, 0x50, 0x41, 0x52, 0x54, + 0x00, 0x00, 0x01, 0x00, 0x5C, 0x00, 0x00, 0x00] + i += 16 + + # CRC is zeroed out till calculated later + GPTBlobBuffer[i:i + 4] = [0x00, 0x00, 0x00, 0x00] + i += 4 + + # Reserved, set to 0 + GPTBlobBuffer[i:i + 4] = [0x00, 0x00, 0x00, 0x00] + i += 4 + + # Current LBA + GPTBlobBuffer[i:i + 8] = [0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00] + i += 8 + + # Backup LBA, No Backup Gpt Used + GPTBlobBuffer[i:i + 8] = [0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00] + i += 8 + + # First Usuable LBA (qc_sec + bootblock location) + GPTBlobBuffer[i:i + 8] = [0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00] + i += 8 + + # Last Usuable LBA (qc_sec + bootblock end location) + GPTBlobBuffer[i] = options.end_lba & 0xFF + GPTBlobBuffer[i+1] = (options.end_lba>>8) & 0xFF + GPTBlobBuffer[i+2] = (options.end_lba>>16) & 0xFF + GPTBlobBuffer[i+3] = (options.end_lba>>24) & 0xFF + GPTBlobBuffer[i+4] = (options.end_lba>>32) & 0xFF + GPTBlobBuffer[i+5] = (options.end_lba>>40) & 0xFF + GPTBlobBuffer[i+6] = (options.end_lba>>48) & 0xFF + GPTBlobBuffer[i+7] = (options.end_lba>>56) & 0xFF + i += 8 + + # GUID + GPTBlobBuffer[i:i + 16] = [0x32,0x1B,0x10,0x98,0xE2,0xBB,0xF2,0x4B, + 0xA0,0x6E,0x2B,0xB3,0x3D,0x00,0x0C,0x20] + i += 16 + + # Partition Table Entry LBA + GPTBlobBuffer[i:i + 8] = [0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00] + i += 8 + + # Number of Partition Entries + GPTBlobBuffer[i:i + 4] = [0x01, 0x00, 0x00, 0x00] + i += 4 + + # Size of One Partition Entry + GPTBlobBuffer[i:i + 4] = [0x80, 0x00, 0x00, 0x00] + i += 4 + + # CRC of Partition Entry + + PartEntry = GPTBlobBuffer[options.sector_size*2:options.sector_size*2 + 128] + CalcEntryCRC = crc32(''.join(struct.pack("B", x) for x in PartEntry)) + + GPTBlobBuffer[i] = CalcEntryCRC & 0xFF + GPTBlobBuffer[i+1] = (CalcEntryCRC>>8) & 0xFF + GPTBlobBuffer[i+2] = (CalcEntryCRC>>16) & 0xFF + GPTBlobBuffer[i+3] = (CalcEntryCRC>>24) & 0xFF + i += 4 + + # CRC of Partition Table Header + GPTHeader = GPTBlobBuffer[options.sector_size:options.sector_size + 92] + CalcEntryCRC = crc32(''.join(struct.pack("B", x) for x in GPTHeader)) + i = options.sector_size + 16 + + GPTBlobBuffer[i] = CalcEntryCRC & 0xFF + GPTBlobBuffer[i+1] = (CalcEntryCRC>>8) & 0xFF + GPTBlobBuffer[i+2] = (CalcEntryCRC>>16) & 0xFF + GPTBlobBuffer[i+3] = (CalcEntryCRC>>24) & 0xFF + + return i + + +if __name__ == '__main__': + usage = 'usage: %prog [OPTIONS] INFILE OUTFILE\n\n' + \ + 'Packages IMAGE in a GPT format.' + parser = OptionParser(usage) + parser.add_option('-s', type="int", dest='sector_size', default=4096, + help='Sector size in bytes [Default:4096(4KB)]', + metavar='SIZE') + + (options, args) = parser.parse_args() + if len(args) != 2: + print("Invalid arguments! Exiting...\n") + parser.print_help() + sys.exit(1) + + if options.sector_size != 4096 and options.sector_size != 512: + print("Invalid Sector Size") + sys.exit(1) + + options.inputfile = args[0] + options.outputfile = args[1] + + with open(options.inputfile, 'r+') as fin: + bb_buffer = fin.read() + + # Round up to next sector if bootblock size not evenly divisible + options.end_lba = ((len(bb_buffer) + options.sector_size - 1) / + options.sector_size) + # Add 3 sectors for MBR, GPT header and GPT partition entry + options.end_lba += 3 + # Subtract one because this is last usable LBA, not amount of LBAs + options.end_lba -= 1 + + GPTBlobBuffer = [0] * (options.sector_size*3) #Size of MBR+GPT+PART_ENTRY + + UpdateMBR(options, GPTBlobBuffer) + + UpdatePartitionEntry(options, GPTBlobBuffer) + + UpdateGPTHeader(options, GPTBlobBuffer) + + with open(options.outputfile, 'wb') as fout: + for b in GPTBlobBuffer: + fout.write(struct.pack("B", b)) + fout.write(bb_buffer) diff --git a/util/romcc/romcc.c b/util/romcc/romcc.c index 4cb2aadcc9..43be171213 100644 --- a/util/romcc/romcc.c +++ b/util/romcc/romcc.c @@ -16,7 +16,6 @@ #include #include #include -#include #include #include #include diff --git a/util/sconfig/lex.yy.c_shipped b/util/sconfig/lex.yy.c_shipped index b3dff41e58..14ffeff9a2 100644 --- a/util/sconfig/lex.yy.c_shipped +++ b/util/sconfig/lex.yy.c_shipped @@ -168,7 +168,7 @@ extern FILE *yyin, *yyout; do \ { \ /* Undo effects of setting up yytext. */ \ - int yyless_macro_arg = (n); \ + yy_size_t yyless_macro_arg = (n); \ YY_LESS_LINENO(yyless_macro_arg);\ *yy_cp = (yy_hold_char); \ YY_RESTORE_YY_MORE_OFFSET \ @@ -358,8 +358,8 @@ static void yynoreturn yy_fatal_error (yyconst char* msg ); *yy_cp = '\0'; \ (yy_c_buf_p) = yy_cp; -#define YY_NUM_RULES 37 -#define YY_END_OF_BUFFER 38 +#define YY_NUM_RULES 38 +#define YY_END_OF_BUFFER 39 /* This struct is not used in this scanner, but its presence is necessary. */ struct yy_trans_info @@ -367,24 +367,25 @@ struct yy_trans_info flex_int32_t yy_verify; flex_int32_t yy_nxt; }; -static yyconst flex_int16_t yy_accept[145] = +static yyconst flex_int16_t yy_accept[160] = { 0, - 0, 0, 38, 36, 1, 3, 36, 36, 36, 31, - 31, 29, 32, 36, 32, 32, 32, 36, 36, 36, - 36, 36, 36, 36, 36, 36, 36, 36, 1, 3, - 36, 0, 36, 36, 0, 2, 31, 32, 36, 36, - 36, 36, 32, 36, 36, 36, 36, 36, 36, 36, - 24, 36, 36, 36, 36, 7, 36, 36, 36, 36, - 36, 36, 35, 35, 36, 0, 30, 36, 36, 16, - 36, 36, 23, 28, 36, 36, 13, 36, 36, 22, - 36, 36, 8, 10, 12, 36, 20, 36, 21, 36, - 0, 33, 4, 36, 36, 36, 36, 36, 36, 36, + 0, 0, 39, 37, 1, 3, 37, 37, 37, 32, + 32, 30, 33, 37, 33, 33, 33, 37, 37, 37, + 37, 37, 37, 37, 37, 37, 37, 37, 1, 3, + 37, 0, 37, 37, 0, 2, 32, 33, 37, 37, + 37, 37, 33, 37, 37, 37, 37, 37, 37, 37, + 24, 37, 37, 37, 37, 7, 37, 37, 37, 37, + 37, 37, 37, 36, 36, 37, 0, 31, 37, 37, + 16, 37, 37, 23, 28, 37, 37, 13, 37, 37, + 22, 37, 37, 8, 10, 12, 37, 37, 20, 37, + 21, 37, 0, 34, 4, 37, 37, 37, 37, 37, - 36, 19, 36, 36, 34, 34, 36, 36, 36, 36, - 36, 36, 36, 14, 36, 36, 36, 5, 17, 36, - 9, 36, 11, 36, 36, 36, 18, 26, 36, 36, - 36, 36, 36, 6, 36, 36, 36, 36, 36, 25, - 36, 15, 27, 0 + 37, 37, 37, 19, 37, 37, 37, 35, 35, 37, + 37, 37, 37, 37, 37, 37, 14, 37, 37, 37, + 37, 5, 17, 37, 9, 37, 11, 37, 37, 37, + 37, 18, 26, 37, 37, 37, 37, 37, 37, 6, + 37, 37, 37, 37, 37, 37, 37, 25, 37, 37, + 15, 37, 27, 37, 37, 37, 37, 29, 0 } ; static yyconst YY_CHAR yy_ec[256] = @@ -427,110 +428,114 @@ static yyconst YY_CHAR yy_meta[39] = 1, 1, 1, 1, 1, 1, 1, 1 } ; -static yyconst flex_uint16_t yy_base[152] = +static yyconst flex_uint16_t yy_base[167] = { 0, - 0, 0, 212, 0, 209, 213, 207, 37, 41, 38, - 172, 0, 44, 194, 54, 78, 60, 186, 181, 45, - 188, 177, 42, 47, 182, 41, 169, 0, 199, 213, - 77, 195, 87, 91, 196, 213, 0, 88, 104, 183, - 172, 161, 93, 168, 163, 173, 164, 171, 171, 165, - 171, 156, 156, 160, 162, 0, 158, 152, 158, 155, - 161, 160, 0, 213, 101, 172, 0, 165, 145, 158, - 148, 155, 0, 0, 150, 150, 0, 148, 138, 0, - 142, 137, 0, 0, 0, 140, 0, 131, 0, 158, - 157, 0, 0, 142, 141, 134, 126, 136, 124, 130, + 0, 0, 227, 0, 224, 228, 222, 37, 41, 38, + 187, 0, 44, 209, 54, 78, 60, 201, 196, 45, + 203, 192, 42, 47, 197, 62, 184, 0, 214, 228, + 77, 210, 88, 69, 211, 228, 0, 87, 104, 198, + 187, 176, 93, 183, 178, 188, 179, 186, 186, 180, + 186, 171, 171, 175, 177, 0, 173, 167, 173, 177, + 169, 175, 174, 0, 228, 101, 186, 0, 179, 159, + 172, 162, 169, 0, 0, 164, 164, 0, 162, 152, + 0, 156, 151, 0, 0, 0, 154, 153, 0, 144, + 0, 171, 170, 0, 0, 155, 154, 147, 139, 149, - 135, 0, 120, 114, 0, 213, 125, 129, 121, 123, - 119, 121, 126, 0, 110, 110, 107, 0, 0, 109, - 0, 93, 104, 98, 84, 84, 0, 0, 89, 77, - 87, 71, 66, 0, 64, 62, 50, 47, 33, 0, - 28, 0, 0, 213, 40, 129, 131, 133, 135, 137, - 139 + 137, 143, 148, 0, 133, 136, 126, 0, 228, 137, + 141, 133, 135, 131, 133, 138, 0, 122, 122, 121, + 118, 0, 0, 133, 0, 117, 134, 128, 132, 113, + 113, 0, 0, 120, 112, 110, 121, 94, 95, 0, + 94, 92, 97, 86, 85, 84, 76, 0, 71, 78, + 0, 67, 0, 61, 55, 32, 29, 0, 228, 40, + 129, 131, 133, 135, 137, 139 } ; -static yyconst flex_int16_t yy_def[152] = +static yyconst flex_int16_t yy_def[167] = { 0, - 144, 1, 144, 145, 144, 144, 145, 146, 147, 145, - 10, 145, 10, 145, 10, 10, 10, 145, 145, 145, - 145, 145, 145, 145, 145, 145, 145, 145, 144, 144, - 146, 148, 149, 147, 150, 144, 10, 10, 10, 145, - 145, 145, 10, 145, 145, 145, 145, 145, 145, 145, - 145, 145, 145, 145, 145, 145, 145, 145, 145, 145, - 145, 145, 145, 144, 149, 151, 39, 145, 145, 145, - 145, 145, 145, 145, 145, 145, 145, 145, 145, 145, - 145, 145, 145, 145, 145, 145, 145, 145, 145, 145, - 144, 145, 145, 145, 145, 145, 145, 145, 145, 145, + 159, 1, 159, 160, 159, 159, 160, 161, 162, 160, + 10, 160, 10, 160, 10, 10, 10, 160, 160, 160, + 160, 160, 160, 160, 160, 160, 160, 160, 159, 159, + 161, 163, 164, 162, 165, 159, 10, 10, 10, 160, + 160, 160, 10, 160, 160, 160, 160, 160, 160, 160, + 160, 160, 160, 160, 160, 160, 160, 160, 160, 160, + 160, 160, 160, 160, 159, 164, 166, 39, 160, 160, + 160, 160, 160, 160, 160, 160, 160, 160, 160, 160, + 160, 160, 160, 160, 160, 160, 160, 160, 160, 160, + 160, 160, 159, 160, 160, 160, 160, 160, 160, 160, - 145, 145, 145, 145, 145, 144, 145, 145, 145, 145, - 145, 145, 145, 145, 145, 145, 145, 145, 145, 145, - 145, 145, 145, 145, 145, 145, 145, 145, 145, 145, - 145, 145, 145, 145, 145, 145, 145, 145, 145, 145, - 145, 145, 145, 0, 144, 144, 144, 144, 144, 144, - 144 + 160, 160, 160, 160, 160, 160, 160, 160, 159, 160, + 160, 160, 160, 160, 160, 160, 160, 160, 160, 160, + 160, 160, 160, 160, 160, 160, 160, 160, 160, 160, + 160, 160, 160, 160, 160, 160, 160, 160, 160, 160, + 160, 160, 160, 160, 160, 160, 160, 160, 160, 160, + 160, 160, 160, 160, 160, 160, 160, 160, 0, 159, + 159, 159, 159, 159, 159, 159 } ; -static yyconst flex_uint16_t yy_nxt[252] = +static yyconst flex_uint16_t yy_nxt[267] = { 0, 4, 5, 6, 7, 8, 9, 10, 11, 10, 12, 13, 13, 14, 4, 4, 4, 13, 13, 15, 16, 17, 13, 18, 19, 20, 21, 22, 4, 23, 24, 4, 25, 26, 4, 27, 4, 4, 4, 32, 32, - 28, 33, 35, 36, 37, 37, 37, 143, 38, 38, + 28, 33, 35, 36, 37, 37, 37, 158, 38, 38, 38, 38, 38, 49, 38, 38, 38, 38, 38, 38, - 38, 38, 38, 55, 142, 57, 38, 38, 38, 56, - 60, 141, 50, 51, 58, 61, 52, 41, 32, 32, - 140, 63, 139, 42, 38, 38, 38, 46, 66, 66, - 138, 28, 35, 36, 38, 38, 38, 137, 43, 38, + 38, 38, 38, 55, 157, 57, 38, 38, 38, 56, + 35, 36, 50, 51, 58, 156, 52, 41, 32, 32, + 155, 64, 154, 42, 38, 38, 38, 46, 60, 67, + 67, 61, 28, 38, 38, 38, 62, 153, 43, 38, - 38, 38, 66, 66, 136, 90, 44, 135, 134, 45, - 67, 67, 67, 133, 67, 67, 132, 131, 130, 129, - 67, 67, 67, 67, 67, 67, 128, 127, 71, 31, - 31, 34, 34, 32, 32, 65, 65, 35, 35, 66, - 66, 126, 125, 124, 123, 122, 121, 120, 119, 118, - 117, 116, 115, 114, 113, 112, 111, 110, 109, 108, - 107, 106, 105, 104, 103, 102, 101, 100, 99, 98, - 97, 96, 95, 94, 93, 92, 91, 89, 88, 87, - 86, 85, 84, 83, 82, 81, 80, 79, 78, 77, - 76, 75, 74, 73, 72, 70, 69, 68, 36, 64, + 38, 38, 67, 67, 152, 92, 44, 151, 150, 45, + 68, 68, 68, 149, 68, 68, 148, 147, 146, 145, + 68, 68, 68, 68, 68, 68, 144, 143, 72, 31, + 31, 34, 34, 32, 32, 66, 66, 35, 35, 67, + 67, 142, 141, 140, 139, 138, 137, 136, 135, 134, + 133, 132, 131, 130, 129, 128, 127, 126, 125, 124, + 123, 122, 121, 120, 119, 118, 117, 116, 115, 114, + 113, 112, 111, 110, 109, 108, 107, 106, 105, 104, + 103, 102, 101, 100, 99, 98, 97, 96, 95, 94, + 93, 91, 90, 89, 88, 87, 86, 85, 84, 83, - 29, 62, 59, 54, 53, 48, 47, 40, 39, 30, - 29, 144, 3, 144, 144, 144, 144, 144, 144, 144, - 144, 144, 144, 144, 144, 144, 144, 144, 144, 144, - 144, 144, 144, 144, 144, 144, 144, 144, 144, 144, - 144, 144, 144, 144, 144, 144, 144, 144, 144, 144, - 144 + 82, 81, 80, 79, 78, 77, 76, 75, 74, 73, + 71, 70, 69, 36, 65, 29, 63, 59, 54, 53, + 48, 47, 40, 39, 30, 29, 159, 3, 159, 159, + 159, 159, 159, 159, 159, 159, 159, 159, 159, 159, + 159, 159, 159, 159, 159, 159, 159, 159, 159, 159, + 159, 159, 159, 159, 159, 159, 159, 159, 159, 159, + 159, 159, 159, 159, 159, 159 } ; -static yyconst flex_int16_t yy_chk[252] = +static yyconst flex_int16_t yy_chk[267] = { 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 8, 8, - 145, 8, 9, 9, 10, 10, 10, 141, 10, 10, + 160, 8, 9, 9, 10, 10, 10, 157, 10, 10, 13, 13, 13, 20, 10, 10, 10, 10, 10, 10, - 15, 15, 15, 23, 139, 24, 17, 17, 17, 23, - 26, 138, 20, 20, 24, 26, 20, 15, 31, 31, - 137, 31, 136, 15, 16, 16, 16, 17, 33, 33, - 135, 33, 34, 34, 38, 38, 38, 133, 16, 43, + 15, 15, 15, 23, 156, 24, 17, 17, 17, 23, + 34, 34, 20, 20, 24, 155, 20, 15, 31, 31, + 154, 31, 152, 15, 16, 16, 16, 17, 26, 33, + 33, 26, 33, 38, 38, 38, 26, 150, 16, 43, - 43, 43, 65, 65, 132, 65, 16, 131, 130, 16, - 39, 39, 39, 129, 39, 39, 126, 125, 124, 123, - 39, 39, 39, 39, 39, 39, 122, 120, 43, 146, - 146, 147, 147, 148, 148, 149, 149, 150, 150, 151, - 151, 117, 116, 115, 113, 112, 111, 110, 109, 108, - 107, 104, 103, 101, 100, 99, 98, 97, 96, 95, - 94, 91, 90, 88, 86, 82, 81, 79, 78, 76, - 75, 72, 71, 70, 69, 68, 66, 62, 61, 60, - 59, 58, 57, 55, 54, 53, 52, 51, 50, 49, - 48, 47, 46, 45, 44, 42, 41, 40, 35, 32, + 43, 43, 66, 66, 149, 66, 16, 147, 146, 16, + 39, 39, 39, 145, 39, 39, 144, 143, 142, 141, + 39, 39, 39, 39, 39, 39, 139, 138, 43, 161, + 161, 162, 162, 163, 163, 164, 164, 165, 165, 166, + 166, 137, 136, 135, 134, 131, 130, 129, 128, 127, + 126, 124, 121, 120, 119, 118, 116, 115, 114, 113, + 112, 111, 110, 107, 106, 105, 103, 102, 101, 100, + 99, 98, 97, 96, 93, 92, 90, 88, 87, 83, + 82, 80, 79, 77, 76, 73, 72, 71, 70, 69, + 67, 63, 62, 61, 60, 59, 58, 57, 55, 54, - 29, 27, 25, 22, 21, 19, 18, 14, 11, 7, - 5, 3, 144, 144, 144, 144, 144, 144, 144, 144, - 144, 144, 144, 144, 144, 144, 144, 144, 144, 144, - 144, 144, 144, 144, 144, 144, 144, 144, 144, 144, - 144, 144, 144, 144, 144, 144, 144, 144, 144, 144, - 144 + 53, 52, 51, 50, 49, 48, 47, 46, 45, 44, + 42, 41, 40, 35, 32, 29, 27, 25, 22, 21, + 19, 18, 14, 11, 7, 5, 3, 159, 159, 159, + 159, 159, 159, 159, 159, 159, 159, 159, 159, 159, + 159, 159, 159, 159, 159, 159, 159, 159, 159, 159, + 159, 159, 159, 159, 159, 159, 159, 159, 159, 159, + 159, 159, 159, 159, 159, 159 } ; static yy_state_type yy_last_accepting_state; @@ -674,7 +679,7 @@ static int input (void ); if ( YY_CURRENT_BUFFER_LVALUE->yy_is_interactive ) \ { \ int c = '*'; \ - size_t n; \ + int n; \ for ( n = 0; n < max_size && \ (c = getc( yyin )) != EOF && c != '\n'; ++n ) \ buf[n] = (char) c; \ @@ -687,7 +692,7 @@ static int input (void ); else \ { \ errno=0; \ - while ( (result = (int) fread(buf, 1, max_size, yyin))==0 && ferror(yyin)) \ + while ( (result = (int) fread(buf, 1, (yy_size_t) max_size, yyin)) == 0 && ferror(yyin)) \ { \ if( errno != EINTR) \ { \ @@ -809,13 +814,13 @@ yy_match: while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state ) { yy_current_state = (int) yy_def[yy_current_state]; - if ( yy_current_state >= 145 ) + if ( yy_current_state >= 160 ) yy_c = yy_meta[(unsigned int) yy_c]; } yy_current_state = yy_nxt[yy_base[yy_current_state] + (flex_int16_t) yy_c]; ++yy_cp; } - while ( yy_base[yy_current_state] != 213 ); + while ( yy_base[yy_current_state] != 228 ); yy_find_action: yy_act = yy_accept[yy_current_state]; @@ -955,11 +960,11 @@ YY_RULE_SETUP YY_BREAK case 29: YY_RULE_SETUP -{return(EQUALS);} +{return(SLOT_DESC);} YY_BREAK case 30: YY_RULE_SETUP -{yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(NUMBER);} +{return(EQUALS);} YY_BREAK case 31: YY_RULE_SETUP @@ -971,12 +976,11 @@ YY_RULE_SETUP YY_BREAK case 33: YY_RULE_SETUP -{yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(PCIINT);} +{yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(NUMBER);} YY_BREAK case 34: -/* rule 34 can match eol */ YY_RULE_SETUP -{yylval.string = malloc(yyleng-1); strncpy(yylval.string, yytext+1, yyleng-2); yylval.string[yyleng-2]='\0'; return(STRING);} +{yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(PCIINT);} YY_BREAK case 35: /* rule 35 can match eol */ @@ -984,10 +988,15 @@ YY_RULE_SETUP {yylval.string = malloc(yyleng-1); strncpy(yylval.string, yytext+1, yyleng-2); yylval.string[yyleng-2]='\0'; return(STRING);} YY_BREAK case 36: +/* rule 36 can match eol */ +YY_RULE_SETUP +{yylval.string = malloc(yyleng-1); strncpy(yylval.string, yytext+1, yyleng-2); yylval.string[yyleng-2]='\0'; return(STRING);} + YY_BREAK +case 37: YY_RULE_SETUP {yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(STRING);} YY_BREAK -case 37: +case 38: YY_RULE_SETUP ECHO; YY_BREAK @@ -1135,7 +1144,7 @@ static int yy_get_next_buffer (void) { char *dest = YY_CURRENT_BUFFER_LVALUE->yy_ch_buf; char *source = (yytext_ptr); - int number_to_move, i; + yy_size_t number_to_move, i; int ret_val; if ( (yy_c_buf_p) > &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars) + 1] ) @@ -1164,7 +1173,7 @@ static int yy_get_next_buffer (void) /* Try to read more data. */ /* First move last chars to start of buffer. */ - number_to_move = (int) ((yy_c_buf_p) - (yytext_ptr) - 1); + number_to_move = (yy_size_t) ((yy_c_buf_p) - (yytext_ptr)) - 1; for ( i = 0; i < number_to_move; ++i ) *(dest++) = *(source++); @@ -1200,7 +1209,7 @@ static int yy_get_next_buffer (void) b->yy_ch_buf = (char *) /* Include room in for 2 EOB chars. */ - yyrealloc((void *) b->yy_ch_buf,b->yy_buf_size + 2 ); + yyrealloc((void *) b->yy_ch_buf,(yy_size_t) (b->yy_buf_size + 2) ); } else /* Can't grow it, we don't own it. */ @@ -1246,10 +1255,10 @@ static int yy_get_next_buffer (void) else ret_val = EOB_ACT_CONTINUE_SCAN; - if (((yy_n_chars) + number_to_move) > YY_CURRENT_BUFFER_LVALUE->yy_buf_size) { + if ((int) ((yy_n_chars) + number_to_move) > YY_CURRENT_BUFFER_LVALUE->yy_buf_size) { /* Extend the array by 50%, plus the number we really need. */ int new_size = (yy_n_chars) + number_to_move + ((yy_n_chars) >> 1); - YY_CURRENT_BUFFER_LVALUE->yy_ch_buf = (char *) yyrealloc((void *) YY_CURRENT_BUFFER_LVALUE->yy_ch_buf,new_size ); + YY_CURRENT_BUFFER_LVALUE->yy_ch_buf = (char *) yyrealloc((void *) YY_CURRENT_BUFFER_LVALUE->yy_ch_buf,(yy_size_t) new_size ); if ( ! YY_CURRENT_BUFFER_LVALUE->yy_ch_buf ) YY_FATAL_ERROR( "out of dynamic memory in yy_get_next_buffer()" ); } @@ -1283,7 +1292,7 @@ static int yy_get_next_buffer (void) while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state ) { yy_current_state = (int) yy_def[yy_current_state]; - if ( yy_current_state >= 145 ) + if ( yy_current_state >= 160 ) yy_c = yy_meta[(unsigned int) yy_c]; } yy_current_state = yy_nxt[yy_base[yy_current_state] + (flex_int16_t) yy_c]; @@ -1311,11 +1320,11 @@ static int yy_get_next_buffer (void) while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state ) { yy_current_state = (int) yy_def[yy_current_state]; - if ( yy_current_state >= 145 ) + if ( yy_current_state >= 160 ) yy_c = yy_meta[(unsigned int) yy_c]; } yy_current_state = yy_nxt[yy_base[yy_current_state] + (flex_int16_t) yy_c]; - yy_is_jam = (yy_current_state == 144); + yy_is_jam = (yy_current_state == 159); return yy_is_jam ? 0 : yy_current_state; } @@ -1510,12 +1519,12 @@ static void yy_load_buffer_state (void) if ( ! b ) YY_FATAL_ERROR( "out of dynamic memory in yy_create_buffer()" ); - b->yy_buf_size = (yy_size_t)size; + b->yy_buf_size = size; /* yy_ch_buf has to be 2 characters longer than the size given because * we need to put in 2 end-of-buffer characters. */ - b->yy_ch_buf = (char *) yyalloc(b->yy_buf_size + 2 ); + b->yy_ch_buf = (char *) yyalloc((yy_size_t) (b->yy_buf_size + 2) ); if ( ! b->yy_ch_buf ) YY_FATAL_ERROR( "out of dynamic memory in yy_create_buffer()" ); @@ -1718,7 +1727,7 @@ YY_BUFFER_STATE yy_scan_buffer (char * base, yy_size_t size ) if ( ! b ) YY_FATAL_ERROR( "out of dynamic memory in yy_scan_buffer()" ); - b->yy_buf_size = size - 2; /* "- 2" to take care of EOB's */ + b->yy_buf_size = (int) (size - 2); /* "- 2" to take care of EOB's */ b->yy_buf_pos = b->yy_ch_buf = base; b->yy_is_our_buffer = 0; b->yy_input_file = NULL; @@ -1801,7 +1810,7 @@ static void yynoreturn yy_fatal_error (yyconst char* msg ) do \ { \ /* Undo effects of setting up yytext. */ \ - int yyless_macro_arg = (n); \ + yy_size_t yyless_macro_arg = (n); \ YY_LESS_LINENO(yyless_macro_arg);\ yytext[yyleng] = (yy_hold_char); \ (yy_c_buf_p) = yytext + yyless_macro_arg; \ diff --git a/util/sconfig/main.c b/util/sconfig/main.c index 5382f470fd..c3aa17f1a0 100644 --- a/util/sconfig/main.c +++ b/util/sconfig/main.c @@ -622,6 +622,22 @@ void add_register(struct chip_instance *chip_instance, char *name, char *val) } } +void add_slot_desc(struct bus *bus, char *type, char *length, char *designation, + char *data_width) +{ + struct device *dev = bus->dev; + + if (dev->bustype != PCI && dev->bustype != DOMAIN) { + printf("ERROR: 'slot_type' only allowed for PCI devices\n"); + exit(1); + } + + dev->smbios_slot_type = type; + dev->smbios_slot_length = length; + dev->smbios_slot_data_width = data_width; + dev->smbios_slot_designation = designation; +} + void add_pci_subsystem_ids(struct bus *bus, int vendor, int device, int inherit) { @@ -831,7 +847,30 @@ static void pass1(FILE *fil, struct device *ptr, struct device *next) fprintf(fil, "\t.chip_info = &%s_info_%d,\n", chip_ins->chip->name_underscore, chip_ins->id); if (next) - fprintf(fil, "\t.next=&%s\n", next->name); + fprintf(fil, "\t.next=&%s,\n", next->name); + if (ptr->smbios_slot_type || ptr->smbios_slot_data_width || + ptr->smbios_slot_designation || ptr->smbios_slot_length) { + fprintf(fil, "#if !DEVTREE_EARLY\n"); + fprintf(fil, "#if CONFIG(GENERATE_SMBIOS_TABLES)\n"); + } + /* SMBIOS types start at 1, if zero it hasn't been set */ + if (ptr->smbios_slot_type) + fprintf(fil, "\t.smbios_slot_type = %s,\n", + ptr->smbios_slot_type); + if (ptr->smbios_slot_data_width) + fprintf(fil, "\t.smbios_slot_data_width = %s,\n", + ptr->smbios_slot_data_width); + if (ptr->smbios_slot_designation) + fprintf(fil, "\t.smbios_slot_designation = \"%s\",\n", + ptr->smbios_slot_designation); + if (ptr->smbios_slot_length) + fprintf(fil, "\t.smbios_slot_length = %s,\n", + ptr->smbios_slot_length); + if (ptr->smbios_slot_type || ptr->smbios_slot_data_width || + ptr->smbios_slot_designation || ptr->smbios_slot_length) { + fprintf(fil, "#endif\n"); + fprintf(fil, "#endif\n"); + } fprintf(fil, "};\n"); emit_resources(fil, ptr); diff --git a/util/sconfig/sconfig.h b/util/sconfig/sconfig.h index 389d697a33..e6363dea83 100644 --- a/util/sconfig/sconfig.h +++ b/util/sconfig/sconfig.h @@ -141,6 +141,18 @@ struct device { struct bus *bus; /* Pointer to last bus under this device. */ struct bus *last_bus; + + /* SMBIOS slot type */ + char *smbios_slot_type; + + /* SMBIOS slot data width */ + char *smbios_slot_data_width; + + /* SMBIOS slot description for reference designation */ + char *smbios_slot_designation; + + /* SMBIOS slot length */ + char *smbios_slot_length; }; extern struct bus *root_parent; @@ -158,6 +170,9 @@ void add_pci_subsystem_ids(struct bus *bus, int vendor, int device, void add_ioapic_info(struct bus *bus, int apicid, const char *_srcpin, int irqpin); +void add_slot_desc(struct bus *bus, char *type, char *length, char *designation, + char *data_width); + void yyrestart(FILE *input_file); /* Add chip data to tail of queue. */ diff --git a/util/sconfig/sconfig.l b/util/sconfig/sconfig.l index b21cca54b1..87de6e2763 100755 --- a/util/sconfig/sconfig.l +++ b/util/sconfig/sconfig.l @@ -21,40 +21,41 @@ int linenum = 0; %} %option nodebug %% -[ \t]+ {} -#.*\n {linenum++;} -\r?\n {linenum++;} -chip {return(CHIP);} -device {return(DEVICE);} -register {return(REGISTER);} -on {yylval.number=1; return(BOOL);} -off {yylval.number=0; return(BOOL);} -hidden {yylval.number=3; return(HIDDEN);} -pci {yylval.number=PCI; return(BUS);} -ioapic {yylval.number=IOAPIC; return(BUS);} -pnp {yylval.number=PNP; return(BUS);} -i2c {yylval.number=I2C; return(BUS);} -lapic {yylval.number=APIC; return(BUS);} -cpu_cluster {yylval.number=CPU_CLUSTER; return(BUS);} -cpu {yylval.number=CPU; return(BUS);} -domain {yylval.number=DOMAIN; return(BUS);} -generic {yylval.number=GENERIC; return(BUS);} -mmio {yylval.number=MMIO; return(BUS);} -spi {yylval.number=SPI; return(BUS);} -usb {yylval.number=USB; return(BUS);} -irq {yylval.number=IRQ; return(RESOURCE);} -drq {yylval.number=DRQ; return(RESOURCE);} -io {yylval.number=IO; return(RESOURCE);} -ioapic_irq {return(IOAPIC_IRQ);} -inherit {return(INHERIT);} -subsystemid {return(SUBSYSTEMID);} -end {return(END);} -= {return(EQUALS);} -0x[0-9a-fA-F.]+ {yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(NUMBER);} -[0-9.]+ {yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(NUMBER);} -[0-9a-fA-F.]+ {yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(NUMBER);} -INT[A-D] {yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(PCIINT);} -\"\"[^\"]+\"\" {yylval.string = malloc(yyleng-1); strncpy(yylval.string, yytext+1, yyleng-2); yylval.string[yyleng-2]='\0'; return(STRING);} -\"[^\"]+\" {yylval.string = malloc(yyleng-1); strncpy(yylval.string, yytext+1, yyleng-2); yylval.string[yyleng-2]='\0'; return(STRING);} -[^ \n\t]+ {yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(STRING);} +[ \t]+ {} +#.*\n {linenum++;} +\r?\n {linenum++;} +chip {return(CHIP);} +device {return(DEVICE);} +register {return(REGISTER);} +on {yylval.number=1; return(BOOL);} +off {yylval.number=0; return(BOOL);} +hidden {yylval.number=3; return(HIDDEN);} +pci {yylval.number=PCI; return(BUS);} +ioapic {yylval.number=IOAPIC; return(BUS);} +pnp {yylval.number=PNP; return(BUS);} +i2c {yylval.number=I2C; return(BUS);} +lapic {yylval.number=APIC; return(BUS);} +cpu_cluster {yylval.number=CPU_CLUSTER; return(BUS);} +cpu {yylval.number=CPU; return(BUS);} +domain {yylval.number=DOMAIN; return(BUS);} +generic {yylval.number=GENERIC; return(BUS);} +mmio {yylval.number=MMIO; return(BUS);} +spi {yylval.number=SPI; return(BUS);} +usb {yylval.number=USB; return(BUS);} +irq {yylval.number=IRQ; return(RESOURCE);} +drq {yylval.number=DRQ; return(RESOURCE);} +io {yylval.number=IO; return(RESOURCE);} +ioapic_irq {return(IOAPIC_IRQ);} +inherit {return(INHERIT);} +subsystemid {return(SUBSYSTEMID);} +end {return(END);} +smbios_slot_desc {return(SLOT_DESC);} += {return(EQUALS);} +0x[0-9a-fA-F.]+ {yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(NUMBER);} +[0-9.]+ {yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(NUMBER);} +[0-9a-fA-F.]+ {yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(NUMBER);} +INT[A-D] {yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(PCIINT);} +\"\"[^\"]+\"\" {yylval.string = malloc(yyleng-1); strncpy(yylval.string, yytext+1, yyleng-2); yylval.string[yyleng-2]='\0'; return(STRING);} +\"[^\"]+\" {yylval.string = malloc(yyleng-1); strncpy(yylval.string, yytext+1, yyleng-2); yylval.string[yyleng-2]='\0'; return(STRING);} +[^ \n\t]+ {yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(STRING);} %% diff --git a/util/sconfig/sconfig.tab.c_shipped b/util/sconfig/sconfig.tab.c_shipped index d59a1b6883..8e1e57de54 100644 --- a/util/sconfig/sconfig.tab.c_shipped +++ b/util/sconfig/sconfig.tab.c_shipped @@ -1,8 +1,8 @@ -/* A Bison parser, made by GNU Bison 3.0.4. */ +/* A Bison parser, made by GNU Bison 3.0.5. */ /* Bison implementation for Yacc-like parsers in C - Copyright (C) 1984, 1989-1990, 2000-2015 Free Software Foundation, Inc. + Copyright (C) 1984, 1989-1990, 2000-2015, 2018 Free Software Foundation, Inc. This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by @@ -44,7 +44,7 @@ #define YYBISON 1 /* Bison version. */ -#define YYBISON_VERSION "3.0.4" +#define YYBISON_VERSION "3.0.5" /* Skeleton name. */ #define YYSKELETON_NAME "yacc.c" @@ -144,17 +144,18 @@ extern int yydebug; DOMAIN = 275, IRQ = 276, DRQ = 277, - IO = 278, - NUMBER = 279, - SUBSYSTEMID = 280, - INHERIT = 281, - IOAPIC_IRQ = 282, - IOAPIC = 283, - PCIINT = 284, - GENERIC = 285, - SPI = 286, - USB = 287, - MMIO = 288 + SLOT_DESC = 278, + IO = 279, + NUMBER = 280, + SUBSYSTEMID = 281, + INHERIT = 282, + IOAPIC_IRQ = 283, + IOAPIC = 284, + PCIINT = 285, + GENERIC = 286, + SPI = 287, + USB = 288, + MMIO = 289 }; #endif @@ -429,21 +430,21 @@ union yyalloc /* YYFINAL -- State number of the termination state. */ #define YYFINAL 3 /* YYLAST -- Last index in YYTABLE. */ -#define YYLAST 40 +#define YYLAST 43 /* YYNTOKENS -- Number of terminals. */ -#define YYNTOKENS 34 +#define YYNTOKENS 35 /* YYNNTS -- Number of nonterminals. */ -#define YYNNTS 14 +#define YYNNTS 15 /* YYNRULES -- Number of rules. */ -#define YYNRULES 24 +#define YYNRULES 28 /* YYNSTATES -- Number of states. */ -#define YYNSTATES 43 +#define YYNSTATES 49 /* YYTRANSLATE[YYX] -- Symbol number corresponding to YYX as returned by yylex, with out-of-bounds checking. */ #define YYUNDEFTOK 2 -#define YYMAXUTOK 288 +#define YYMAXUTOK 289 #define YYTRANSLATE(YYX) \ ((unsigned int) (YYX) <= YYMAXUTOK ? yytranslate[YYX] : YYUNDEFTOK) @@ -480,7 +481,7 @@ static const yytype_uint8 yytranslate[] = 2, 2, 2, 2, 2, 2, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, - 25, 26, 27, 28, 29, 30, 31, 32, 33 + 25, 26, 27, 28, 29, 30, 31, 32, 33, 34 }; #if YYDEBUG @@ -488,8 +489,8 @@ static const yytype_uint8 yytranslate[] = static const yytype_uint8 yyrline[] = { 0, 36, 36, 36, 38, 38, 38, 38, 40, 40, - 40, 40, 40, 40, 42, 42, 51, 51, 59, 59, - 61, 64, 67, 70, 73 + 40, 40, 40, 40, 40, 42, 42, 51, 51, 59, + 59, 61, 64, 67, 70, 73, 76, 79, 82 }; #endif @@ -500,11 +501,12 @@ static const char *const yytname[] = { "$end", "error", "$undefined", "CHIP", "DEVICE", "REGISTER", "BOOL", "HIDDEN", "BUS", "RESOURCE", "END", "EQUALS", "HEX", "STRING", "PCI", - "PNP", "I2C", "APIC", "CPU_CLUSTER", "CPU", "DOMAIN", "IRQ", "DRQ", "IO", - "NUMBER", "SUBSYSTEMID", "INHERIT", "IOAPIC_IRQ", "IOAPIC", "PCIINT", - "GENERIC", "SPI", "USB", "MMIO", "$accept", "devtree", "$@1", - "chipchildren", "devicechildren", "chip", "@2", "device", "@3", "status", - "resource", "registers", "subsystemid", "ioapic_irq", YY_NULLPTR + "PNP", "I2C", "APIC", "CPU_CLUSTER", "CPU", "DOMAIN", "IRQ", "DRQ", + "SLOT_DESC", "IO", "NUMBER", "SUBSYSTEMID", "INHERIT", "IOAPIC_IRQ", + "IOAPIC", "PCIINT", "GENERIC", "SPI", "USB", "MMIO", "$accept", + "devtree", "$@1", "chipchildren", "devicechildren", "chip", "@2", + "device", "@3", "status", "resource", "registers", "subsystemid", + "ioapic_irq", "smbios_slot_desc", YY_NULLPTR }; #endif @@ -516,14 +518,14 @@ static const yytype_uint16 yytoknum[] = 0, 256, 257, 258, 259, 260, 261, 262, 263, 264, 265, 266, 267, 268, 269, 270, 271, 272, 273, 274, 275, 276, 277, 278, 279, 280, 281, 282, 283, 284, - 285, 286, 287, 288 + 285, 286, 287, 288, 289 }; # endif -#define YYPACT_NINF -10 +#define YYPACT_NINF -12 #define yypact_value_is_default(Yystate) \ - (!!((Yystate) == (-10))) + (!!((Yystate) == (-12))) #define YYTABLE_NINF -1 @@ -534,11 +536,11 @@ static const yytype_uint16 yytoknum[] = STATE-NUM. */ static const yytype_int8 yypact[] = { - -10, 11, 9, -10, 1, -10, -10, -10, 0, 5, - 3, -10, -10, -10, -10, -9, 6, 2, 7, -10, - -10, -10, -10, -10, -3, -5, -10, -1, 4, -10, - -10, -10, -10, -10, 10, 8, -4, 12, 13, 14, - -10, -10, -10 + -12, 11, 9, -12, 1, -12, -12, -12, 0, 5, + 3, -12, -12, -12, -12, -10, 6, 2, 8, -12, + -12, -12, -12, -12, -3, -1, -12, 13, 4, 7, + -12, -12, -12, -12, -12, -12, 16, 15, 10, -11, + 12, 17, -5, 14, -12, 18, -12, -12, -12 }; /* YYDEFACT[STATE-NUM] -- Default reduction number in state STATE-NUM. @@ -546,25 +548,25 @@ static const yytype_int8 yypact[] = means the default is an error. */ static const yytype_uint8 yydefact[] = { - 2, 0, 0, 1, 0, 3, 14, 7, 0, 0, - 0, 15, 5, 4, 6, 0, 0, 0, 0, 18, - 19, 16, 21, 13, 0, 0, 17, 0, 0, 9, - 8, 10, 11, 12, 0, 0, 0, 0, 22, 0, - 20, 23, 24 + 2, 0, 0, 1, 0, 3, 15, 7, 0, 0, + 0, 16, 5, 4, 6, 0, 0, 0, 0, 19, + 20, 17, 22, 14, 0, 0, 18, 0, 0, 0, + 9, 8, 10, 11, 12, 13, 0, 0, 0, 0, + 0, 28, 23, 0, 21, 27, 24, 25, 26 }; /* YYPGOTO[NTERM-NUM]. */ static const yytype_int8 yypgoto[] = { - -10, -10, -10, -10, -10, -6, -10, 16, -10, -10, - -10, -10, -10, -10 + -12, -12, -12, -12, -12, -6, -12, 19, -12, -12, + -12, -12, -12, -12, -12 }; /* YYDEFGOTO[NTERM-NUM]. */ static const yytype_int8 yydefgoto[] = { -1, 1, 2, 8, 24, 5, 7, 13, 23, 21, - 31, 14, 32, 33 + 32, 14, 33, 34, 35 }; /* YYTABLE[YYPACT[STATE-NUM]] -- What to do in state STATE-NUM. If @@ -573,46 +575,46 @@ static const yytype_int8 yydefgoto[] = static const yytype_uint8 yytable[] = { 4, 9, 12, 4, 9, 10, 25, 26, 19, 20, - 11, 3, 4, 15, 6, 17, 16, 18, 29, 34, - 22, 37, 27, 35, 28, 39, 0, 0, 36, 0, - 0, 0, 38, 0, 0, 0, 40, 0, 42, 41, - 30 + 11, 3, 4, 15, 6, 17, 16, 18, 30, 43, + 27, 22, 46, 28, 36, 29, 37, 40, 41, 38, + 45, 48, 39, 0, 0, 42, 0, 44, 0, 47, + 0, 0, 0, 31 }; static const yytype_int8 yycheck[] = { 3, 4, 8, 3, 4, 5, 9, 10, 6, 7, - 10, 0, 3, 8, 13, 24, 13, 11, 24, 24, - 13, 11, 25, 24, 27, 29, -1, -1, 24, -1, - -1, -1, 24, -1, -1, -1, 24, -1, 24, 26, - 24 + 10, 0, 3, 8, 13, 25, 13, 11, 24, 30, + 23, 13, 27, 26, 25, 28, 13, 11, 13, 25, + 13, 13, 25, -1, -1, 25, -1, 25, -1, 25, + -1, -1, -1, 24 }; /* YYSTOS[STATE-NUM] -- The (internal number of the) accessing symbol of state STATE-NUM. */ static const yytype_uint8 yystos[] = { - 0, 35, 36, 0, 3, 39, 13, 40, 37, 4, - 5, 10, 39, 41, 45, 8, 13, 24, 11, 6, - 7, 43, 13, 42, 38, 9, 10, 25, 27, 39, - 41, 44, 46, 47, 24, 24, 24, 11, 24, 29, - 24, 26, 24 + 0, 36, 37, 0, 3, 40, 13, 41, 38, 4, + 5, 10, 40, 42, 46, 8, 13, 25, 11, 6, + 7, 44, 13, 43, 39, 9, 10, 23, 26, 28, + 40, 42, 45, 47, 48, 49, 25, 13, 25, 25, + 11, 13, 25, 30, 25, 13, 27, 25, 13 }; /* YYR1[YYN] -- Symbol number of symbol that rule YYN derives. */ static const yytype_uint8 yyr1[] = { - 0, 34, 36, 35, 37, 37, 37, 37, 38, 38, - 38, 38, 38, 38, 40, 39, 42, 41, 43, 43, - 44, 45, 46, 46, 47 + 0, 35, 37, 36, 38, 38, 38, 38, 39, 39, + 39, 39, 39, 39, 39, 41, 40, 43, 42, 44, + 44, 45, 46, 47, 47, 48, 49, 49, 49 }; /* YYR2[YYN] -- Number of symbols on the right hand side of rule YYN. */ static const yytype_uint8 yyr2[] = { 0, 2, 0, 2, 2, 2, 2, 0, 2, 2, - 2, 2, 2, 0, 0, 5, 0, 7, 1, 1, - 4, 4, 3, 4, 4 + 2, 2, 2, 2, 0, 0, 5, 0, 7, 1, + 1, 4, 4, 3, 4, 4, 5, 4, 3 }; @@ -973,6 +975,7 @@ yysyntax_error (YYSIZE_T *yymsg_alloc, char **yymsg, case N: \ yyformat = S; \ break + default: /* Avoid compiler warnings. */ YYCASE_(0, YY_("syntax error")); YYCASE_(1, YY_("syntax error, unexpected %s")); YYCASE_(2, YY_("syntax error, unexpected %s, expecting %s")); @@ -1294,7 +1297,7 @@ yyreduce: break; - case 14: + case 15: { (yyval.chip_instance) = new_chip_instance((yyvsp[0].string)); @@ -1304,7 +1307,7 @@ yyreduce: break; - case 15: + case 16: { cur_chip_instance = chip_dequeue_tail(); @@ -1312,7 +1315,7 @@ yyreduce: break; - case 16: + case 17: { (yyval.dev) = new_device(cur_parent, cur_chip_instance, (yyvsp[-2].number), (yyvsp[-1].string), (yyvsp[0].number)); @@ -1321,7 +1324,7 @@ yyreduce: break; - case 17: + case 18: { cur_parent = (yyvsp[-2].dev)->parent; @@ -1329,36 +1332,54 @@ yyreduce: break; - case 20: + case 21: { add_resource(cur_parent, (yyvsp[-3].number), strtol((yyvsp[-2].string), NULL, 0), strtol((yyvsp[0].string), NULL, 0)); } break; - case 21: + case 22: { add_register(cur_chip_instance, (yyvsp[-2].string), (yyvsp[0].string)); } break; - case 22: + case 23: { add_pci_subsystem_ids(cur_parent, strtol((yyvsp[-1].string), NULL, 16), strtol((yyvsp[0].string), NULL, 16), 0); } break; - case 23: + case 24: { add_pci_subsystem_ids(cur_parent, strtol((yyvsp[-2].string), NULL, 16), strtol((yyvsp[-1].string), NULL, 16), 1); } break; - case 24: + case 25: { add_ioapic_info(cur_parent, strtol((yyvsp[-2].string), NULL, 16), (yyvsp[-1].string), strtol((yyvsp[0].string), NULL, 16)); } break; + case 26: + + { add_slot_desc(cur_parent, (yyvsp[-3].string), (yyvsp[-2].string), (yyvsp[-1].string), (yyvsp[0].string)); } + + break; + + case 27: + + { add_slot_desc(cur_parent, (yyvsp[-2].string), (yyvsp[-1].string), (yyvsp[0].string), NULL); } + + break; + + case 28: + + { add_slot_desc(cur_parent, (yyvsp[-1].string), (yyvsp[0].string), NULL, NULL); } + + break; + default: break; diff --git a/util/sconfig/sconfig.tab.h_shipped b/util/sconfig/sconfig.tab.h_shipped index cabc4743b8..bcbd644b01 100644 --- a/util/sconfig/sconfig.tab.h_shipped +++ b/util/sconfig/sconfig.tab.h_shipped @@ -1,8 +1,8 @@ -/* A Bison parser, made by GNU Bison 3.0.4. */ +/* A Bison parser, made by GNU Bison 3.0.5. */ /* Bison interface for Yacc-like parsers in C - Copyright (C) 1984, 1989-1990, 2000-2015 Free Software Foundation, Inc. + Copyright (C) 1984, 1989-1990, 2000-2015, 2018 Free Software Foundation, Inc. This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by @@ -65,17 +65,18 @@ extern int yydebug; DOMAIN = 275, IRQ = 276, DRQ = 277, - IO = 278, - NUMBER = 279, - SUBSYSTEMID = 280, - INHERIT = 281, - IOAPIC_IRQ = 282, - IOAPIC = 283, - PCIINT = 284, - GENERIC = 285, - SPI = 286, - USB = 287, - MMIO = 288 + SLOT_DESC = 278, + IO = 279, + NUMBER = 280, + SUBSYSTEMID = 281, + INHERIT = 282, + IOAPIC_IRQ = 283, + IOAPIC = 284, + PCIINT = 285, + GENERIC = 286, + SPI = 287, + USB = 288, + MMIO = 289 }; #endif diff --git a/util/sconfig/sconfig.y b/util/sconfig/sconfig.y index 3a6e9ab8a3..0d894a9e35 100755 --- a/util/sconfig/sconfig.y +++ b/util/sconfig/sconfig.y @@ -31,13 +31,13 @@ static struct chip_instance *cur_chip_instance; int number; } -%token CHIP DEVICE REGISTER BOOL HIDDEN BUS RESOURCE END EQUALS HEX STRING PCI PNP I2C APIC CPU_CLUSTER CPU DOMAIN IRQ DRQ IO NUMBER SUBSYSTEMID INHERIT IOAPIC_IRQ IOAPIC PCIINT GENERIC SPI USB MMIO +%token CHIP DEVICE REGISTER BOOL HIDDEN BUS RESOURCE END EQUALS HEX STRING PCI PNP I2C APIC CPU_CLUSTER CPU DOMAIN IRQ DRQ SLOT_DESC IO NUMBER SUBSYSTEMID INHERIT IOAPIC_IRQ IOAPIC PCIINT GENERIC SPI USB MMIO %% devtree: { cur_parent = root_parent; } chip; chipchildren: chipchildren device | chipchildren chip | chipchildren registers | /* empty */ ; -devicechildren: devicechildren device | devicechildren chip | devicechildren resource | devicechildren subsystemid | devicechildren ioapic_irq | /* empty */ ; +devicechildren: devicechildren device | devicechildren chip | devicechildren resource | devicechildren subsystemid | devicechildren ioapic_irq | devicechildren smbios_slot_desc | /* empty */ ; chip: CHIP STRING /* == path */ { $$ = new_chip_instance($2); @@ -72,4 +72,14 @@ subsystemid: SUBSYSTEMID NUMBER NUMBER INHERIT ioapic_irq: IOAPIC_IRQ NUMBER PCIINT NUMBER { add_ioapic_info(cur_parent, strtol($2, NULL, 16), $3, strtol($4, NULL, 16)); }; + +smbios_slot_desc: SLOT_DESC STRING STRING STRING STRING + { add_slot_desc(cur_parent, $2, $3, $4, $5); }; + +smbios_slot_desc: SLOT_DESC STRING STRING STRING + { add_slot_desc(cur_parent, $2, $3, $4, NULL); }; + +smbios_slot_desc: SLOT_DESC STRING STRING + { add_slot_desc(cur_parent, $2, $3, NULL, NULL); }; + %%