s4880
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1305 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Ronald G. Minnich
221
src/mainboard/tyan/s4880/Config.lb
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221
src/mainboard/tyan/s4880/Config.lb
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uses HAVE_MP_TABLE
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uses HAVE_PIRQ_TABLE
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uses USE_FALLBACK_IMAGE
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uses MAINBOARD
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uses ARCH
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#
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#
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###
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### Set all of the defaults for an x86 architecture
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###
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#
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#
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###
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### Build the objects we have code for in this directory.
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###
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##object mainboard.o
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config chip.h
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#register "fixup_scsi" = "1"
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#register "fixup_vga" = "1"
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driver mainboard.o
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driver lsi_scsi.o
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#driver adaptec_scsi.o
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driver si_sata.o
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#driver intel_nic.o
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object reset.o
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if HAVE_MP_TABLE object mptable.o end
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if HAVE_PIRQ_TABLE object irq_tables.o end
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#
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arch i386 end
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#cpu k8 end
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#
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###
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### Build our 16 bit and 32 bit linuxBIOS entry code
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###
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mainboardinit cpu/i386/entry16.inc
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mainboardinit cpu/i386/entry32.inc
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ldscript /cpu/i386/entry16.lds
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ldscript /cpu/i386/entry32.lds
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#
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###
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### Build our reset vector (This is where linuxBIOS is entered)
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###
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if USE_FALLBACK_IMAGE
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mainboardinit cpu/i386/reset16.inc
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ldscript /cpu/i386/reset16.lds
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else
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mainboardinit cpu/i386/reset32.inc
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ldscript /cpu/i386/reset32.lds
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end
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#
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#### Should this be in the northbridge code?
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mainboardinit arch/i386/lib/cpu_reset.inc
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#
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###
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### Include an id string (For safe flashing)
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###
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mainboardinit arch/i386/lib/id.inc
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ldscript /arch/i386/lib/id.lds
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#
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####
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#### This is the early phase of linuxBIOS startup
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#### Things are delicate and we test to see if we should
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#### failover to another image.
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####
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#option MAX_REBOOT_CNT=2
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if USE_FALLBACK_IMAGE
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ldscript /arch/i386/lib/failover.lds
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end
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#
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###
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### Setup our mtrrs
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###
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mainboardinit cpu/k8/earlymtrr.inc
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###
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### Only the bootstrap cpu makes it here.
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### Failover if we need to
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###
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#
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if USE_FALLBACK_IMAGE
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mainboardinit ./failover.inc
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end
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#
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#
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###
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### Setup the serial port
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###
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#mainboardinit superiowinbond/w83627hf/setup_serial.inc
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mainboardinit pc80/serial.inc
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mainboardinit arch/i386/lib/console.inc
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#
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####
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#### O.k. We aren't just an intermediary anymore!
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####
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#
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###
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### When debugging disable the watchdog timer
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###
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##option MAXIMUM_CONSOLE_LOGLEVEL=7
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#default MAXIMUM_CONSOLE_LOGLEVEL=7
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#
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#if USE_FALLBACK_IMAGE mainboardinit arch/i386/lib/noop_failover.inc end
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#
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###
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### Romcc output
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###
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#makerule ./failover.E dep "$(MAINBOARD)/failover.c" act "$(CPP) -I$(TOP)/src $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failever.E"
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#makerule ./failover.inc dep "./romcc ./failover.E" act "./romcc -O ./failover.E > failover.inc"
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#mainboardinit .failover.inc
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makerule ./failover.E
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depends "$(MAINBOARD)/failover.c"
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action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
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end
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makerule ./failover.inc
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depends "./romcc ./failover.E"
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action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"end
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makerule ./auto.E
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depends "$(MAINBOARD)/auto.c"
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action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
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end
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makerule ./auto.inc
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depends "./romcc ./auto.E"
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action "./romcc -O -mcpu=k8 -o auto.inc --label-prefix=auto ./auto.E"
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# action "./romcc -mcpu=k8 -O ./auto.E > auto.inc"
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end
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mainboardinit cpu/k8/enable_mmx_sse.inc
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mainboardinit ./auto.inc
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mainboardinit cpu/k8/disable_mmx_sse.inc
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#
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###
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### Include the secondary Configuration files
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###
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northbridge amd/amdk8 "mc0"
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pci 0:18.0
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pci 0:18.0
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pci 0:18.0
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pci 0:18.1
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pci 0:18.2
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pci 0:18.3
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southbridge amd/amd8131 "amd8131" link 2
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pci 0:0.0
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pci 0:0.1
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pci 0:1.0
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pci 0:1.1
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end
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southbridge amd/amd8111 "amd8111" link 2
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pci 0:0.0
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pci 0:1.0 on
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pci 0:1.1 on
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pci 0:1.2 on
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pci 0:1.3 on
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pci 0:1.5 off
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pci 0:1.6 off
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pci 1:0.0 on
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pci 1:0.1 on
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pci 1:0.2 on
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pci 1:1.0 off
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end
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end
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northbridge amd/amdk8 "mc1"
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pci 0:19.0
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pci 0:19.0
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pci 0:19.0
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pci 0:19.1
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pci 0:19.2
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pci 0:19.3
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end
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northbridge amd/amdk8 "mc2"
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pci 0:1a.0
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pci 0:1a.0
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pci 0:1a.0
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pci 0:1a.1
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pci 0:1a.2
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pci 0:1a.3
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end
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northbridge amd/amdk8 "mc3"
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pci 0:1b.0
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pci 0:1b.0
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pci 0:1b.0
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pci 0:1b.1
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pci 0:1b.2
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pci 0:1b.3
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end
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#northbridge amd/amdk8
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#end
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#southbridge amd/amd8111 "amd8111"
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#end
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#southbridge amd/amd8131 "amd8131"
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#end
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#mainboardinit archi386/smp/secondary.inc
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#superio NSC/pc87360
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# register "com1" = "{1}"
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# register "lpt" = "{1}"
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#end
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dir /pc80
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##dir /src/superio/winbond/w83627hf
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#dir /bioscall
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#dir /cpu/k8
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cpu k8 "cpu0"
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register "up" = "{.chip = &amd8131, .ht_width=16, .ht_speed=600}"
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end
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cpu k8 "cpu1"
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end
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cpu k8 "cpu2"
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end
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cpu k8 "cpu3"
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end
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