From 130a3b0281ea92561f735bcd93ffc4c736f000a1 Mon Sep 17 00:00:00 2001
From: Jeremy Soller <jeremy@system76.com>
Date: Wed, 18 Nov 2020 20:27:00 -0700
Subject: [PATCH] WIP: undo changes that might impact CPU PCIe

Change-Id: Ied4e4ed4c11172a9bb1c7aa47787ba6fb7e72803
---
 src/soc/intel/tigerlake/acpi/pci_irqs.asl     |  6 ------
 src/soc/intel/tigerlake/acpi/pcie.asl         | 10 ----------
 src/soc/intel/tigerlake/chip.c                |  1 -
 src/soc/intel/tigerlake/fsp_params.c          |  6 ------
 src/soc/intel/tigerlake/romstage/fsp_params.c |  3 ---
 5 files changed, 26 deletions(-)

diff --git a/src/soc/intel/tigerlake/acpi/pci_irqs.asl b/src/soc/intel/tigerlake/acpi/pci_irqs.asl
index 8fe0d4648e..6f5f4bc3fd 100644
--- a/src/soc/intel/tigerlake/acpi/pci_irqs.asl
+++ b/src/soc/intel/tigerlake/acpi/pci_irqs.asl
@@ -67,9 +67,6 @@ Name (PICP, Package () {
 	Package(){0x0007FFFF, 3, 0, 19 },
 	/* D6 */
 	Package(){0x0006FFFF, 0, 0, 16 },
-	Package(){0x0006FFFF, 1, 0, 17 },
-	Package(){0x0006FFFF, 2, 0, 18 },
-	Package(){0x0006FFFF, 3, 0, 19 },
 	/* D5 */
 	Package(){0x0005FFFF, 0, 0, 16 },
 	/* D4 */
@@ -145,9 +142,6 @@ Name (PICN, Package () {
 	Package(){0x0007FFFF, 3, 0, 11 },
 	/* D6 */
 	Package(){0x0006FFFF, 0, 0, 11 },
-	Package(){0x0006FFFF, 1, 0, 10 },
-	Package(){0x0006FFFF, 2, 0, 11 },
-	Package(){0x0006FFFF, 3, 0, 11 },
 	/* D5 */
 	Package(){0x0005FFFF, 0, 0, 11 },
 	/* D4 */
diff --git a/src/soc/intel/tigerlake/acpi/pcie.asl b/src/soc/intel/tigerlake/acpi/pcie.asl
index 7ad1468e0b..a19feb7168 100644
--- a/src/soc/intel/tigerlake/acpi/pcie.asl
+++ b/src/soc/intel/tigerlake/acpi/pcie.asl
@@ -96,16 +96,6 @@ Method (IRQM, 1, Serialized) {
 	}
 }
 
-Device (PEG0)
-{
-	Name (_ADR, 0x00060000)
-
-	Method (_PRT)
-	{
-		Return (IRQM (1))
-	}
-}
-
 Device (RP01)
 {
 	Name (_ADR, 0x001C0000)
diff --git a/src/soc/intel/tigerlake/chip.c b/src/soc/intel/tigerlake/chip.c
index 53fc528446..62201a2f4f 100644
--- a/src/soc/intel/tigerlake/chip.c
+++ b/src/soc/intel/tigerlake/chip.c
@@ -66,7 +66,6 @@ const char *soc_acpi_name(const struct device *dev)
 
 	switch (dev->path.pci.devfn) {
 	case SA_DEVFN_ROOT:		return "MCHC";
-	case SA_DEVFN_CPU_PCIE:		return "PEG0";
 	case SA_DEVFN_TCSS_XDCI:	return "TXDC";
 	case SA_DEVFN_TBT0:		return "TRP0";
 	case SA_DEVFN_TBT1:		return "TRP1";
diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c
index 3e82bbb4d3..cd0ada6dcc 100644
--- a/src/soc/intel/tigerlake/fsp_params.c
+++ b/src/soc/intel/tigerlake/fsp_params.c
@@ -194,12 +194,6 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 	memcpy(params->PcieRpClkReqDetect, config->PcieRpClkReqDetect,
 		sizeof(config->PcieRpClkReqDetect));
 
-	/* TODO: CPU RP Configs */
-	for (i = 0; i < 4; i++) {
-		params->CpuPcieRpAdvancedErrorReporting[i] = 0;
-		params->CpuPcieRpPtmEnabled[i] = 0;
-	}
-
 	/* Enable xDCI controller if enabled in devicetree and allowed */
 	dev = pcidev_path_on_root(PCH_DEVFN_USBOTG);
 	if (dev) {
diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c
index bdb6042f95..dc9caee9fb 100644
--- a/src/soc/intel/tigerlake/romstage/fsp_params.c
+++ b/src/soc/intel/tigerlake/romstage/fsp_params.c
@@ -212,9 +212,6 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
 	dev = pcidev_path_on_root(SA_DEVFN_CPU_PCIE);
 	m_cfg->CpuPcieRpEnableMask = dev && dev->enabled;
 
-	/* Disable clock req messaging */
-	m_cfg->CpuPcieRpClockReqMsgEnable = 0;
-
 	/* Change TmeEnable UPD value according to INTEL_TME Kconfig */
 	m_cfg->TmeEnable = CONFIG(INTEL_TME);
 }